diff options
| author | Jeff Law <jeffreyalaw@gmail.com> | 2023-12-01 07:19:50 -0700 |
|---|---|---|
| committer | Jeff Law <jeffreyalaw@gmail.com> | 2023-12-01 07:19:50 -0700 |
| commit | 37d6ee9350c68c1f9688eeb030e3585b548fec81 (patch) | |
| tree | d8d13ae34a82808e783fb42df6b80a08e476a066 /sim/mcore | |
| parent | fbd9e35c5436108732575e82e78cc42be5ba52f5 (diff) | |
| download | gdb-37d6ee9350c68c1f9688eeb030e3585b548fec81.zip gdb-37d6ee9350c68c1f9688eeb030e3585b548fec81.tar.gz gdb-37d6ee9350c68c1f9688eeb030e3585b548fec81.tar.bz2 | |
Fix right shifts in mcore simulator on 64 bit hosts.
If the value to be shifted has the sign bit set, the sign
bit would get copied into bits 32..63 of the temporary. Those
would then be right shifted into the final value giving an
incorrect final result.
This was observed with upcoming GCC improvements which eliminate
unnecessary extensions.
Diffstat (limited to 'sim/mcore')
| -rw-r--r-- | sim/mcore/interp.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c index 48d9ff8..7561c44 100644 --- a/sim/mcore/interp.c +++ b/sim/mcore/interp.c @@ -757,7 +757,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) break; case 0x0B: /* lsr */ { - unsigned long dst, src; + uint32_t dst, src; dst = gr[RD]; src = gr[RS]; /* We must not rely solely upon the native shift operations, since they @@ -1060,7 +1060,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) case 0x3E: case 0x3F: /* lsrc, lsri */ { unsigned imm = IMM5; - unsigned long tmp = gr[RD]; + uint32_t tmp = gr[RD]; if (imm == 0) { NEW_C (tmp); |