diff options
| -rw-r--r-- | sim/mcore/interp.c | 4 | ||||
| -rw-r--r-- | sim/testsuite/mcore/lsr.s | 28 | ||||
| -rw-r--r-- | sim/testsuite/mcore/lsri.s | 25 |
3 files changed, 55 insertions, 2 deletions
diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c index 48d9ff8..7561c44 100644 --- a/sim/mcore/interp.c +++ b/sim/mcore/interp.c @@ -757,7 +757,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) break; case 0x0B: /* lsr */ { - unsigned long dst, src; + uint32_t dst, src; dst = gr[RD]; src = gr[RS]; /* We must not rely solely upon the native shift operations, since they @@ -1060,7 +1060,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu) case 0x3E: case 0x3F: /* lsrc, lsri */ { unsigned imm = IMM5; - unsigned long tmp = gr[RD]; + uint32_t tmp = gr[RD]; if (imm == 0) { NEW_C (tmp); diff --git a/sim/testsuite/mcore/lsr.s b/sim/testsuite/mcore/lsr.s new file mode 100644 index 0000000..a9a76aa --- /dev/null +++ b/sim/testsuite/mcore/lsr.s @@ -0,0 +1,28 @@ +# check that lsr works correctly +# mach: mcore + +.include "testutils.inc" + + start + # Construct -1 + bmaski r2, 32 + + # Construct 24 + movi r3, 24 + + # logical shift right by r3 (24) + lsr r2, r3 + + # Construct 255 + bmaski r1, 8 + + # Compare them, they should be equal + cmpne r2,r1 + jbt .L1 + pass +.L1: + fail + + + + diff --git a/sim/testsuite/mcore/lsri.s b/sim/testsuite/mcore/lsri.s new file mode 100644 index 0000000..bb7bec6 --- /dev/null +++ b/sim/testsuite/mcore/lsri.s @@ -0,0 +1,25 @@ +# check that lsri works correctly +# mach: mcore + +.include "testutils.inc" + + start + # Construct -1 + bmaski r2, 32 + + # logical shift right by 24 + lsri r2, 24 + + # Construct 255 + bmaski r1, 8 + + # Compare them, they should be equal + cmpne r2,r1 + jbt .L1 + pass +.L1: + fail + + + + |