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| author | Bernd Schmidt <bernds@codesourcery.com> | 2008-03-26 16:21:10 +0000 |
|---|---|---|
| committer | Bernd Schmidt <bernds@codesourcery.com> | 2008-03-26 16:21:10 +0000 |
| commit | ee171c8f9472821b181ceaec7d78bb266d3291d4 (patch) | |
| tree | 87c15fa68dd0cd2d7d10539264c0e736cf3e834c /opcodes | |
| parent | c183e9618cf196b24dac78bb6174f480259830f7 (diff) | |
| download | gdb-ee171c8f9472821b181ceaec7d78bb266d3291d4.zip gdb-ee171c8f9472821b181ceaec7d78bb266d3291d4.tar.gz gdb-ee171c8f9472821b181ceaec7d78bb266d3291d4.tar.bz2 | |
gas/
* config/bfin-parse.y (check_macfunc_option): Allow (IU)
option for multiply and multiply-accumulate to data register
instruction.
(check_macfuncs): Don't check if accumulator matches the data register
here.
(assign_macfunc): Check if accumulator matches the
data register in each rule that moves to the data
register.
gas/testsuite/
* gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check
for IU option.
* gas/bfin/expected_errors.l, gas/bfin/expected_errors.s:
Add check for mismatch of accumulator and data register.
opcodes/
* bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
multiply and multiply-accumulate to data register instruction.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/bfin-dis.c | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 95336e6..8360494 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -16,6 +16,10 @@ (get_allreg): New. (decode_LDIMMhalf_0): Print out the whole register value. + From Jie Zhang <jie.zhang@analog.com> + * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for + multiply and multiply-accumulate to data register instruction. + 2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> * aclocal.m4: Regenerate. diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c index 09152ee..046027e 100644 --- a/opcodes/bfin-dis.c +++ b/opcodes/bfin-dis.c @@ -2755,7 +2755,7 @@ decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf) if ((w1 || w0) && mmod == M_W32) return 0; - if (((1 << mmod) & (P ? 0x31b : 0x1b5f)) == 0) + if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0) return 0; if (w1 == 1 || op1 != 3) |