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authorKyrylo Tkachov <ktkachov@sourceware.org>2013-03-11 11:09:33 +0000
committerKyrylo Tkachov <ktkachov@sourceware.org>2013-03-11 11:09:33 +0000
commitdd5181d57f54aba7df0cee40028b9b446ef55f57 (patch)
treeea975d618fc936f9cb625ab747620f1212b2a2c2 /opcodes
parent2f1d9bddccc54e02e2c5a94e8aa21e3c2f430068 (diff)
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Add support for AArch32 CRC instruction in ARMv8.
gas/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/tc-arm.c (crc_ext_armv8): New feature set. (UNPRED_REG): New macro. (do_crc32_1): New function. (do_crc32b, do_crc32h, do_crc32w, do_crc32cb, do_crc32ch, do_crc32cw): Likewise. (TUEc): New macro. (insns): Add entries for crc32 mnemonics. (arm_extensions): Add entry for crc. include/opcode/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm.h (CRC_EXT_ARMV8): New constant. (ARCH_CRC_ARMV8): New macro. opcodes/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * arm-dis.c (arm_opcodes): Add entries for CRC instructions. (thumb32_opcodes): Likewise. (print_insn_thumb32): Handle 'S' control char. gas/testsuite/ChangeLog 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gas/arm/crc32-bad.d: New file. * gas/arm/crc32-bad.l: Likewise. * gas/arm/crc32-bad.s: Likewise. * gas/arm/crc32.d: Likewise. * gas/arm/crc32.s: Likewise.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/arm-dis.c22
2 files changed, 27 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f311e1d..d7fe4a5 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
+ (thumb32_opcodes): Likewise.
+ (print_insn_thumb32): Handle 'S' control char.
+
2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
* lm32-desc.c: Regenerate.
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index ad7a67f..0b1ed1a 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -903,6 +903,13 @@ static const struct opcode32 arm_opcodes[] =
{ARM_EXT_V8, 0x01d00c9f, 0x0ff00fff, "ldab%c\t%12-15r, [%16-19R]"},
{ARM_EXT_V8, 0x01e0fc90, 0x0ff0fff0, "stlh%c\t%0-3r, [%16-19R]"},
{ARM_EXT_V8, 0x01f00c9f, 0x0ff00fff, "ldaexh%c\t%12-15r, [%16-19R]"},
+ /* CRC32 instructions. */
+ {CRC_EXT_ARMV8, 0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
+ {CRC_EXT_ARMV8, 0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
+ {CRC_EXT_ARMV8, 0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
+ {CRC_EXT_ARMV8, 0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
+ {CRC_EXT_ARMV8, 0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
+ {CRC_EXT_ARMV8, 0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
/* Virtualization Extension instructions. */
{ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
@@ -1455,7 +1462,8 @@ static const struct opcode16 thumb_opcodes[] =
%<bitfield>d print bitfield in decimal
%<bitfield>W print bitfield*4 in decimal
%<bitfield>r print bitfield as an ARM register
- %<bitfield>R as %<>r bit r15 is UNPREDICTABLE
+ %<bitfield>R as %<>r but r15 is UNPREDICTABLE
+ %<bitfield>S as %<>R but r13 is UNPREDICTABLE
%<bitfield>c print bitfield as a condition code
%<bitfield>'c print specified char iff bitfield is all ones
@@ -1490,6 +1498,14 @@ static const struct opcode32 thumb32_opcodes[] =
{ARM_EXT_V8, 0xe8d00fef, 0xfff00fff, "ldaex%c\t%12-15r, [%16-19R]"},
{ARM_EXT_V8, 0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
+ /* CRC32 instructions. */
+ {CRC_EXT_ARMV8, 0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11S, %16-19S, %0-3S"},
+ {CRC_EXT_ARMV8, 0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11S, %16-19S, %0-3S"},
+ {CRC_EXT_ARMV8, 0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11S, %16-19S, %0-3S"},
+ {CRC_EXT_ARMV8, 0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11S, %16-19S, %0-3S"},
+ {CRC_EXT_ARMV8, 0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11S, %16-19S, %0-3S"},
+ {CRC_EXT_ARMV8, 0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11S, %16-19S, %0-3S"},
+
/* V7 instructions. */
{ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
{ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
@@ -4427,6 +4443,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
value_in_comment = val * 4;
break;
+ case 'S':
+ if (val == 13)
+ is_unpredictable = TRUE;
+ /* Fall through. */
case 'R':
if (val == 15)
is_unpredictable = TRUE;