Add support for the Infineon XC16X.

13 files changed, 10741 insertions, 4 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f36656c..d6c9096 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,20 @@
+2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
+            Anil Paranjape   <anilp1@kpitcummins.com>
+            Shilin Shakti    <shilins@kpitcummins.com>
+
+	* xc16x-desc.h: New file
+	* xc16x-desc.c: New file
+	* xc16x-opc.h: New file	
+	* xc16x-opc.c: New file
+	* xc16x-ibld.c: New file
+	* xc16x-asm.c: New file
+	* xc16x-dis.c: New file
+	* Makefile.am: Entries for xc16x 
+	* Makefile.in: Regenerate 
+	* cofigure.in: Add xc16x target information.
+	* configure: Regenerate.
+	* disassemble.c: Add xc16x target information.
+
 2006-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386-dis.c (dis386_twobyte): Use "movZ" for debug register
diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 4df0445..8d03307 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -42,6 +42,7 @@ HFILES = \
 	sh64-opc.h \
 	sysdep.h \
 	w65-opc.h \
+	xc16x-desc.h xc16x-opc.h \
 	xstormy16-desc.h xstormy16-opc.h \
 	z8k-opc.h
 
@@ -173,6 +174,11 @@ CFILES = \
 	v850-opc.c \
 	vax-dis.c \
 	w65-dis.c \
+	xc16x-asm.c \
+	xc16x-desc.c \
+	xc16x-dis.c \
+	xc16x-ibld.c \
+	xc16x-opc.c \
 	xstormy16-asm.c \
 	xstormy16-desc.c \
 	xstormy16-dis.c \
@@ -299,6 +305,11 @@ ALL_MACHINES = \
 	v850-opc.lo \
 	vax-dis.lo \
 	w65-dis.lo \
+	xc16x-asm.lo \
+	xc16x-desc.lo \
+	xc16x-dis.lo \
+	xc16x-ibld.lo \
+	xc16x-opc.lo \
 	xstormy16-asm.lo \
 	xstormy16-desc.lo \
 	xstormy16-dis.lo \
@@ -378,7 +389,7 @@ uninstall_libopcodes:
 
 CLEANFILES = \
 	stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \
-	stamp-openrisc stamp-iq2000 stamp-mt stamp-xstormy16 \
+	stamp-openrisc stamp-iq2000 stamp-mt stamp-xstormy16 stamp-xc16x\
 	libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
 
 
@@ -394,7 +405,7 @@ CGENDEPS = \
 	$(CGENDIR)/opc-opinst.scm \
 	cgen-asm.in cgen-dis.in cgen-ibld.in
 
-CGEN_CPUS = fr30 frv ip2k m32c m32r mt openrisc xstormy16
+CGEN_CPUS = fr30 frv ip2k m32c m32r mt openrisc xc16x xstormy16
 
 if CGEN_MAINT
 IP2K_DEPS = stamp-ip2k
@@ -405,6 +416,7 @@ FRV_DEPS = stamp-frv
 MT_DEPS = stamp-mt
 OPENRISC_DEPS = stamp-openrisc
 IQ2000_DEPS = stamp-iq2000
+XC16X_DEPS = stamp-xc16x
 XSTORMY16_DEPS = stamp-xstormy16
 else
 IP2K_DEPS =
@@ -415,6 +427,7 @@ FRV_DEPS =
 MT_DEPS =
 OPENRISC_DEPS = 
 IQ2000_DEPS = 
+XC16X_DEPS = 
 XSTORMY16_DEPS = 
 endif
 
@@ -512,6 +525,12 @@ stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc
 	$(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= \
 		archfile=$(CPUDIR)/xstormy16.cpu opcfile=$(CPUDIR)/xstormy16.opc extrafiles=
 
+$(srcdir)/xc16x-desc.h $(srcdir)/xc16x-desc.c $(srcdir)/xc16x-opc.h $(srcdir)/xc16x-opc.c $(srcdir)/xc16x-ibld.c $(srcdir)/xc16x-asm.c $(srcdir)/xc16x-dis.c: $(XC16X_DEPS)
+	@true
+stamp-xc16x: $(CGENDEPS) $(CPUDIR)/xc16x.cpu $(CPUDIR)/xc16x.opc
+	$(MAKE) run-cgen arch=xc16x prefix=xc16x options= \
+		archfile=$(CPUDIR)/xc16x.cpu opcfile=$(CPUDIR)/xc16x.opc extrafiles=
+
 ia64-gen: ia64-gen.o
 	$(LINK) ia64-gen.o $(LIBIBERTY)
 
@@ -974,6 +993,23 @@ xstormy16-opc.lo: xstormy16-opc.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
   xstormy16-opc.h $(INCDIR)/libiberty.h
+xc16x-asm.lo: xc16x-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(BFD_H) $(INCDIR)/symcat.h xc16x-desc.h $(INCDIR)/opcode/cgen.h \
+  xc16x-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+xc16x-desc.lo: xc16x-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(BFD_H) $(INCDIR)/symcat.h xc16x-desc.h $(INCDIR)/opcode/cgen.h \
+  xc16x-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \
+  $(INCDIR)/xregex2.h
+xc16x-dis.lo: xc16x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
+  xc16x-desc.h $(INCDIR)/opcode/cgen.h xc16x-opc.h opintl.h
+xc16x-ibld.lo: xc16x-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h xc16x-desc.h \
+  $(INCDIR)/opcode/cgen.h xc16x-opc.h opintl.h $(INCDIR)/safe-ctype.h
+xc16x-opc.lo: xc16x-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(BFD_H) $(INCDIR)/symcat.h xc16x-desc.h $(INCDIR)/opcode/cgen.h \
+  xc16x-opc.h $(INCDIR)/libiberty.h 
 xtensa-dis.lo: xtensa-dis.c $(INCDIR)/xtensa-isa.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h sysdep.h \
   config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in
index 69ccc96..a28ff0e 100644
--- a/opcodes/Makefile.in
+++ b/opcodes/Makefile.in
@@ -263,6 +263,7 @@ HFILES = \
 	sh64-opc.h \
 	sysdep.h \
 	w65-opc.h \
+	xc16x-desc.h xc16x-opc.h \
 	xstormy16-desc.h xstormy16-opc.h \
 	z8k-opc.h
 
@@ -395,6 +396,11 @@ CFILES = \
 	v850-opc.c \
 	vax-dis.c \
 	w65-dis.c \
+	xc16x-asm.c \
+	xc16x-desc.c \
+	xc16x-dis.c \
+	xc16x-ibld.c \
+	xc16x-opc.c \
 	xstormy16-asm.c \
 	xstormy16-desc.c \
 	xstormy16-dis.c \
@@ -521,6 +527,11 @@ ALL_MACHINES = \
 	v850-opc.lo \
 	vax-dis.lo \
 	w65-dis.lo \
+	xc16x-asm.lo \
+	xc16x-desc.lo \
+	xc16x-dis.lo \
+	xc16x-ibld.lo \
+	xc16x-opc.lo \
 	xstormy16-asm.lo \
 	xstormy16-desc.lo \
 	xstormy16-dis.lo \
@@ -554,7 +565,7 @@ noinst_LIBRARIES = libopcodes.a
 POTFILES = $(HFILES) $(CFILES)
 CLEANFILES = \
 	stamp-ip2k stamp-m32c stamp-m32r stamp-fr30 stamp-frv \
-	stamp-openrisc stamp-iq2000 stamp-mt stamp-xstormy16 \
+	stamp-openrisc stamp-iq2000 stamp-mt stamp-xstormy16 stamp-xc16x\
 	libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2
 
 CGENDIR = @cgendir@
@@ -568,7 +579,7 @@ CGENDEPS = \
 	$(CGENDIR)/opc-opinst.scm \
 	cgen-asm.in cgen-dis.in cgen-ibld.in
 
-CGEN_CPUS = fr30 frv ip2k m32c m32r mt openrisc xstormy16
+CGEN_CPUS = fr30 frv ip2k m32c m32r mt openrisc xc16x xstormy16
 @CGEN_MAINT_FALSE@IP2K_DEPS = 
 @CGEN_MAINT_TRUE@IP2K_DEPS = stamp-ip2k
 @CGEN_MAINT_FALSE@M32C_DEPS = 
@@ -585,6 +596,8 @@ CGEN_CPUS = fr30 frv ip2k m32c m32r mt openrisc xstormy16
 @CGEN_MAINT_TRUE@OPENRISC_DEPS = stamp-openrisc
 @CGEN_MAINT_FALSE@IQ2000_DEPS = 
 @CGEN_MAINT_TRUE@IQ2000_DEPS = stamp-iq2000
+@CGEN_MAINT_FALSE@XC16X_DEPS = 
+@CGEN_MAINT_TRUE@XC16X_DEPS = stamp-xc16x
 @CGEN_MAINT_FALSE@XSTORMY16_DEPS = 
 @CGEN_MAINT_TRUE@XSTORMY16_DEPS = stamp-xstormy16
 m32c_opc_h = m32c-opc.h cgen-types.h cgen-ops.h
@@ -1054,6 +1067,12 @@ stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc
 	$(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= \
 		archfile=$(CPUDIR)/xstormy16.cpu opcfile=$(CPUDIR)/xstormy16.opc extrafiles=
 
+$(srcdir)/xc16x-desc.h $(srcdir)/xc16x-desc.c $(srcdir)/xc16x-opc.h $(srcdir)/xc16x-opc.c $(srcdir)/xc16x-ibld.c $(srcdir)/xc16x-asm.c $(srcdir)/xc16x-dis.c: $(XC16X_DEPS)
+	@true
+stamp-xc16x: $(CGENDEPS) $(CPUDIR)/xc16x.cpu $(CPUDIR)/xc16x.opc
+	$(MAKE) run-cgen arch=xc16x prefix=xc16x options= \
+		archfile=$(CPUDIR)/xc16x.cpu opcfile=$(CPUDIR)/xc16x.opc extrafiles=
+
 ia64-gen: ia64-gen.o
 	$(LINK) ia64-gen.o $(LIBIBERTY)
 
@@ -1516,6 +1535,23 @@ xstormy16-opc.lo: xstormy16-opc.c sysdep.h config.h \
   $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \
   $(INCDIR)/opcode/cgen-bitset.h $(INCDIR)/opcode/cgen.h \
   xstormy16-opc.h $(INCDIR)/libiberty.h
+xc16x-asm.lo: xc16x-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(BFD_H) $(INCDIR)/symcat.h xc16x-desc.h $(INCDIR)/opcode/cgen.h \
+  xc16x-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \
+  $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h
+xc16x-desc.lo: xc16x-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(BFD_H) $(INCDIR)/symcat.h xc16x-desc.h $(INCDIR)/opcode/cgen.h \
+  xc16x-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \
+  $(INCDIR)/xregex2.h
+xc16x-dis.lo: xc16x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \
+  xc16x-desc.h $(INCDIR)/opcode/cgen.h xc16x-opc.h opintl.h
+xc16x-ibld.lo: xc16x-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h xc16x-desc.h \
+  $(INCDIR)/opcode/cgen.h xc16x-opc.h opintl.h $(INCDIR)/safe-ctype.h
+xc16x-opc.lo: xc16x-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \
+  $(BFD_H) $(INCDIR)/symcat.h xc16x-desc.h $(INCDIR)/opcode/cgen.h \
+  xc16x-opc.h $(INCDIR)/libiberty.h 
 xtensa-dis.lo: xtensa-dis.c $(INCDIR)/xtensa-isa.h \
   $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h sysdep.h \
   config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h
diff --git a/opcodes/configure b/opcodes/configure
index a24d066..b692e83 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -8875,6 +8875,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_vax_arch)		ta="$ta vax-dis.lo" ;;
 	bfd_w65_arch)		ta="$ta w65-dis.lo" ;;
 	bfd_we32k_arch)		;;
+	bfd_xc16x_arch)		ta="$ta xc16x-asm.lo xc16x-desc.lo xc16x-dis.lo xc16x-ibld.lo xc16x-opc.lo" using_cgen=yes ;;
 	bfd_xstormy16_arch)	ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;;
 	bfd_xtensa_arch)	ta="$ta xtensa-dis.lo" ;;
 	bfd_z80_arch)		ta="$ta z80-dis.lo" ;;
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 4915671..d19d23c 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -227,6 +227,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_vax_arch)		ta="$ta vax-dis.lo" ;;
 	bfd_w65_arch)		ta="$ta w65-dis.lo" ;;
 	bfd_we32k_arch)		;;
+	bfd_xc16x_arch)		ta="$ta xc16x-asm.lo xc16x-desc.lo xc16x-dis.lo xc16x-ibld.lo xc16x-opc.lo" using_cgen=yes ;;
 	bfd_xstormy16_arch)	ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;;
 	bfd_xtensa_arch)	ta="$ta xtensa-dis.lo" ;;
 	bfd_z80_arch)		ta="$ta z80-dis.lo" ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 5cef902..3ea4583 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -74,6 +74,7 @@
 #define ARCH_vax
 #define ARCH_w65
 #define ARCH_xstormy16
+#define ARCH_xc16x
 #define ARCH_xtensa
 #define ARCH_z80
 #define ARCH_z8k
@@ -370,6 +371,11 @@ disassembler (abfd)
       disassemble = print_insn_xstormy16;
       break;
 #endif
+#ifdef ARCH_xc16x
+    case bfd_arch_xc16x:
+      disassemble = print_insn_xc16x;
+      break;
+#endif
 #ifdef ARCH_xtensa
     case bfd_arch_xtensa:
       disassemble = print_insn_xtensa;
diff --git a/opcodes/xc16x-asm.c b/opcodes/xc16x-asm.c
new file mode 100644
index 0000000..eb3a0e5
--- /dev/null
+++ b/opcodes/xc16x-asm.c
@@ -0,0 +1,750 @@
+/* Assembler interface for targets using CGEN. -*- C -*-
+   CGEN: Cpu tools GENerator
+
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-asm.in isn't
+
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005
+   Free Software Foundation, Inc.
+
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+   Keep that in mind.  */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "xc16x-desc.h"
+#include "xc16x-opc.h"
+#include "opintl.h"
+#include "xregex.h"
+#include "libiberty.h"
+#include "safe-ctype.h"
+
+#undef  min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef  max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+static const char * parse_insn_normal
+  (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *);
+
+/* -- assembler routines inserted here.  */
+
+/* -- asm.c */
+/* Handle '#' prefixes (i.e. skip over them).  */
+
+static const char *
+parse_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    const char **strp,
+	    int opindex ATTRIBUTE_UNUSED,
+	    long *valuep ATTRIBUTE_UNUSED)
+{
+  if (**strp == '#')
+    ++*strp;
+  return NULL;
+}
+
+/* Handle '.' prefixes (i.e. skip over them).  */
+
+static const char *
+parse_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   const char **strp,
+	   int opindex ATTRIBUTE_UNUSED,
+	   long *valuep ATTRIBUTE_UNUSED)
+{
+  if (**strp == '.')
+    ++*strp;
+  return NULL;
+}
+
+/* Handle '.' prefixes (i.e. skip over them).  */
+
+static const char *
+parse_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   const char **strp,
+	   int opindex ATTRIBUTE_UNUSED,
+	   long *valuep ATTRIBUTE_UNUSED)
+{
+  if (!strncasecmp (*strp, "pof:", 4))
+    *strp += 4;
+  return NULL;
+}
+
+/* Handle '.' prefixes (i.e. skip over them).  */
+
+static const char *
+parse_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   const char **strp,
+	   int opindex ATTRIBUTE_UNUSED,
+	   long *valuep ATTRIBUTE_UNUSED)
+{
+  if (!strncasecmp (*strp, "pag:", 4))
+    *strp += 4;
+  return NULL;
+}
+
+/* Handle 'sof' prefixes (i.e. skip over them).  */
+static const char *
+parse_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   const char **strp,
+	   int opindex ATTRIBUTE_UNUSED,
+	   long *valuep ATTRIBUTE_UNUSED)
+{
+  if (!strncasecmp (*strp, "sof:", 4))
+    *strp += 4;
+  return NULL;
+}
+
+/* Handle 'seg' prefixes (i.e. skip over them).  */
+static const char *
+parse_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   const char **strp,
+	   int opindex ATTRIBUTE_UNUSED,
+	   long *valuep ATTRIBUTE_UNUSED)
+{
+  if (!strncasecmp (*strp, "seg:", 4))
+    *strp += 4;
+  return NULL;
+}
+/* -- */
+
+const char * xc16x_cgen_parse_operand
+  (CGEN_CPU_DESC, int, const char **, CGEN_FIELDS *);
+
+/* Main entry point for operand parsing.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `parse_insn_normal', but keeping it
+   separate makes clear the interface between `parse_insn_normal' and each of
+   the handlers.  */
+
+const char *
+xc16x_cgen_parse_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   const char ** strp,
+			   CGEN_FIELDS * fields)
+{
+  const char * errmsg = NULL;
+  /* Used by scalar operands that still need to be parsed.  */
+  long junk ATTRIBUTE_UNUSED;
+
+  switch (opindex)
+    {
+    case XC16X_OPERAND_REGNAM :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_psw_names, & fields->f_reg8);
+      break;
+    case XC16X_OPERAND_BIT01 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT01, (unsigned long *) (& fields->f_op_1bit));
+      break;
+    case XC16X_OPERAND_BIT1 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT1, (unsigned long *) (& fields->f_op_bit1));
+      break;
+    case XC16X_OPERAND_BIT2 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT2, (unsigned long *) (& fields->f_op_bit2));
+      break;
+    case XC16X_OPERAND_BIT4 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT4, (unsigned long *) (& fields->f_op_bit4));
+      break;
+    case XC16X_OPERAND_BIT8 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BIT8, (unsigned long *) (& fields->f_op_bit8));
+      break;
+    case XC16X_OPERAND_BITONE :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_BITONE, (unsigned long *) (& fields->f_op_onebit));
+      break;
+    case XC16X_OPERAND_CADDR :
+      {
+        bfd_vma value = 0;
+        errmsg = cgen_parse_address (cd, strp, XC16X_OPERAND_CADDR, 0, NULL,  & value);
+        fields->f_offset16 = value;
+      }
+      break;
+    case XC16X_OPERAND_COND :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_conditioncode_names, & fields->f_condcode);
+      break;
+    case XC16X_OPERAND_DATA8 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_DATA8, (unsigned long *) (& fields->f_data8));
+      break;
+    case XC16X_OPERAND_DATAHI8 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_DATAHI8, (unsigned long *) (& fields->f_datahi8));
+      break;
+    case XC16X_OPERAND_DOT :
+      errmsg = parse_dot (cd, strp, XC16X_OPERAND_DOT, (long *) (& junk));
+      break;
+    case XC16X_OPERAND_DR :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r1);
+      break;
+    case XC16X_OPERAND_DRB :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_grb_names, & fields->f_r1);
+      break;
+    case XC16X_OPERAND_DRI :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r4);
+      break;
+    case XC16X_OPERAND_EXTCOND :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_extconditioncode_names, & fields->f_extccode);
+      break;
+    case XC16X_OPERAND_GENREG :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_r8_names, & fields->f_regb8);
+      break;
+    case XC16X_OPERAND_HASH :
+      errmsg = parse_hash (cd, strp, XC16X_OPERAND_HASH, (long *) (& junk));
+      break;
+    case XC16X_OPERAND_ICOND :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_conditioncode_names, & fields->f_icondcode);
+      break;
+    case XC16X_OPERAND_LBIT2 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_LBIT2, (unsigned long *) (& fields->f_op_lbit2));
+      break;
+    case XC16X_OPERAND_LBIT4 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_LBIT4, (unsigned long *) (& fields->f_op_lbit4));
+      break;
+    case XC16X_OPERAND_MASK8 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_MASK8, (unsigned long *) (& fields->f_mask8));
+      break;
+    case XC16X_OPERAND_MASKLO8 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_MASKLO8, (unsigned long *) (& fields->f_datahi8));
+      break;
+    case XC16X_OPERAND_MEMGR8 :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_memgr8_names, & fields->f_memgr8);
+      break;
+    case XC16X_OPERAND_MEMORY :
+      {
+        bfd_vma value = 0;
+        errmsg = cgen_parse_address (cd, strp, XC16X_OPERAND_MEMORY, 0, NULL,  & value);
+        fields->f_memory = value;
+      }
+      break;
+    case XC16X_OPERAND_PAG :
+      errmsg = parse_pag (cd, strp, XC16X_OPERAND_PAG, (long *) (& junk));
+      break;
+    case XC16X_OPERAND_PAGENUM :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_PAGENUM, (unsigned long *) (& fields->f_pagenum));
+      break;
+    case XC16X_OPERAND_POF :
+      errmsg = parse_pof (cd, strp, XC16X_OPERAND_POF, (long *) (& junk));
+      break;
+    case XC16X_OPERAND_QBIT :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_QBIT, (unsigned long *) (& fields->f_qbit));
+      break;
+    case XC16X_OPERAND_QHIBIT :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_QHIBIT, (unsigned long *) (& fields->f_qhibit));
+      break;
+    case XC16X_OPERAND_QLOBIT :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_QLOBIT, (unsigned long *) (& fields->f_qlobit));
+      break;
+    case XC16X_OPERAND_REG8 :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_r8_names, & fields->f_reg8);
+      break;
+    case XC16X_OPERAND_REGB8 :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_grb8_names, & fields->f_regb8);
+      break;
+    case XC16X_OPERAND_REGBMEM8 :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_regbmem8_names, & fields->f_regmem8);
+      break;
+    case XC16X_OPERAND_REGHI8 :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_r8_names, & fields->f_reghi8);
+      break;
+    case XC16X_OPERAND_REGMEM8 :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_regmem8_names, & fields->f_regmem8);
+      break;
+    case XC16X_OPERAND_REGOFF8 :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_r8_names, & fields->f_regoff8);
+      break;
+    case XC16X_OPERAND_REL :
+      errmsg = cgen_parse_signed_integer (cd, strp, XC16X_OPERAND_REL, (long *) (& fields->f_rel8));
+      break;
+    case XC16X_OPERAND_RELHI :
+      errmsg = cgen_parse_signed_integer (cd, strp, XC16X_OPERAND_RELHI, (long *) (& fields->f_relhi8));
+      break;
+    case XC16X_OPERAND_SEG :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_SEG, (unsigned long *) (& fields->f_seg8));
+      break;
+    case XC16X_OPERAND_SEGHI8 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_SEGHI8, (unsigned long *) (& fields->f_segnum8));
+      break;
+    case XC16X_OPERAND_SEGM :
+      errmsg = parse_seg (cd, strp, XC16X_OPERAND_SEGM, (long *) (& junk));
+      break;
+    case XC16X_OPERAND_SOF :
+      errmsg = parse_sof (cd, strp, XC16X_OPERAND_SOF, (long *) (& junk));
+      break;
+    case XC16X_OPERAND_SR :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r2);
+      break;
+    case XC16X_OPERAND_SR2 :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r0);
+      break;
+    case XC16X_OPERAND_SRB :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_grb_names, & fields->f_r2);
+      break;
+    case XC16X_OPERAND_SRC1 :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r1);
+      break;
+    case XC16X_OPERAND_SRC2 :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_gr_names, & fields->f_r2);
+      break;
+    case XC16X_OPERAND_SRDIV :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_regdiv8_names, & fields->f_reg8);
+      break;
+    case XC16X_OPERAND_U4 :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_reg0_name, & fields->f_uimm4);
+      break;
+    case XC16X_OPERAND_UIMM16 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UIMM16, (unsigned long *) (& fields->f_uimm16));
+      break;
+    case XC16X_OPERAND_UIMM2 :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_ext_names, & fields->f_uimm2);
+      break;
+    case XC16X_OPERAND_UIMM3 :
+      errmsg = cgen_parse_keyword (cd, strp, & xc16x_cgen_opval_reg0_name1, & fields->f_uimm3);
+      break;
+    case XC16X_OPERAND_UIMM4 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UIMM4, (unsigned long *) (& fields->f_uimm4));
+      break;
+    case XC16X_OPERAND_UIMM7 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UIMM7, (unsigned long *) (& fields->f_uimm7));
+      break;
+    case XC16X_OPERAND_UIMM8 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UIMM8, (unsigned long *) (& fields->f_uimm8));
+      break;
+    case XC16X_OPERAND_UPAG16 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_UPAG16, (unsigned long *) (& fields->f_uimm16));
+      break;
+    case XC16X_OPERAND_UPOF16 :
+      {
+        bfd_vma value = 0;
+        errmsg = cgen_parse_address (cd, strp, XC16X_OPERAND_UPOF16, 0, NULL,  & value);
+        fields->f_memory = value;
+      }
+      break;
+    case XC16X_OPERAND_USEG16 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_USEG16, (unsigned long *) (& fields->f_offset16));
+      break;
+    case XC16X_OPERAND_USEG8 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_USEG8, (unsigned long *) (& fields->f_seg8));
+      break;
+    case XC16X_OPERAND_USOF16 :
+      errmsg = cgen_parse_unsigned_integer (cd, strp, XC16X_OPERAND_USOF16, (unsigned long *) (& fields->f_offset16));
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while parsing.\n"), opindex);
+      abort ();
+  }
+
+  return errmsg;
+}
+
+cgen_parse_fn * const xc16x_cgen_parse_handlers[] = 
+{
+  parse_insn_normal,
+};
+
+void
+xc16x_cgen_init_asm (CGEN_CPU_DESC cd)
+{
+  xc16x_cgen_init_opcode_table (cd);
+  xc16x_cgen_init_ibld_table (cd);
+  cd->parse_handlers = & xc16x_cgen_parse_handlers[0];
+  cd->parse_operand = xc16x_cgen_parse_operand;
+}
+
+
+
+/* Regex construction routine.
+
+   This translates an opcode syntax string into a regex string,
+   by replacing any non-character syntax element (such as an
+   opcode) with the pattern '.*'
+
+   It then compiles the regex and stores it in the opcode, for
+   later use by xc16x_cgen_assemble_insn
+
+   Returns NULL for success, an error message for failure.  */
+
+char * 
+xc16x_cgen_build_insn_regex (CGEN_INSN *insn)
+{  
+  CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn);
+  const char *mnem = CGEN_INSN_MNEMONIC (insn);
+  char rxbuf[CGEN_MAX_RX_ELEMENTS];
+  char *rx = rxbuf;
+  const CGEN_SYNTAX_CHAR_TYPE *syn;
+  int reg_err;
+
+  syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc));
+
+  /* Mnemonics come first in the syntax string.  */
+  if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+    return _("missing mnemonic in syntax string");
+  ++syn;
+
+  /* Generate a case sensitive regular expression that emulates case
+     insensitive matching in the "C" locale.  We cannot generate a case
+     insensitive regular expression because in Turkish locales, 'i' and 'I'
+     are not equal modulo case conversion.  */
+
+  /* Copy the literal mnemonic out of the insn.  */
+  for (; *mnem; mnem++)
+    {
+      char c = *mnem;
+
+      if (ISALPHA (c))
+	{
+	  *rx++ = '[';
+	  *rx++ = TOLOWER (c);
+	  *rx++ = TOUPPER (c);
+	  *rx++ = ']';
+	}
+      else
+	*rx++ = c;
+    }
+
+  /* Copy any remaining literals from the syntax string into the rx.  */
+  for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn)
+    {
+      if (CGEN_SYNTAX_CHAR_P (* syn)) 
+	{
+	  char c = CGEN_SYNTAX_CHAR (* syn);
+
+	  switch (c) 
+	    {
+	      /* Escape any regex metacharacters in the syntax.  */
+	    case '.': case '[': case '\\': 
+	    case '*': case '^': case '$': 
+
+#ifdef CGEN_ESCAPE_EXTENDED_REGEX
+	    case '?': case '{': case '}': 
+	    case '(': case ')': case '*':
+	    case '|': case '+': case ']':
+#endif
+	      *rx++ = '\\';
+	      *rx++ = c;
+	      break;
+
+	    default:
+	      if (ISALPHA (c))
+		{
+		  *rx++ = '[';
+		  *rx++ = TOLOWER (c);
+		  *rx++ = TOUPPER (c);
+		  *rx++ = ']';
+		}
+	      else
+		*rx++ = c;
+	      break;
+	    }
+	}
+      else
+	{
+	  /* Replace non-syntax fields with globs.  */
+	  *rx++ = '.';
+	  *rx++ = '*';
+	}
+    }
+
+  /* Trailing whitespace ok.  */
+  * rx++ = '['; 
+  * rx++ = ' '; 
+  * rx++ = '\t'; 
+  * rx++ = ']'; 
+  * rx++ = '*'; 
+
+  /* But anchor it after that.  */
+  * rx++ = '$'; 
+  * rx = '\0';
+
+  CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t));
+  reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB);
+
+  if (reg_err == 0) 
+    return NULL;
+  else
+    {
+      static char msg[80];
+
+      regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80);
+      regfree ((regex_t *) CGEN_INSN_RX (insn));
+      free (CGEN_INSN_RX (insn));
+      (CGEN_INSN_RX (insn)) = NULL;
+      return msg;
+    }
+}
+
+
+/* Default insn parser.
+
+   The syntax string is scanned and operands are parsed and stored in FIELDS.
+   Relocs are queued as we go via other callbacks.
+
+   ??? Note that this is currently an all-or-nothing parser.  If we fail to
+   parse the instruction, we return 0 and the caller will start over from
+   the beginning.  Backtracking will be necessary in parsing subexpressions,
+   but that can be handled there.  Not handling backtracking here may get
+   expensive in the case of the m68k.  Deal with later.
+
+   Returns NULL for success, an error message for failure.  */
+
+static const char *
+parse_insn_normal (CGEN_CPU_DESC cd,
+		   const CGEN_INSN *insn,
+		   const char **strp,
+		   CGEN_FIELDS *fields)
+{
+  /* ??? Runtime added insns not handled yet.  */
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  const char *str = *strp;
+  const char *errmsg;
+  const char *p;
+  const CGEN_SYNTAX_CHAR_TYPE * syn;
+#ifdef CGEN_MNEMONIC_OPERANDS
+  /* FIXME: wip */
+  int past_opcode_p;
+#endif
+
+  /* For now we assume the mnemonic is first (there are no leading operands).
+     We can parse it without needing to set up operand parsing.
+     GAS's input scrubber will ensure mnemonics are lowercase, but we may
+     not be called from GAS.  */
+  p = CGEN_INSN_MNEMONIC (insn);
+  while (*p && TOLOWER (*p) == TOLOWER (*str))
+    ++p, ++str;
+
+  if (* p)
+    return _("unrecognized instruction");
+
+#ifndef CGEN_MNEMONIC_OPERANDS
+  if (* str && ! ISSPACE (* str))
+    return _("unrecognized instruction");
+#endif
+
+  CGEN_INIT_PARSE (cd);
+  cgen_init_parse_operand (cd);
+#ifdef CGEN_MNEMONIC_OPERANDS
+  past_opcode_p = 0;
+#endif
+
+  /* We don't check for (*str != '\0') here because we want to parse
+     any trailing fake arguments in the syntax string.  */
+  syn = CGEN_SYNTAX_STRING (syntax);
+
+  /* Mnemonics come first for now, ensure valid string.  */
+  if (! CGEN_SYNTAX_MNEMONIC_P (* syn))
+    abort ();
+
+  ++syn;
+
+  while (* syn != 0)
+    {
+      /* Non operand chars must match exactly.  */
+      if (CGEN_SYNTAX_CHAR_P (* syn))
+	{
+	  /* FIXME: While we allow for non-GAS callers above, we assume the
+	     first char after the mnemonic part is a space.  */
+	  /* FIXME: We also take inappropriate advantage of the fact that
+	     GAS's input scrubber will remove extraneous blanks.  */
+	  if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn)))
+	    {
+#ifdef CGEN_MNEMONIC_OPERANDS
+	      if (CGEN_SYNTAX_CHAR(* syn) == ' ')
+		past_opcode_p = 1;
+#endif
+	      ++ syn;
+	      ++ str;
+	    }
+	  else if (*str)
+	    {
+	      /* Syntax char didn't match.  Can't be this insn.  */
+	      static char msg [80];
+
+	      /* xgettext:c-format */
+	      sprintf (msg, _("syntax error (expected char `%c', found `%c')"),
+		       CGEN_SYNTAX_CHAR(*syn), *str);
+	      return msg;
+	    }
+	  else
+	    {
+	      /* Ran out of input.  */
+	      static char msg [80];
+
+	      /* xgettext:c-format */
+	      sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"),
+		       CGEN_SYNTAX_CHAR(*syn));
+	      return msg;
+	    }
+	  continue;
+	}
+
+      /* We have an operand of some sort.  */
+      errmsg = cd->parse_operand (cd, CGEN_SYNTAX_FIELD (*syn),
+					  &str, fields);
+      if (errmsg)
+	return errmsg;
+
+      /* Done with this operand, continue with next one.  */
+      ++ syn;
+    }
+
+  /* If we're at the end of the syntax string, we're done.  */
+  if (* syn == 0)
+    {
+      /* FIXME: For the moment we assume a valid `str' can only contain
+	 blanks now.  IE: We needn't try again with a longer version of
+	 the insn and it is assumed that longer versions of insns appear
+	 before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3).  */
+      while (ISSPACE (* str))
+	++ str;
+
+      if (* str != '\0')
+	return _("junk at end of line"); /* FIXME: would like to include `str' */
+
+      return NULL;
+    }
+
+  /* We couldn't parse it.  */
+  return _("unrecognized instruction");
+}
+
+/* Main entry point.
+   This routine is called for each instruction to be assembled.
+   STR points to the insn to be assembled.
+   We assume all necessary tables have been initialized.
+   The assembled instruction, less any fixups, is stored in BUF.
+   Remember that if CGEN_INT_INSN_P then BUF is an int and thus the value
+   still needs to be converted to target byte order, otherwise BUF is an array
+   of bytes in target byte order.
+   The result is a pointer to the insn's entry in the opcode table,
+   or NULL if an error occured (an error message will have already been
+   printed).
+
+   Note that when processing (non-alias) macro-insns,
+   this function recurses.
+
+   ??? It's possible to make this cpu-independent.
+   One would have to deal with a few minor things.
+   At this point in time doing so would be more of a curiosity than useful
+   [for example this file isn't _that_ big], but keeping the possibility in
+   mind helps keep the design clean.  */
+
+const CGEN_INSN *
+xc16x_cgen_assemble_insn (CGEN_CPU_DESC cd,
+			   const char *str,
+			   CGEN_FIELDS *fields,
+			   CGEN_INSN_BYTES_PTR buf,
+			   char **errmsg)
+{
+  const char *start;
+  CGEN_INSN_LIST *ilist;
+  const char *parse_errmsg = NULL;
+  const char *insert_errmsg = NULL;
+  int recognized_mnemonic = 0;
+
+  /* Skip leading white space.  */
+  while (ISSPACE (* str))
+    ++ str;
+
+  /* The instructions are stored in hashed lists.
+     Get the first in the list.  */
+  ilist = CGEN_ASM_LOOKUP_INSN (cd, str);
+
+  /* Keep looking until we find a match.  */
+  start = str;
+  for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist))
+    {
+      const CGEN_INSN *insn = ilist->insn;
+      recognized_mnemonic = 1;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
+      /* Not usually needed as unsupported opcodes
+	 shouldn't be in the hash lists.  */
+      /* Is this insn supported by the selected cpu?  */
+      if (! xc16x_cgen_insn_supported (cd, insn))
+	continue;
+#endif
+      /* If the RELAXED attribute is set, this is an insn that shouldn't be
+	 chosen immediately.  Instead, it is used during assembler/linker
+	 relaxation if possible.  */
+      if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0)
+	continue;
+
+      str = start;
+
+      /* Skip this insn if str doesn't look right lexically.  */
+      if (CGEN_INSN_RX (insn) != NULL &&
+	  regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH)
+	continue;
+
+      /* Allow parse/insert handlers to obtain length of insn.  */
+      CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+      parse_errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields);
+      if (parse_errmsg != NULL)
+	continue;
+
+      /* ??? 0 is passed for `pc'.  */
+      insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf,
+						 (bfd_vma) 0);
+      if (insert_errmsg != NULL)
+        continue;
+
+      /* It is up to the caller to actually output the insn and any
+         queued relocs.  */
+      return insn;
+    }
+
+  {
+    static char errbuf[150];
+#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS
+    const char *tmp_errmsg;
+
+    /* If requesting verbose error messages, use insert_errmsg.
+       Failing that, use parse_errmsg.  */
+    tmp_errmsg = (insert_errmsg ? insert_errmsg :
+		  parse_errmsg ? parse_errmsg :
+		  recognized_mnemonic ?
+		  _("unrecognized form of instruction") :
+		  _("unrecognized instruction"));
+
+    if (strlen (start) > 50)
+      /* xgettext:c-format */
+      sprintf (errbuf, "%s `%.50s...'", tmp_errmsg, start);
+    else 
+      /* xgettext:c-format */
+      sprintf (errbuf, "%s `%.50s'", tmp_errmsg, start);
+#else
+    if (strlen (start) > 50)
+      /* xgettext:c-format */
+      sprintf (errbuf, _("bad instruction `%.50s...'"), start);
+    else 
+      /* xgettext:c-format */
+      sprintf (errbuf, _("bad instruction `%.50s'"), start);
+#endif
+      
+    *errmsg = errbuf;
+    return NULL;
+  }
+}
diff --git a/opcodes/xc16x-desc.c b/opcodes/xc16x-desc.c
new file mode 100644
index 0000000..6e59aa4
--- /dev/null
+++ b/opcodes/xc16x-desc.c
@@ -0,0 +1,3534 @@
+/* CPU data for xc16x.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2005 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sysdep.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "xc16x-desc.h"
+#include "xc16x-opc.h"
+#include "opintl.h"
+#include "libiberty.h"
+#include "xregex.h"
+
+/* Attributes.  */
+
+static const CGEN_ATTR_ENTRY bool_attr[] =
+{
+  { "#f", 0 },
+  { "#t", 1 },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
+{
+  { "base", MACH_BASE },
+  { "xc16x", MACH_XC16X },
+  { "max", MACH_MAX },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
+{
+  { "xc16x", ISA_XC16X },
+  { "max", ISA_MAX },
+  { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED =
+{
+  { "NONE", PIPE_NONE },
+  { "OS", PIPE_OS },
+  { 0, 0 }
+};
+
+const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "RESERVED", &bool_attr[0], &bool_attr[0] },
+  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+  { "SIGNED", &bool_attr[0], &bool_attr[0] },
+  { "RELOC", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "PC", &bool_attr[0], &bool_attr[0] },
+  { "PROFILE", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
+  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
+  { "SIGNED", &bool_attr[0], &bool_attr[0] },
+  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
+  { "RELAX", &bool_attr[0], &bool_attr[0] },
+  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
+  { "RELOC", &bool_attr[0], &bool_attr[0] },
+  { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
+  { "DOT-PREFIX", &bool_attr[0], &bool_attr[0] },
+  { "POF-PREFIX", &bool_attr[0], &bool_attr[0] },
+  { "PAG-PREFIX", &bool_attr[0], &bool_attr[0] },
+  { "SOF-PREFIX", &bool_attr[0], &bool_attr[0] },
+  { "SEG-PREFIX", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[] =
+{
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
+  { "ALIAS", &bool_attr[0], &bool_attr[0] },
+  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
+  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
+  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
+  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
+  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
+  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
+  { "RELAXED", &bool_attr[0], &bool_attr[0] },
+  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
+  { "PBB", &bool_attr[0], &bool_attr[0] },
+  { 0, 0, 0 }
+};
+
+/* Instruction set variants.  */
+
+static const CGEN_ISA xc16x_cgen_isa_table[] = {
+  { "xc16x", 16, 32, 16, 32 },
+  { 0, 0, 0, 0, 0 }
+};
+
+/* Machine variants.  */
+
+static const CGEN_MACH xc16x_cgen_mach_table[] = {
+  { "xc16x", "xc16x", MACH_XC16X, 32 },
+  { 0, 0, 0, 0 }
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_gr_names_entries[] =
+{
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_gr_names =
+{
+  & xc16x_cgen_opval_gr_names_entries[0],
+  16,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_ext_names_entries[] =
+{
+  { "0x1", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x2", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x3", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x4", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "1", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "2", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "3", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "4", 3, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_ext_names =
+{
+  & xc16x_cgen_opval_ext_names_entries[0],
+  8,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_psw_names_entries[] =
+{
+  { "IEN", 136, {0, {{{0, 0}}}}, 0, 0 },
+  { "r0.11", 240, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1.11", 241, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2.11", 242, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3.11", 243, {0, {{{0, 0}}}}, 0, 0 },
+  { "r4.11", 244, {0, {{{0, 0}}}}, 0, 0 },
+  { "r5.11", 245, {0, {{{0, 0}}}}, 0, 0 },
+  { "r6.11", 246, {0, {{{0, 0}}}}, 0, 0 },
+  { "r7.11", 247, {0, {{{0, 0}}}}, 0, 0 },
+  { "r8.11", 248, {0, {{{0, 0}}}}, 0, 0 },
+  { "r9.11", 249, {0, {{{0, 0}}}}, 0, 0 },
+  { "r10.11", 250, {0, {{{0, 0}}}}, 0, 0 },
+  { "r11.11", 251, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12.11", 252, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13.11", 253, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14.11", 254, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15.11", 255, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_psw_names =
+{
+  & xc16x_cgen_opval_psw_names_entries[0],
+  17,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb_names_entries[] =
+{
+  { "rl0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh0", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl1", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh1", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl2", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh2", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl3", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh3", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl4", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh4", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl5", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh5", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl6", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh6", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl7", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh7", 15, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_grb_names =
+{
+  & xc16x_cgen_opval_grb_names_entries[0],
+  16,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_conditioncode_names_entries[] =
+{
+  { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_NET", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_Z", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_EQ", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_NZ", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_NE", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_V", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_NV", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_N", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_NN", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_ULT", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_UGE", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_C", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_NC", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_SGT", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_SLE", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_SLT", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_SGE", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_UGT", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_ULE", 15, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names =
+{
+  & xc16x_cgen_opval_conditioncode_names_entries[0],
+  20,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_extconditioncode_names_entries[] =
+{
+  { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_NET", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_Z", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_EQ", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_NZ", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_NE", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_V", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_NV", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_N", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_NN", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_ULT", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_UGE", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_C", 16, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_NC", 18, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_SGT", 20, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_SLE", 22, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_SLT", 24, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_SGE", 26, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_UGT", 28, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_ULE", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_nusr0", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_nusr1", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_usr0", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "cc_usr1", 7, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names =
+{
+  & xc16x_cgen_opval_extconditioncode_names_entries[0],
+  24,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb8_names_entries[] =
+{
+  { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
+  { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
+  { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
+  { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
+  { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
+  { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_grb8_names =
+{
+  & xc16x_cgen_opval_grb8_names_entries[0],
+  36,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_r8_names_entries[] =
+{
+  { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
+  { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
+  { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
+  { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
+  { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
+  { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
+  { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
+  { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
+  { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
+  { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
+  { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
+  { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
+  { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
+  { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
+  { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_r8_names =
+{
+  & xc16x_cgen_opval_r8_names_entries[0],
+  36,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regmem8_names_entries[] =
+{
+  { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
+  { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
+  { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
+  { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
+  { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
+  { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
+  { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
+  { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
+  { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
+  { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
+  { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
+  { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
+  { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
+  { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
+  { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_regmem8_names =
+{
+  & xc16x_cgen_opval_regmem8_names_entries[0],
+  36,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regdiv8_names_entries[] =
+{
+  { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "r1", 17, {0, {{{0, 0}}}}, 0, 0 },
+  { "r2", 34, {0, {{{0, 0}}}}, 0, 0 },
+  { "r3", 51, {0, {{{0, 0}}}}, 0, 0 },
+  { "r4", 68, {0, {{{0, 0}}}}, 0, 0 },
+  { "r5", 85, {0, {{{0, 0}}}}, 0, 0 },
+  { "r6", 102, {0, {{{0, 0}}}}, 0, 0 },
+  { "r7", 119, {0, {{{0, 0}}}}, 0, 0 },
+  { "r8", 136, {0, {{{0, 0}}}}, 0, 0 },
+  { "r9", 153, {0, {{{0, 0}}}}, 0, 0 },
+  { "r10", 170, {0, {{{0, 0}}}}, 0, 0 },
+  { "r11", 187, {0, {{{0, 0}}}}, 0, 0 },
+  { "r12", 204, {0, {{{0, 0}}}}, 0, 0 },
+  { "r13", 221, {0, {{{0, 0}}}}, 0, 0 },
+  { "r14", 238, {0, {{{0, 0}}}}, 0, 0 },
+  { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names =
+{
+  & xc16x_cgen_opval_regdiv8_names_entries[0],
+  16,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name_entries[] =
+{
+  { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "0xa", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "0xb", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "0xc", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "0xd", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "0xe", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "0xf", 15, {0, {{{0, 0}}}}, 0, 0 },
+  { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "8", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "9", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "10", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "11", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "12", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "13", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "14", 14, {0, {{{0, 0}}}}, 0, 0 },
+  { "15", 15, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_reg0_name =
+{
+  & xc16x_cgen_opval_reg0_name_entries[0],
+  30,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name1_entries[] =
+{
+  { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
+  { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "7", 7, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_reg0_name1 =
+{
+  & xc16x_cgen_opval_reg0_name1_entries[0],
+  14,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regbmem8_names_entries[] =
+{
+  { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
+  { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
+  { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
+  { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
+  { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
+  { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
+  { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
+  { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
+  { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
+  { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
+  { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
+  { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names =
+{
+  & xc16x_cgen_opval_regbmem8_names_entries[0],
+  36,
+  0, 0, 0, 0, ""
+};
+
+static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_memgr8_names_entries[] =
+{
+  { "dpp0", 65024, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp1", 65026, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp2", 65028, {0, {{{0, 0}}}}, 0, 0 },
+  { "dpp3", 65030, {0, {{{0, 0}}}}, 0, 0 },
+  { "psw", 65296, {0, {{{0, 0}}}}, 0, 0 },
+  { "cp", 65040, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdl", 65038, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdh", 65036, {0, {{{0, 0}}}}, 0, 0 },
+  { "mdc", 65294, {0, {{{0, 0}}}}, 0, 0 },
+  { "sp", 65042, {0, {{{0, 0}}}}, 0, 0 },
+  { "csp", 65032, {0, {{{0, 0}}}}, 0, 0 },
+  { "vecseg", 65298, {0, {{{0, 0}}}}, 0, 0 },
+  { "stkov", 65044, {0, {{{0, 0}}}}, 0, 0 },
+  { "stkun", 65046, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpucon1", 65048, {0, {{{0, 0}}}}, 0, 0 },
+  { "cpucon2", 65050, {0, {{{0, 0}}}}, 0, 0 },
+  { "zeros", 65308, {0, {{{0, 0}}}}, 0, 0 },
+  { "ones", 65310, {0, {{{0, 0}}}}, 0, 0 },
+  { "spseg", 65292, {0, {{{0, 0}}}}, 0, 0 },
+  { "tfr", 65452, {0, {{{0, 0}}}}, 0, 0 }
+};
+
+CGEN_KEYWORD xc16x_cgen_opval_memgr8_names =
+{
+  & xc16x_cgen_opval_memgr8_names_entries[0],
+  20,
+  0, 0, 0, 0, ""
+};
+
+
+/* The hardware table.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_HW_##a)
+#else
+#define A(a) (1 << CGEN_HW_/**/a)
+#endif
+
+const CGEN_HW_ENTRY xc16x_cgen_hw_table[] =
+{
+  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-ext", HW_H_EXT, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_ext_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-psw", HW_H_PSW, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_psw_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-grb", HW_H_GRB, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_conditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-ecc", HW_H_ECC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_extconditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-grb8", HW_H_GRB8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-r8", HW_H_R8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_r8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-regmem8", HW_H_REGMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regmem8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-regdiv8", HW_H_REGDIV8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regdiv8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-r01", HW_H_R01, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name1, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-regbmem8", HW_H_REGBMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regbmem8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-memgr8", HW_H_MEMGR8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_memgr8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { "h-sgtdis", HW_H_SGTDIS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+  { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
+};
+
+#undef A
+
+
+/* The instruction field table.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_IFLD_##a)
+#else
+#define A(a) (1 << CGEN_IFLD_/**/a)
+#endif
+
+const CGEN_IFLD xc16x_cgen_ifld_table[] =
+{
+  { XC16X_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP1, "f-op1", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP2, "f-op2", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_ICONDCODE, "f-icondcode", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_RCOND, "f-rcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_QCOND, "f-qcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_EXTCCODE, "f-extccode", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_R0, "f-r0", 0, 32, 9, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_R1, "f-r1", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_R2, "f-r2", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_R3, "f-r3", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_R4, "f-r4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_UIMM2, "f-uimm2", 0, 32, 13, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_UIMM3, "f-uimm3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_UIMM4, "f-uimm4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_UIMM7, "f-uimm7", 0, 32, 15, 7, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_UIMM8, "f-uimm8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_UIMM16, "f-uimm16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_MEMORY, "f-memory", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_MEMGR8, "f-memgr8", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_REL8, "f-rel8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_RELHI8, "f-relhi8", 0, 32, 23, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_REG8, "f-reg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_REGMEM8, "f-regmem8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_REGOFF8, "f-regoff8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_REGHI8, "f-reghi8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_REGB8, "f-regb8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_SEG8, "f-seg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_SEGNUM8, "f-segnum8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_MASK8, "f-mask8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_PAGENUM, "f-pagenum", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_DATAHI8, "f-datahi8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_DATA8, "f-data8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OFFSET16, "f-offset16", 0, 32, 31, 16, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP_BIT1, "f-op-bit1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP_BIT2, "f-op-bit2", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP_BIT4, "f-op-bit4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP_BIT3, "f-op-bit3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP_2BIT, "f-op-2bit", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP_BITONE, "f-op-bitone", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP_ONEBIT, "f-op-onebit", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP_1BIT, "f-op-1bit", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP_LBIT4, "f-op-lbit4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP_LBIT2, "f-op-lbit2", 0, 32, 15, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP_BIT8, "f-op-bit8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_OP_BIT16, "f-op-bit16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_QBIT, "f-qbit", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_QLOBIT, "f-qlobit", 0, 32, 31, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_QHIBIT, "f-qhibit", 0, 32, 27, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_QLOBIT2, "f-qlobit2", 0, 32, 27, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { XC16X_F_POF, "f-pof", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+  { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
+};
+
+#undef A
+
+
+
+/* multi ifield declarations */
+
+
+
+/* multi ifield definitions */
+
+
+/* The operand table.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_OPERAND_##a)
+#else
+#define A(a) (1 << CGEN_OPERAND_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) XC16X_OPERAND_##op
+#else
+#define OPERAND(op) XC16X_OPERAND_/**/op
+#endif
+
+const CGEN_OPERAND xc16x_cgen_operand_table[] =
+{
+/* pc: program counter */
+  { "pc", XC16X_OPERAND_PC, HW_H_PC, 0, 0,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_NIL] } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* sr: source register */
+  { "sr", XC16X_OPERAND_SR, HW_H_GR, 11, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* dr: destination register */
+  { "dr", XC16X_OPERAND_DR, HW_H_GR, 15, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* dri: destination register */
+  { "dri", XC16X_OPERAND_DRI, HW_H_GR, 11, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R4] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* srb: source register */
+  { "srb", XC16X_OPERAND_SRB, HW_H_GRB, 11, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* drb: destination register */
+  { "drb", XC16X_OPERAND_DRB, HW_H_GRB, 15, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* sr2: 2 bit source register */
+  { "sr2", XC16X_OPERAND_SR2, HW_H_GR, 9, 2,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R0] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* src1: source register 1 */
+  { "src1", XC16X_OPERAND_SRC1, HW_H_GR, 15, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* src2: source register 2 */
+  { "src2", XC16X_OPERAND_SRC2, HW_H_GR, 11, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* srdiv: source register 2 */
+  { "srdiv", XC16X_OPERAND_SRDIV, HW_H_REGDIV8, 15, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* RegNam: PSW bits */
+  { "RegNam", XC16X_OPERAND_REGNAM, HW_H_PSW, 15, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* uimm2: 2 bit unsigned number */
+  { "uimm2", XC16X_OPERAND_UIMM2, HW_H_EXT, 13, 2,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM2] } }, 
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* uimm3: 3 bit unsigned number */
+  { "uimm3", XC16X_OPERAND_UIMM3, HW_H_R01, 10, 3,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM3] } }, 
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* uimm4: 4 bit unsigned number */
+  { "uimm4", XC16X_OPERAND_UIMM4, HW_H_UINT, 15, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } }, 
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* uimm7: 7 bit trap number */
+  { "uimm7", XC16X_OPERAND_UIMM7, HW_H_UINT, 15, 7,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM7] } }, 
+    { 0|A(HASH_PREFIX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+/* uimm8: 8 bit unsigned immediate */
+  { "uimm8", XC16X_OPERAND_UIMM8, HW_H_UINT, 23, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM8] } }, 
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* uimm16: 16 bit unsigned immediate */
+  { "uimm16", XC16X_OPERAND_UIMM16, HW_H_UINT, 31, 16,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } }, 
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* upof16: 16 bit unsigned immediate */
+  { "upof16", XC16X_OPERAND_UPOF16, HW_H_ADDR, 31, 16,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } }, 
+    { 0|A(POF_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* reg8: 8 bit word register number */
+  { "reg8", XC16X_OPERAND_REG8, HW_H_R8, 15, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* regmem8: 8 bit word register number */
+  { "regmem8", XC16X_OPERAND_REGMEM8, HW_H_REGMEM8, 15, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* regbmem8: 8 bit byte register number */
+  { "regbmem8", XC16X_OPERAND_REGBMEM8, HW_H_REGBMEM8, 15, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* regoff8: 8 bit word register number */
+  { "regoff8", XC16X_OPERAND_REGOFF8, HW_H_R8, 15, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGOFF8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* reghi8: 8 bit word register number */
+  { "reghi8", XC16X_OPERAND_REGHI8, HW_H_R8, 23, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGHI8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* regb8: 8 bit byte register number */
+  { "regb8", XC16X_OPERAND_REGB8, HW_H_GRB8, 15, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* genreg: 8 bit word register number */
+  { "genreg", XC16X_OPERAND_GENREG, HW_H_R8, 15, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* seg: 8 bit segment number */
+  { "seg", XC16X_OPERAND_SEG, HW_H_UINT, 15, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* seghi8: 8 bit hi segment number */
+  { "seghi8", XC16X_OPERAND_SEGHI8, HW_H_UINT, 23, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEGNUM8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* caddr: 16 bit address offset */
+  { "caddr", XC16X_OPERAND_CADDR, HW_H_ADDR, 31, 16,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } }, 
+    { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+/* rel: 8 bit signed relative offset */
+  { "rel", XC16X_OPERAND_REL, HW_H_SINT, 15, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REL8] } }, 
+    { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+/* relhi: hi 8 bit signed relative offset */
+  { "relhi", XC16X_OPERAND_RELHI, HW_H_SINT, 23, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_RELHI8] } }, 
+    { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+/* condbit: condition bit */
+  { "condbit", XC16X_OPERAND_CONDBIT, HW_H_COND, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* bit1: gap of 1 bit */
+  { "bit1", XC16X_OPERAND_BIT1, HW_H_UINT, 11, 1,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT1] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* bit2: gap of 2 bits */
+  { "bit2", XC16X_OPERAND_BIT2, HW_H_UINT, 11, 2,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT2] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* bit4: gap of 4 bits */
+  { "bit4", XC16X_OPERAND_BIT4, HW_H_UINT, 11, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT4] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* lbit4: gap of 4 bits */
+  { "lbit4", XC16X_OPERAND_LBIT4, HW_H_UINT, 15, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT4] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* lbit2: gap of 2 bits */
+  { "lbit2", XC16X_OPERAND_LBIT2, HW_H_UINT, 15, 2,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT2] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* bit8: gap of 8 bits */
+  { "bit8", XC16X_OPERAND_BIT8, HW_H_UINT, 31, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* u4: gap of 4 bits */
+  { "u4", XC16X_OPERAND_U4, HW_H_R0, 15, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* bitone: field of 1 bit */
+  { "bitone", XC16X_OPERAND_BITONE, HW_H_UINT, 9, 1,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_ONEBIT] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* bit01: field of 1 bit */
+  { "bit01", XC16X_OPERAND_BIT01, HW_H_UINT, 8, 1,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_1BIT] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* cond: condition code */
+  { "cond", XC16X_OPERAND_COND, HW_H_CC, 7, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_CONDCODE] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* icond: indirect condition code */
+  { "icond", XC16X_OPERAND_ICOND, HW_H_CC, 15, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_ICONDCODE] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* extcond: extended condition code */
+  { "extcond", XC16X_OPERAND_EXTCOND, HW_H_ECC, 15, 5,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_EXTCCODE] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* memory: 16 bit memory */
+  { "memory", XC16X_OPERAND_MEMORY, HW_H_ADDR, 31, 16,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* memgr8: 16 bit memory */
+  { "memgr8", XC16X_OPERAND_MEMGR8, HW_H_MEMGR8, 31, 16,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMGR8] } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* cbit: carry bit */
+  { "cbit", XC16X_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* qbit: bit addr */
+  { "qbit", XC16X_OPERAND_QBIT, HW_H_UINT, 7, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QBIT] } }, 
+    { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* qlobit: bit addr */
+  { "qlobit", XC16X_OPERAND_QLOBIT, HW_H_UINT, 31, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QLOBIT] } }, 
+    { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* qhibit: bit addr */
+  { "qhibit", XC16X_OPERAND_QHIBIT, HW_H_UINT, 27, 4,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QHIBIT] } }, 
+    { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* mask8: 8 bit mask */
+  { "mask8", XC16X_OPERAND_MASK8, HW_H_UINT, 23, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MASK8] } }, 
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* masklo8: 8 bit mask */
+  { "masklo8", XC16X_OPERAND_MASKLO8, HW_H_UINT, 31, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } }, 
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* pagenum: 10 bit page number */
+  { "pagenum", XC16X_OPERAND_PAGENUM, HW_H_UINT, 25, 10,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_PAGENUM] } }, 
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* data8: 8 bit data */
+  { "data8", XC16X_OPERAND_DATA8, HW_H_UINT, 23, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATA8] } }, 
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* datahi8: 8 bit data */
+  { "datahi8", XC16X_OPERAND_DATAHI8, HW_H_UINT, 31, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } }, 
+    { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* sgtdisbit: segmentation enable bit */
+  { "sgtdisbit", XC16X_OPERAND_SGTDISBIT, HW_H_SGTDIS, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
+/* upag16: 16 bit unsigned immediate */
+  { "upag16", XC16X_OPERAND_UPAG16, HW_H_UINT, 31, 16,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } }, 
+    { 0|A(PAG_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* useg8: 8 bit segment  */
+  { "useg8", XC16X_OPERAND_USEG8, HW_H_UINT, 15, 8,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } }, 
+    { 0|A(SEG_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
+/* useg16: 16 bit address offset */
+  { "useg16", XC16X_OPERAND_USEG16, HW_H_UINT, 31, 16,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } }, 
+    { 0|A(SEG_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+/* usof16: 16 bit address offset */
+  { "usof16", XC16X_OPERAND_USOF16, HW_H_UINT, 31, 16,
+    { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } }, 
+    { 0|A(SOF_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
+/* hash: # prefix */
+  { "hash", XC16X_OPERAND_HASH, HW_H_SINT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* dot: . prefix */
+  { "dot", XC16X_OPERAND_DOT, HW_H_SINT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* pof: pof: prefix */
+  { "pof", XC16X_OPERAND_POF, HW_H_SINT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* pag: pag: prefix */
+  { "pag", XC16X_OPERAND_PAG, HW_H_SINT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* sof: sof: prefix */
+  { "sof", XC16X_OPERAND_SOF, HW_H_SINT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* segm: seg: prefix */
+  { "segm", XC16X_OPERAND_SEGM, HW_H_SINT, 0, 0,
+    { 0, { (const PTR) 0 } }, 
+    { 0, { { { (1<<MACH_BASE), 0 } } } }  },
+/* sentinel */
+  { 0, 0, 0, 0, 0,
+    { 0, { (const PTR) 0 } },
+    { 0, { { { (1<<MACH_BASE), 0 } } } } }
+};
+
+#undef A
+
+
+/* The instruction table.  */
+
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+
+static const CGEN_IBASE xc16x_cgen_insn_table[MAX_INSNS] =
+{
+  /* Special null first entry.
+     A `num' value of zero is thus invalid.
+     Also, the special `invalid' insn resides here.  */
+  { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
+/* add $reg8,$pof$upof16 */
+  {
+    XC16X_INSN_ADDRPOF, "addrpof", "add", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $reg8,$pof$upof16 */
+  {
+    XC16X_INSN_SUBRPOF, "subrpof", "sub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $regb8,$pof$upof16 */
+  {
+    XC16X_INSN_ADDBRPOF, "addbrpof", "addb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $regb8,$pof$upof16 */
+  {
+    XC16X_INSN_SUBBRPOF, "subbrpof", "subb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $reg8,$pag$upag16 */
+  {
+    XC16X_INSN_ADDRPAG, "addrpag", "add", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $reg8,$pag$upag16 */
+  {
+    XC16X_INSN_SUBRPAG, "subrpag", "sub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $regb8,$pag$upag16 */
+  {
+    XC16X_INSN_ADDBRPAG, "addbrpag", "addb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $regb8,$pag$upag16 */
+  {
+    XC16X_INSN_SUBBRPAG, "subbrpag", "subb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $reg8,$pof$upof16 */
+  {
+    XC16X_INSN_ADDCRPOF, "addcrpof", "addc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $reg8,$pof$upof16 */
+  {
+    XC16X_INSN_SUBCRPOF, "subcrpof", "subc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $regb8,$pof$upof16 */
+  {
+    XC16X_INSN_ADDCBRPOF, "addcbrpof", "addcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $regb8,$pof$upof16 */
+  {
+    XC16X_INSN_SUBCBRPOF, "subcbrpof", "subcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $reg8,$pag$upag16 */
+  {
+    XC16X_INSN_ADDCRPAG, "addcrpag", "addc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $reg8,$pag$upag16 */
+  {
+    XC16X_INSN_SUBCRPAG, "subcrpag", "subc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $regb8,$pag$upag16 */
+  {
+    XC16X_INSN_ADDCBRPAG, "addcbrpag", "addcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $regb8,$pag$upag16 */
+  {
+    XC16X_INSN_SUBCBRPAG, "subcbrpag", "subcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $pof$upof16,$reg8 */
+  {
+    XC16X_INSN_ADDRPOFR, "addrpofr", "add", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $pof$upof16,$reg8 */
+  {
+    XC16X_INSN_SUBRPOFR, "subrpofr", "sub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $pof$upof16,$regb8 */
+  {
+    XC16X_INSN_ADDBRPOFR, "addbrpofr", "addb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $pof$upof16,$regb8 */
+  {
+    XC16X_INSN_SUBBRPOFR, "subbrpofr", "subb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $pof$upof16,$reg8 */
+  {
+    XC16X_INSN_ADDCRPOFR, "addcrpofr", "addc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $pof$upof16,$reg8 */
+  {
+    XC16X_INSN_SUBCRPOFR, "subcrpofr", "subc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $pof$upof16,$regb8 */
+  {
+    XC16X_INSN_ADDCBRPOFR, "addcbrpofr", "addcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $pof$upof16,$regb8 */
+  {
+    XC16X_INSN_SUBCBRPOFR, "subcbrpofr", "subcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $reg8,$hash$pof$uimm16 */
+  {
+    XC16X_INSN_ADDRHPOF, "addrhpof", "add", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $reg8,$hash$pof$uimm16 */
+  {
+    XC16X_INSN_SUBRHPOF, "subrhpof", "sub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $reg8,$hash$pag$uimm16 */
+  {
+    XC16X_INSN_ADDBRHPOF, "addbrhpof", "add", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $reg8,$hash$pag$uimm16 */
+  {
+    XC16X_INSN_SUBBRHPOF, "subbrhpof", "sub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $dr,$hash$pof$uimm3 */
+  {
+    XC16X_INSN_ADDRHPOF3, "addrhpof3", "add", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $dr,$hash$pof$uimm3 */
+  {
+    XC16X_INSN_SUBRHPOF3, "subrhpof3", "sub", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $drb,$hash$pag$uimm3 */
+  {
+    XC16X_INSN_ADDBRHPAG3, "addbrhpag3", "addb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $drb,$hash$pag$uimm3 */
+  {
+    XC16X_INSN_SUBBRHPAG3, "subbrhpag3", "subb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $dr,$hash$pag$uimm3 */
+  {
+    XC16X_INSN_ADDRHPAG3, "addrhpag3", "add", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $dr,$hash$pag$uimm3 */
+  {
+    XC16X_INSN_SUBRHPAG3, "subrhpag3", "sub", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $drb,$hash$pof$uimm3 */
+  {
+    XC16X_INSN_ADDBRHPOF3, "addbrhpof3", "addb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $drb,$hash$pof$uimm3 */
+  {
+    XC16X_INSN_SUBBRHPOF3, "subbrhpof3", "subb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $regb8,$hash$pof$uimm8 */
+  {
+    XC16X_INSN_ADDRBHPOF, "addrbhpof", "addb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $regb8,$hash$pof$uimm8 */
+  {
+    XC16X_INSN_SUBRBHPOF, "subrbhpof", "subb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $regb8,$hash$pag$uimm8 */
+  {
+    XC16X_INSN_ADDBRHPAG, "addbrhpag", "addb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $regb8,$hash$pag$uimm8 */
+  {
+    XC16X_INSN_SUBBRHPAG, "subbrhpag", "subb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $reg8,$hash$pof$uimm16 */
+  {
+    XC16X_INSN_ADDCRHPOF, "addcrhpof", "addc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $reg8,$hash$pof$uimm16 */
+  {
+    XC16X_INSN_SUBCRHPOF, "subcrhpof", "subc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $reg8,$hash$pag$uimm16 */
+  {
+    XC16X_INSN_ADDCBRHPOF, "addcbrhpof", "addc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $reg8,$hash$pag$uimm16 */
+  {
+    XC16X_INSN_SUBCBRHPOF, "subcbrhpof", "subc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $dr,$hash$pof$uimm3 */
+  {
+    XC16X_INSN_ADDCRHPOF3, "addcrhpof3", "addc", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $dr,$hash$pof$uimm3 */
+  {
+    XC16X_INSN_SUBCRHPOF3, "subcrhpof3", "subc", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $drb,$hash$pag$uimm3 */
+  {
+    XC16X_INSN_ADDCBRHPAG3, "addcbrhpag3", "addcb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $drb,$hash$pag$uimm3 */
+  {
+    XC16X_INSN_SUBCBRHPAG3, "subcbrhpag3", "subcb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $dr,$hash$pag$uimm3 */
+  {
+    XC16X_INSN_ADDCRHPAG3, "addcrhpag3", "addc", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $dr,$hash$pag$uimm3 */
+  {
+    XC16X_INSN_SUBCRHPAG3, "subcrhpag3", "subc", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $drb,$hash$pof$uimm3 */
+  {
+    XC16X_INSN_ADDCBRHPOF3, "addcbrhpof3", "addcb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $drb,$hash$pof$uimm3 */
+  {
+    XC16X_INSN_SUBCBRHPOF3, "subcbrhpof3", "subcb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $regb8,$hash$pof$uimm8 */
+  {
+    XC16X_INSN_ADDCRBHPOF, "addcrbhpof", "addcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $regb8,$hash$pof$uimm8 */
+  {
+    XC16X_INSN_SUBCRBHPOF, "subcrbhpof", "subcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $regb8,$hash$pag$uimm8 */
+  {
+    XC16X_INSN_ADDCBRHPAG, "addcbrhpag", "addcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $regb8,$hash$pag$uimm8 */
+  {
+    XC16X_INSN_SUBCBRHPAG, "subcbrhpag", "subcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $dr,$hash$uimm3 */
+  {
+    XC16X_INSN_ADDRI, "addri", "add", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $dr,$hash$uimm3 */
+  {
+    XC16X_INSN_SUBRI, "subri", "sub", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $drb,$hash$uimm3 */
+  {
+    XC16X_INSN_ADDBRI, "addbri", "addb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $drb,$hash$uimm3 */
+  {
+    XC16X_INSN_SUBBRI, "subbri", "subb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_ADDRIM, "addrim", "add", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_SUBRIM, "subrim", "sub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $regb8,$hash$uimm8 */
+  {
+    XC16X_INSN_ADDBRIM, "addbrim", "addb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $regb8,$hash$uimm8 */
+  {
+    XC16X_INSN_SUBBRIM, "subbrim", "subb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $dr,$hash$uimm3 */
+  {
+    XC16X_INSN_ADDCRI, "addcri", "addc", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $dr,$hash$uimm3 */
+  {
+    XC16X_INSN_SUBCRI, "subcri", "subc", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $drb,$hash$uimm3 */
+  {
+    XC16X_INSN_ADDCBRI, "addcbri", "addcb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $drb,$hash$uimm3 */
+  {
+    XC16X_INSN_SUBCBRI, "subcbri", "subcb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_ADDCRIM, "addcrim", "addc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_SUBCRIM, "subcrim", "subc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $regb8,$hash$uimm8 */
+  {
+    XC16X_INSN_ADDCBRIM, "addcbrim", "addcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $regb8,$hash$uimm8 */
+  {
+    XC16X_INSN_SUBCBRIM, "subcbrim", "subcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $dr,$sr */
+  {
+    XC16X_INSN_ADDR, "addr", "add", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $dr,$sr */
+  {
+    XC16X_INSN_SUBR, "subr", "sub", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $drb,$srb */
+  {
+    XC16X_INSN_ADDBR, "addbr", "addb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $drb,$srb */
+  {
+    XC16X_INSN_SUBBR, "subbr", "subb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $dr,[$sr2] */
+  {
+    XC16X_INSN_ADD2, "add2", "add", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $dr,[$sr2] */
+  {
+    XC16X_INSN_SUB2, "sub2", "sub", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $drb,[$sr2] */
+  {
+    XC16X_INSN_ADDB2, "addb2", "addb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $drb,[$sr2] */
+  {
+    XC16X_INSN_SUBB2, "subb2", "subb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $dr,[$sr2+] */
+  {
+    XC16X_INSN_ADD2I, "add2i", "add", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $dr,[$sr2+] */
+  {
+    XC16X_INSN_SUB2I, "sub2i", "sub", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $drb,[$sr2+] */
+  {
+    XC16X_INSN_ADDB2I, "addb2i", "addb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $drb,[$sr2+] */
+  {
+    XC16X_INSN_SUBB2I, "subb2i", "subb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $dr,$sr */
+  {
+    XC16X_INSN_ADDCR, "addcr", "addc", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $dr,$sr */
+  {
+    XC16X_INSN_SUBCR, "subcr", "subc", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $drb,$srb */
+  {
+    XC16X_INSN_ADDBCR, "addbcr", "addcb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $drb,$srb */
+  {
+    XC16X_INSN_SUBBCR, "subbcr", "subcb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $dr,[$sr2] */
+  {
+    XC16X_INSN_ADDCR2, "addcr2", "addc", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $dr,[$sr2] */
+  {
+    XC16X_INSN_SUBCR2, "subcr2", "subc", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $drb,[$sr2] */
+  {
+    XC16X_INSN_ADDBCR2, "addbcr2", "addcb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $drb,[$sr2] */
+  {
+    XC16X_INSN_SUBBCR2, "subbcr2", "subcb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $dr,[$sr2+] */
+  {
+    XC16X_INSN_ADDCR2I, "addcr2i", "addc", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $dr,[$sr2+] */
+  {
+    XC16X_INSN_SUBCR2I, "subcr2i", "subc", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $drb,[$sr2+] */
+  {
+    XC16X_INSN_ADDBCR2I, "addbcr2i", "addcb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $drb,[$sr2+] */
+  {
+    XC16X_INSN_SUBBCR2I, "subbcr2i", "subcb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $regmem8,$memgr8 */
+  {
+    XC16X_INSN_ADDRM2, "addrm2", "add", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $memgr8,$regmem8 */
+  {
+    XC16X_INSN_ADDRM3, "addrm3", "add", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $reg8,$memory */
+  {
+    XC16X_INSN_ADDRM, "addrm", "add", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* add $memory,$reg8 */
+  {
+    XC16X_INSN_ADDRM1, "addrm1", "add", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $regmem8,$memgr8 */
+  {
+    XC16X_INSN_SUBRM3, "subrm3", "sub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $memgr8,$regmem8 */
+  {
+    XC16X_INSN_SUBRM2, "subrm2", "sub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $reg8,$memory */
+  {
+    XC16X_INSN_SUBRM1, "subrm1", "sub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sub $memory,$reg8 */
+  {
+    XC16X_INSN_SUBRM, "subrm", "sub", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $regbmem8,$memgr8 */
+  {
+    XC16X_INSN_ADDBRM2, "addbrm2", "addb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $memgr8,$regbmem8 */
+  {
+    XC16X_INSN_ADDBRM3, "addbrm3", "addb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $regb8,$memory */
+  {
+    XC16X_INSN_ADDBRM, "addbrm", "addb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addb $memory,$regb8 */
+  {
+    XC16X_INSN_ADDBRM1, "addbrm1", "addb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $regbmem8,$memgr8 */
+  {
+    XC16X_INSN_SUBBRM3, "subbrm3", "subb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $memgr8,$regbmem8 */
+  {
+    XC16X_INSN_SUBBRM2, "subbrm2", "subb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $regb8,$memory */
+  {
+    XC16X_INSN_SUBBRM1, "subbrm1", "subb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subb $memory,$regb8 */
+  {
+    XC16X_INSN_SUBBRM, "subbrm", "subb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $regmem8,$memgr8 */
+  {
+    XC16X_INSN_ADDCRM2, "addcrm2", "addc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $memgr8,$regmem8 */
+  {
+    XC16X_INSN_ADDCRM3, "addcrm3", "addc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $reg8,$memory */
+  {
+    XC16X_INSN_ADDCRM, "addcrm", "addc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addc $memory,$reg8 */
+  {
+    XC16X_INSN_ADDCRM1, "addcrm1", "addc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $regmem8,$memgr8 */
+  {
+    XC16X_INSN_SUBCRM3, "subcrm3", "subc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $memgr8,$regmem8 */
+  {
+    XC16X_INSN_SUBCRM2, "subcrm2", "subc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $reg8,$memory */
+  {
+    XC16X_INSN_SUBCRM1, "subcrm1", "subc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subc $memory,$reg8 */
+  {
+    XC16X_INSN_SUBCRM, "subcrm", "subc", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $regbmem8,$memgr8 */
+  {
+    XC16X_INSN_ADDCBRM2, "addcbrm2", "addcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $memgr8,$regbmem8 */
+  {
+    XC16X_INSN_ADDCBRM3, "addcbrm3", "addcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $regb8,$memory */
+  {
+    XC16X_INSN_ADDCBRM, "addcbrm", "addcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* addcb $memory,$regb8 */
+  {
+    XC16X_INSN_ADDCBRM1, "addcbrm1", "addcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $regbmem8,$memgr8 */
+  {
+    XC16X_INSN_SUBCBRM3, "subcbrm3", "subcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $memgr8,$regbmem8 */
+  {
+    XC16X_INSN_SUBCBRM2, "subcbrm2", "subcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $regb8,$memory */
+  {
+    XC16X_INSN_SUBCBRM1, "subcbrm1", "subcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* subcb $memory,$regb8 */
+  {
+    XC16X_INSN_SUBCBRM, "subcbrm", "subcb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mul $src1,$src2 */
+  {
+    XC16X_INSN_MULS, "muls", "mul", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mulu $src1,$src2 */
+  {
+    XC16X_INSN_MULU, "mulu", "mulu", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* div $srdiv */
+  {
+    XC16X_INSN_DIV, "div", "div", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* divl $srdiv */
+  {
+    XC16X_INSN_DIVL, "divl", "divl", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* divlu $srdiv */
+  {
+    XC16X_INSN_DIVLU, "divlu", "divlu", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* divu $srdiv */
+  {
+    XC16X_INSN_DIVU, "divu", "divu", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cpl $dr */
+  {
+    XC16X_INSN_CPL, "cpl", "cpl", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cplb $drb */
+  {
+    XC16X_INSN_CPLB, "cplb", "cplb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* neg $dr */
+  {
+    XC16X_INSN_NEG, "neg", "neg", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* negb $drb */
+  {
+    XC16X_INSN_NEGB, "negb", "negb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* and $dr,$sr */
+  {
+    XC16X_INSN_ANDR, "andr", "and", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* or $dr,$sr */
+  {
+    XC16X_INSN_ORR, "orr", "or", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xor $dr,$sr */
+  {
+    XC16X_INSN_XORR, "xorr", "xor", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* andb $drb,$srb */
+  {
+    XC16X_INSN_ANDBR, "andbr", "andb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* orb $drb,$srb */
+  {
+    XC16X_INSN_ORBR, "orbr", "orb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xorb $drb,$srb */
+  {
+    XC16X_INSN_XORBR, "xorbr", "xorb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* and $dr,$hash$uimm3 */
+  {
+    XC16X_INSN_ANDRI, "andri", "and", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* or $dr,$hash$uimm3 */
+  {
+    XC16X_INSN_ORRI, "orri", "or", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xor $dr,$hash$uimm3 */
+  {
+    XC16X_INSN_XORRI, "xorri", "xor", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* andb $drb,$hash$uimm3 */
+  {
+    XC16X_INSN_ANDBRI, "andbri", "andb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* orb $drb,$hash$uimm3 */
+  {
+    XC16X_INSN_ORBRI, "orbri", "orb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xorb $drb,$hash$uimm3 */
+  {
+    XC16X_INSN_XORBRI, "xorbri", "xorb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* and $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_ANDRIM, "andrim", "and", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* or $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_ORRIM, "orrim", "or", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xor $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_XORRIM, "xorrim", "xor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* andb $regb8,$hash$uimm8 */
+  {
+    XC16X_INSN_ANDBRIM, "andbrim", "andb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* orb $regb8,$hash$uimm8 */
+  {
+    XC16X_INSN_ORBRIM, "orbrim", "orb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xorb $regb8,$hash$uimm8 */
+  {
+    XC16X_INSN_XORBRIM, "xorbrim", "xorb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* and $dr,[$sr2] */
+  {
+    XC16X_INSN_AND2, "and2", "and", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* or $dr,[$sr2] */
+  {
+    XC16X_INSN_OR2, "or2", "or", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xor $dr,[$sr2] */
+  {
+    XC16X_INSN_XOR2, "xor2", "xor", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* andb $drb,[$sr2] */
+  {
+    XC16X_INSN_ANDB2, "andb2", "andb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* orb $drb,[$sr2] */
+  {
+    XC16X_INSN_ORB2, "orb2", "orb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xorb $drb,[$sr2] */
+  {
+    XC16X_INSN_XORB2, "xorb2", "xorb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* and $dr,[$sr2+] */
+  {
+    XC16X_INSN_AND2I, "and2i", "and", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* or $dr,[$sr2+] */
+  {
+    XC16X_INSN_OR2I, "or2i", "or", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xor $dr,[$sr2+] */
+  {
+    XC16X_INSN_XOR2I, "xor2i", "xor", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* andb $drb,[$sr2+] */
+  {
+    XC16X_INSN_ANDB2I, "andb2i", "andb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* orb $drb,[$sr2+] */
+  {
+    XC16X_INSN_ORB2I, "orb2i", "orb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xorb $drb,[$sr2+] */
+  {
+    XC16X_INSN_XORB2I, "xorb2i", "xorb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* and $pof$reg8,$upof16 */
+  {
+    XC16X_INSN_ANDPOFR, "andpofr", "and", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* or $pof$reg8,$upof16 */
+  {
+    XC16X_INSN_ORPOFR, "orpofr", "or", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xor $pof$reg8,$upof16 */
+  {
+    XC16X_INSN_XORPOFR, "xorpofr", "xor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* andb $pof$regb8,$upof16 */
+  {
+    XC16X_INSN_ANDBPOFR, "andbpofr", "andb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* orb $pof$regb8,$upof16 */
+  {
+    XC16X_INSN_ORBPOFR, "orbpofr", "orb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xorb $pof$regb8,$upof16 */
+  {
+    XC16X_INSN_XORBPOFR, "xorbpofr", "xorb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* and $pof$upof16,$reg8 */
+  {
+    XC16X_INSN_ANDRPOFR, "andrpofr", "and", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* or $pof$upof16,$reg8 */
+  {
+    XC16X_INSN_ORRPOFR, "orrpofr", "or", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xor $pof$upof16,$reg8 */
+  {
+    XC16X_INSN_XORRPOFR, "xorrpofr", "xor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* andb $pof$upof16,$regb8 */
+  {
+    XC16X_INSN_ANDBRPOFR, "andbrpofr", "andb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* orb $pof$upof16,$regb8 */
+  {
+    XC16X_INSN_ORBRPOFR, "orbrpofr", "orb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xorb $pof$upof16,$regb8 */
+  {
+    XC16X_INSN_XORBRPOFR, "xorbrpofr", "xorb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* and $regmem8,$memgr8 */
+  {
+    XC16X_INSN_ANDRM2, "andrm2", "and", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* and $memgr8,$regmem8 */
+  {
+    XC16X_INSN_ANDRM3, "andrm3", "and", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* and $reg8,$memory */
+  {
+    XC16X_INSN_ANDRM, "andrm", "and", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* and $memory,$reg8 */
+  {
+    XC16X_INSN_ANDRM1, "andrm1", "and", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* or $regmem8,$memgr8 */
+  {
+    XC16X_INSN_ORRM3, "orrm3", "or", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* or $memgr8,$regmem8 */
+  {
+    XC16X_INSN_ORRM2, "orrm2", "or", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* or $reg8,$memory */
+  {
+    XC16X_INSN_ORRM1, "orrm1", "or", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* or $memory,$reg8 */
+  {
+    XC16X_INSN_ORRM, "orrm", "or", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xor $regmem8,$memgr8 */
+  {
+    XC16X_INSN_XORRM3, "xorrm3", "xor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xor $memgr8,$regmem8 */
+  {
+    XC16X_INSN_XORRM2, "xorrm2", "xor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xor $reg8,$memory */
+  {
+    XC16X_INSN_XORRM1, "xorrm1", "xor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xor $memory,$reg8 */
+  {
+    XC16X_INSN_XORRM, "xorrm", "xor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* andb $regbmem8,$memgr8 */
+  {
+    XC16X_INSN_ANDBRM2, "andbrm2", "andb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* andb $memgr8,$regbmem8 */
+  {
+    XC16X_INSN_ANDBRM3, "andbrm3", "andb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* andb $regb8,$memory */
+  {
+    XC16X_INSN_ANDBRM, "andbrm", "andb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* andb $memory,$regb8 */
+  {
+    XC16X_INSN_ANDBRM1, "andbrm1", "andb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* orb $regbmem8,$memgr8 */
+  {
+    XC16X_INSN_ORBRM3, "orbrm3", "orb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* orb $memgr8,$regbmem8 */
+  {
+    XC16X_INSN_ORBRM2, "orbrm2", "orb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* orb $regb8,$memory */
+  {
+    XC16X_INSN_ORBRM1, "orbrm1", "orb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* orb $memory,$regb8 */
+  {
+    XC16X_INSN_ORBRM, "orbrm", "orb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xorb $regbmem8,$memgr8 */
+  {
+    XC16X_INSN_XORBRM3, "xorbrm3", "xorb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xorb $memgr8,$regbmem8 */
+  {
+    XC16X_INSN_XORBRM2, "xorbrm2", "xorb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xorb $regb8,$memory */
+  {
+    XC16X_INSN_XORBRM1, "xorbrm1", "xorb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* xorb $memory,$regb8 */
+  {
+    XC16X_INSN_XORBRM, "xorbrm", "xorb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $dr,$sr */
+  {
+    XC16X_INSN_MOVR, "movr", "mov", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $drb,$srb */
+  {
+    XC16X_INSN_MOVRB, "movrb", "movb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $dri,$hash$u4 */
+  {
+    XC16X_INSN_MOVRI, "movri", "mov", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $srb,$hash$u4 */
+  {
+    XC16X_INSN_MOVBRI, "movbri", "movb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_MOVI, "movi", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $regb8,$hash$uimm8 */
+  {
+    XC16X_INSN_MOVBI, "movbi", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $dr,[$sr] */
+  {
+    XC16X_INSN_MOVR2, "movr2", "mov", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $drb,[$sr] */
+  {
+    XC16X_INSN_MOVBR2, "movbr2", "movb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov [$sr],$dr */
+  {
+    XC16X_INSN_MOVRI2, "movri2", "mov", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb [$sr],$drb */
+  {
+    XC16X_INSN_MOVBRI2, "movbri2", "movb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov [-$sr],$dr */
+  {
+    XC16X_INSN_MOVRI3, "movri3", "mov", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb [-$sr],$drb */
+  {
+    XC16X_INSN_MOVBRI3, "movbri3", "movb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $dr,[$sr+] */
+  {
+    XC16X_INSN_MOV2I, "mov2i", "mov", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $drb,[$sr+] */
+  {
+    XC16X_INSN_MOVB2I, "movb2i", "movb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov [$dr],[$sr] */
+  {
+    XC16X_INSN_MOV6I, "mov6i", "mov", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb [$dr],[$sr] */
+  {
+    XC16X_INSN_MOVB6I, "movb6i", "movb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov [$dr+],[$sr] */
+  {
+    XC16X_INSN_MOV7I, "mov7i", "mov", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb [$dr+],[$sr] */
+  {
+    XC16X_INSN_MOVB7I, "movb7i", "movb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov [$dr],[$sr+] */
+  {
+    XC16X_INSN_MOV8I, "mov8i", "mov", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb [$dr],[$sr+] */
+  {
+    XC16X_INSN_MOVB8I, "movb8i", "movb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $dr,[$sr+$hash$uimm16] */
+  {
+    XC16X_INSN_MOV9I, "mov9i", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $drb,[$sr+$hash$uimm16] */
+  {
+    XC16X_INSN_MOVB9I, "movb9i", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov [$sr+$hash$uimm16],$dr */
+  {
+    XC16X_INSN_MOV10I, "mov10i", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb [$sr+$hash$uimm16],$drb */
+  {
+    XC16X_INSN_MOVB10I, "movb10i", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov [$src2],$memory */
+  {
+    XC16X_INSN_MOVRI11, "movri11", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb [$src2],$memory */
+  {
+    XC16X_INSN_MOVBRI11, "movbri11", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $memory,[$src2] */
+  {
+    XC16X_INSN_MOVRI12, "movri12", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $memory,[$src2] */
+  {
+    XC16X_INSN_MOVBRI12, "movbri12", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $regoff8,$hash$pof$upof16 */
+  {
+    XC16X_INSN_MOVEHM5, "movehm5", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $regoff8,$hash$pag$upag16 */
+  {
+    XC16X_INSN_MOVEHM6, "movehm6", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $regoff8,$hash$segm$useg16 */
+  {
+    XC16X_INSN_MOVEHM7, "movehm7", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $regoff8,$hash$sof$usof16 */
+  {
+    XC16X_INSN_MOVEHM8, "movehm8", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $regb8,$hash$pof$uimm8 */
+  {
+    XC16X_INSN_MOVEHM9, "movehm9", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $regoff8,$hash$pag$uimm8 */
+  {
+    XC16X_INSN_MOVEHM10, "movehm10", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $regoff8,$pof$upof16 */
+  {
+    XC16X_INSN_MOVRMP, "movrmp", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $regb8,$pof$upof16 */
+  {
+    XC16X_INSN_MOVRMP1, "movrmp1", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $regoff8,$pag$upag16 */
+  {
+    XC16X_INSN_MOVRMP2, "movrmp2", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $regb8,$pag$upag16 */
+  {
+    XC16X_INSN_MOVRMP3, "movrmp3", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $pof$upof16,$regoff8 */
+  {
+    XC16X_INSN_MOVRMP4, "movrmp4", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $pof$upof16,$regb8 */
+  {
+    XC16X_INSN_MOVRMP5, "movrmp5", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $dri,$hash$pof$u4 */
+  {
+    XC16X_INSN_MOVEHM1, "movehm1", "mov", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $srb,$hash$pof$u4 */
+  {
+    XC16X_INSN_MOVEHM2, "movehm2", "movb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $dri,$hash$pag$u4 */
+  {
+    XC16X_INSN_MOVEHM3, "movehm3", "mov", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $srb,$hash$pag$u4 */
+  {
+    XC16X_INSN_MOVEHM4, "movehm4", "movb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $regmem8,$memgr8 */
+  {
+    XC16X_INSN_MVE12, "mve12", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $memgr8,$regmem8 */
+  {
+    XC16X_INSN_MVE13, "mve13", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $reg8,$memory */
+  {
+    XC16X_INSN_MOVER12, "mover12", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* mov $memory,$reg8 */
+  {
+    XC16X_INSN_MVR13, "mvr13", "mov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $regbmem8,$memgr8 */
+  {
+    XC16X_INSN_MVER12, "mver12", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $memgr8,$regbmem8 */
+  {
+    XC16X_INSN_MVER13, "mver13", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $regb8,$memory */
+  {
+    XC16X_INSN_MOVR12, "movr12", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movb $memory,$regb8 */
+  {
+    XC16X_INSN_MOVR13, "movr13", "movb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbs $sr,$drb */
+  {
+    XC16X_INSN_MOVBSRR, "movbsrr", "movbs", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbz $sr,$drb */
+  {
+    XC16X_INSN_MOVBZRR, "movbzrr", "movbz", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbs $regmem8,$pof$upof16 */
+  {
+    XC16X_INSN_MOVBSRPOFM, "movbsrpofm", "movbs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbs $pof$upof16,$regbmem8 */
+  {
+    XC16X_INSN_MOVBSPOFMR, "movbspofmr", "movbs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbz $reg8,$pof$upof16 */
+  {
+    XC16X_INSN_MOVBZRPOFM, "movbzrpofm", "movbz", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbz $pof$upof16,$regb8 */
+  {
+    XC16X_INSN_MOVBZPOFMR, "movbzpofmr", "movbz", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbs $regmem8,$memgr8 */
+  {
+    XC16X_INSN_MOVEBS14, "movebs14", "movbs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbs $memgr8,$regbmem8 */
+  {
+    XC16X_INSN_MOVEBS15, "movebs15", "movbs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbs $reg8,$memory */
+  {
+    XC16X_INSN_MOVERBS14, "moverbs14", "movbs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbs $memory,$regb8 */
+  {
+    XC16X_INSN_MOVRBS15, "movrbs15", "movbs", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbz $regmem8,$memgr8 */
+  {
+    XC16X_INSN_MOVEBZ14, "movebz14", "movbz", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbz $memgr8,$regbmem8 */
+  {
+    XC16X_INSN_MOVEBZ15, "movebz15", "movbz", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbz $reg8,$memory */
+  {
+    XC16X_INSN_MOVERBZ14, "moverbz14", "movbz", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbz $memory,$regb8 */
+  {
+    XC16X_INSN_MOVRBZ15, "movrbz15", "movbz", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbs $sr,$drb */
+  {
+    XC16X_INSN_MOVRBS, "movrbs", "movbs", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* movbz $sr,$drb */
+  {
+    XC16X_INSN_MOVRBZ, "movrbz", "movbz", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpa+ $extcond,$caddr */
+  {
+    XC16X_INSN_JMPA0, "jmpa0", "jmpa+", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpa $extcond,$caddr */
+  {
+    XC16X_INSN_JMPA1, "jmpa1", "jmpa", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpa- $extcond,$caddr */
+  {
+    XC16X_INSN_JMPA_, "jmpa-", "jmpa-", 32,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpi $icond,[$sr] */
+  {
+    XC16X_INSN_JMPI, "jmpi", "jmpi", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_NENZ, "jmpr_nenz", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_SGT, "jmpr_sgt", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_Z, "jmpr_z", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_V, "jmpr_v", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_NV, "jmpr_nv", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_N, "jmpr_n", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_NN, "jmpr_nn", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_C, "jmpr_c", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_NC, "jmpr_nc", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_EQ, "jmpr_eq", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_NE, "jmpr_ne", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_ULT, "jmpr_ult", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_ULE, "jmpr_ule", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_UGE, "jmpr_uge", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_UGT, "jmpr_ugt", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_SLE, "jmpr_sle", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_SGE, "jmpr_sge", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_NET, "jmpr_net", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_UC, "jmpr_uc", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmpr $cond,$rel */
+  {
+    XC16X_INSN_JMPR_SLT, "jmpr_slt", "jmpr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmps $hash$segm$useg8,$hash$sof$usof16 */
+  {
+    XC16X_INSN_JMPSEG, "jmpseg", "jmps", 32,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jmps $seg,$caddr */
+  {
+    XC16X_INSN_JMPS, "jmps", "jmps", 32,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jb $genreg$dot$qlobit,$relhi */
+  {
+    XC16X_INSN_JB, "jb", "jb", 32,
+    { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jbc $genreg$dot$qlobit,$relhi */
+  {
+    XC16X_INSN_JBC, "jbc", "jbc", 32,
+    { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jnb $genreg$dot$qlobit,$relhi */
+  {
+    XC16X_INSN_JNB, "jnb", "jnb", 32,
+    { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* jnbs $genreg$dot$qlobit,$relhi */
+  {
+    XC16X_INSN_JNBS, "jnbs", "jnbs", 32,
+    { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* calla+ $extcond,$caddr */
+  {
+    XC16X_INSN_CALLA0, "calla0", "calla+", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* calla $extcond,$caddr */
+  {
+    XC16X_INSN_CALLA1, "calla1", "calla", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* calla- $extcond,$caddr */
+  {
+    XC16X_INSN_CALLA_, "calla-", "calla-", 32,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* calli $icond,[$sr] */
+  {
+    XC16X_INSN_CALLI, "calli", "calli", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* callr $rel */
+  {
+    XC16X_INSN_CALLR, "callr", "callr", 16,
+    { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* calls $hash$segm$useg8,$hash$sof$usof16 */
+  {
+    XC16X_INSN_CALLSEG, "callseg", "calls", 32,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* calls $seg,$caddr */
+  {
+    XC16X_INSN_CALLS, "calls", "calls", 32,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* pcall $reg8,$caddr */
+  {
+    XC16X_INSN_PCALL, "pcall", "pcall", 32,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* trap $hash$uimm7 */
+  {
+    XC16X_INSN_TRAP, "trap", "trap", 16,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* ret */
+  {
+    XC16X_INSN_RET, "ret", "ret", 16,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* rets */
+  {
+    XC16X_INSN_RETS, "rets", "rets", 16,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* retp $reg8 */
+  {
+    XC16X_INSN_RETP, "retp", "retp", 16,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* reti */
+  {
+    XC16X_INSN_RETI, "reti", "reti", 16,
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* pop $reg8 */
+  {
+    XC16X_INSN_POP, "pop", "pop", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* push $reg8 */
+  {
+    XC16X_INSN_PUSH, "push", "push", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* scxt $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_SCXTI, "scxti", "scxt", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* scxt $reg8,$pof$upof16 */
+  {
+    XC16X_INSN_SCXTRPOFM, "scxtrpofm", "scxt", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* scxt $regmem8,$memgr8 */
+  {
+    XC16X_INSN_SCXTMG, "scxtmg", "scxt", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* scxt $reg8,$memory */
+  {
+    XC16X_INSN_SCXTM, "scxtm", "scxt", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* nop */
+  {
+    XC16X_INSN_NOP, "nop", "nop", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* srst */
+  {
+    XC16X_INSN_SRSTM, "srstm", "srst", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* idle */
+  {
+    XC16X_INSN_IDLEM, "idlem", "idle", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* pwrdn */
+  {
+    XC16X_INSN_PWRDNM, "pwrdnm", "pwrdn", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* diswdt */
+  {
+    XC16X_INSN_DISWDTM, "diswdtm", "diswdt", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* enwdt */
+  {
+    XC16X_INSN_ENWDTM, "enwdtm", "enwdt", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* einit */
+  {
+    XC16X_INSN_EINITM, "einitm", "einit", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* srvwdt */
+  {
+    XC16X_INSN_SRVWDTM, "srvwdtm", "srvwdt", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* sbrk */
+  {
+    XC16X_INSN_SBRK, "sbrk", "sbrk", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* atomic $hash$uimm2 */
+  {
+    XC16X_INSN_ATOMIC, "atomic", "atomic", 16,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* extr $hash$uimm2 */
+  {
+    XC16X_INSN_EXTR, "extr", "extr", 16,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* extp $sr,$hash$uimm2 */
+  {
+    XC16X_INSN_EXTP, "extp", "extp", 16,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* extp $hash$pagenum,$hash$uimm2 */
+  {
+    XC16X_INSN_EXTP1, "extp1", "extp", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* extp $hash$pag$upag16,$hash$uimm2 */
+  {
+    XC16X_INSN_EXTPG1, "extpg1", "extp", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* extpr $sr,$hash$uimm2 */
+  {
+    XC16X_INSN_EXTPR, "extpr", "extpr", 16,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* extpr $hash$pagenum,$hash$uimm2 */
+  {
+    XC16X_INSN_EXTPR1, "extpr1", "extpr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* exts $sr,$hash$uimm2 */
+  {
+    XC16X_INSN_EXTS, "exts", "exts", 16,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* exts $hash$seghi8,$hash$uimm2 */
+  {
+    XC16X_INSN_EXTS1, "exts1", "exts", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* extsr $sr,$hash$uimm2 */
+  {
+    XC16X_INSN_EXTSR, "extsr", "extsr", 16,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* extsr $hash$seghi8,$hash$uimm2 */
+  {
+    XC16X_INSN_EXTSR1, "extsr1", "extsr", 32,
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* prior $dr,$sr */
+  {
+    XC16X_INSN_PRIOR, "prior", "prior", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $RegNam */
+  {
+    XC16X_INSN_BCLR18, "bclr18", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR0, "bclr0", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR1, "bclr1", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR2, "bclr2", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR3, "bclr3", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR4, "bclr4", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR5, "bclr5", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR6, "bclr6", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR7, "bclr7", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR8, "bclr8", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR9, "bclr9", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR10, "bclr10", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR11, "bclr11", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR12, "bclr12", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR13, "bclr13", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR14, "bclr14", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    XC16X_INSN_BCLR15, "bclr15", "bclr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $RegNam */
+  {
+    XC16X_INSN_BSET19, "bset19", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET0, "bset0", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET1, "bset1", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET2, "bset2", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET3, "bset3", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET4, "bset4", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET5, "bset5", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET6, "bset6", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET7, "bset7", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET8, "bset8", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET9, "bset9", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET10, "bset10", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET11, "bset11", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET12, "bset12", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET13, "bset13", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET14, "bset14", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    XC16X_INSN_BSET15, "bset15", "bset", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bmov $reghi8$dot$qhibit,$reg8$dot$qlobit */
+  {
+    XC16X_INSN_BMOV, "bmov", "bmov", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit */
+  {
+    XC16X_INSN_BMOVN, "bmovn", "bmovn", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* band $reghi8$dot$qhibit,$reg8$dot$qlobit */
+  {
+    XC16X_INSN_BAND, "band", "band", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bor $reghi8$dot$qhibit,$reg8$dot$qlobit */
+  {
+    XC16X_INSN_BOR, "bor", "bor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bxor $reghi8$dot$qhibit,$reg8$dot$qlobit */
+  {
+    XC16X_INSN_BXOR, "bxor", "bxor", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit */
+  {
+    XC16X_INSN_BCMP, "bcmp", "bcmp", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bfldl $reg8,$hash$mask8,$hash$datahi8 */
+  {
+    XC16X_INSN_BFLDL, "bfldl", "bfldl", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* bfldh $reg8,$hash$masklo8,$hash$data8 */
+  {
+    XC16X_INSN_BFLDH, "bfldh", "bfldh", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmp $src1,$src2 */
+  {
+    XC16X_INSN_CMPR, "cmpr", "cmp", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpb $drb,$srb */
+  {
+    XC16X_INSN_CMPBR, "cmpbr", "cmpb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmp $src1,$hash$uimm3 */
+  {
+    XC16X_INSN_CMPRI, "cmpri", "cmp", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpb $drb,$hash$uimm3 */
+  {
+    XC16X_INSN_CMPBRI, "cmpbri", "cmpb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmp $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_CMPI, "cmpi", "cmp", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpb $regb8,$hash$uimm8 */
+  {
+    XC16X_INSN_CMPBI, "cmpbi", "cmpb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmp $dr,[$sr2] */
+  {
+    XC16X_INSN_CMPR2, "cmpr2", "cmp", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpb $drb,[$sr2] */
+  {
+    XC16X_INSN_CMPBR2, "cmpbr2", "cmpb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmp $dr,[$sr2+] */
+  {
+    XC16X_INSN_CMP2I, "cmp2i", "cmp", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpb $drb,[$sr2+] */
+  {
+    XC16X_INSN_CMPB2I, "cmpb2i", "cmpb", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmp $reg8,$pof$upof16 */
+  {
+    XC16X_INSN_CMP04, "cmp04", "cmp", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpb $regb8,$pof$upof16 */
+  {
+    XC16X_INSN_CMPB4, "cmpb4", "cmpb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmp $regmem8,$memgr8 */
+  {
+    XC16X_INSN_CMP004, "cmp004", "cmp", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmp $reg8,$memory */
+  {
+    XC16X_INSN_CMP0004, "cmp0004", "cmp", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpb $regbmem8,$memgr8 */
+  {
+    XC16X_INSN_CMPB04, "cmpb04", "cmpb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpb $regb8,$memory */
+  {
+    XC16X_INSN_CMPB004, "cmpb004", "cmpb", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpd1 $sr,$hash$uimm4 */
+  {
+    XC16X_INSN_CMPD1RI, "cmpd1ri", "cmpd1", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpd2 $sr,$hash$uimm4 */
+  {
+    XC16X_INSN_CMPD2RI, "cmpd2ri", "cmpd2", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpi1 $sr,$hash$uimm4 */
+  {
+    XC16X_INSN_CMPI1RI, "cmpi1ri", "cmpi1", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpi2 $sr,$hash$uimm4 */
+  {
+    XC16X_INSN_CMPI2RI, "cmpi2ri", "cmpi2", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpd1 $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_CMPD1RIM, "cmpd1rim", "cmpd1", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpd2 $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_CMPD2RIM, "cmpd2rim", "cmpd2", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpi1 $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_CMPI1RIM, "cmpi1rim", "cmpi1", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpi2 $reg8,$hash$uimm16 */
+  {
+    XC16X_INSN_CMPI2RIM, "cmpi2rim", "cmpi2", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpd1 $reg8,$pof$upof16 */
+  {
+    XC16X_INSN_CMPD1RP, "cmpd1rp", "cmpd1", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpd2 $reg8,$pof$upof16 */
+  {
+    XC16X_INSN_CMPD2RP, "cmpd2rp", "cmpd2", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpi1 $reg8,$pof$upof16 */
+  {
+    XC16X_INSN_CMPI1RP, "cmpi1rp", "cmpi1", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpi2 $reg8,$pof$upof16 */
+  {
+    XC16X_INSN_CMPI2RP, "cmpi2rp", "cmpi2", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpd1 $regmem8,$memgr8 */
+  {
+    XC16X_INSN_CMPD1RM, "cmpd1rm", "cmpd1", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpd2 $regmem8,$memgr8 */
+  {
+    XC16X_INSN_CMPD2RM, "cmpd2rm", "cmpd2", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpi1 $regmem8,$memgr8 */
+  {
+    XC16X_INSN_CMPI1RM, "cmpi1rm", "cmpi1", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpi2 $regmem8,$memgr8 */
+  {
+    XC16X_INSN_CMPI2RM, "cmpi2rm", "cmpi2", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpd1 $reg8,$memory */
+  {
+    XC16X_INSN_CMPD1RMI, "cmpd1rmi", "cmpd1", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpd2 $reg8,$memory */
+  {
+    XC16X_INSN_CMPD2RMI, "cmpd2rmi", "cmpd2", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpi1 $reg8,$memory */
+  {
+    XC16X_INSN_CMPI1RMI, "cmpi1rmi", "cmpi1", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* cmpi2 $reg8,$memory */
+  {
+    XC16X_INSN_CMPI2RMI, "cmpi2rmi", "cmpi2", 32,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* shl $dr,$sr */
+  {
+    XC16X_INSN_SHLR, "shlr", "shl", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* shr $dr,$sr */
+  {
+    XC16X_INSN_SHRR, "shrr", "shr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* rol $dr,$sr */
+  {
+    XC16X_INSN_ROLR, "rolr", "rol", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* ror $dr,$sr */
+  {
+    XC16X_INSN_RORR, "rorr", "ror", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* ashr $dr,$sr */
+  {
+    XC16X_INSN_ASHRR, "ashrr", "ashr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* shl $sr,$hash$uimm4 */
+  {
+    XC16X_INSN_SHLRI, "shlri", "shl", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* shr $sr,$hash$uimm4 */
+  {
+    XC16X_INSN_SHRRI, "shrri", "shr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* rol $sr,$hash$uimm4 */
+  {
+    XC16X_INSN_ROLRI, "rolri", "rol", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* ror $sr,$hash$uimm4 */
+  {
+    XC16X_INSN_RORRI, "rorri", "ror", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+/* ashr $sr,$hash$uimm4 */
+  {
+    XC16X_INSN_ASHRRI, "ashrri", "ashr", 16,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
+  },
+};
+
+#undef OP
+#undef A
+
+/* Initialize anything needed to be done once, before any cpu_open call.  */
+
+static void
+init_tables (void)
+{
+}
+
+static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
+static void build_hw_table      (CGEN_CPU_TABLE *);
+static void build_ifield_table  (CGEN_CPU_TABLE *);
+static void build_operand_table (CGEN_CPU_TABLE *);
+static void build_insn_table    (CGEN_CPU_TABLE *);
+static void xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *);
+
+/* Subroutine of xc16x_cgen_cpu_open to look up a mach via its bfd name.  */
+
+static const CGEN_MACH *
+lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
+{
+  while (table->name)
+    {
+      if (strcmp (name, table->bfd_name) == 0)
+	return table;
+      ++table;
+    }
+  abort ();
+}
+
+/* Subroutine of xc16x_cgen_cpu_open to build the hardware table.  */
+
+static void
+build_hw_table (CGEN_CPU_TABLE *cd)
+{
+  int i;
+  int machs = cd->machs;
+  const CGEN_HW_ENTRY *init = & xc16x_cgen_hw_table[0];
+  /* MAX_HW is only an upper bound on the number of selected entries.
+     However each entry is indexed by it's enum so there can be holes in
+     the table.  */
+  const CGEN_HW_ENTRY **selected =
+    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
+
+  cd->hw_table.init_entries = init;
+  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
+  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
+  /* ??? For now we just use machs to determine which ones we want.  */
+  for (i = 0; init[i].name != NULL; ++i)
+    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
+	& machs)
+      selected[init[i].type] = &init[i];
+  cd->hw_table.entries = selected;
+  cd->hw_table.num_entries = MAX_HW;
+}
+
+/* Subroutine of xc16x_cgen_cpu_open to build the hardware table.  */
+
+static void
+build_ifield_table (CGEN_CPU_TABLE *cd)
+{
+  cd->ifld_table = & xc16x_cgen_ifld_table[0];
+}
+
+/* Subroutine of xc16x_cgen_cpu_open to build the hardware table.  */
+
+static void
+build_operand_table (CGEN_CPU_TABLE *cd)
+{
+  int i;
+  int machs = cd->machs;
+  const CGEN_OPERAND *init = & xc16x_cgen_operand_table[0];
+  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
+     However each entry is indexed by it's enum so there can be holes in
+     the table.  */
+  const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
+
+  cd->operand_table.init_entries = init;
+  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
+  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
+  /* ??? For now we just use mach to determine which ones we want.  */
+  for (i = 0; init[i].name != NULL; ++i)
+    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
+	& machs)
+      selected[init[i].type] = &init[i];
+  cd->operand_table.entries = selected;
+  cd->operand_table.num_entries = MAX_OPERANDS;
+}
+
+/* Subroutine of xc16x_cgen_cpu_open to build the hardware table.
+   ??? This could leave out insns not supported by the specified mach/isa,
+   but that would cause errors like "foo only supported by bar" to become
+   "unknown insn", so for now we include all insns and require the app to
+   do the checking later.
+   ??? On the other hand, parsing of such insns may require their hardware or
+   operand elements to be in the table [which they mightn't be].  */
+
+static void
+build_insn_table (CGEN_CPU_TABLE *cd)
+{
+  int i;
+  const CGEN_IBASE *ib = & xc16x_cgen_insn_table[0];
+  CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
+
+  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
+  for (i = 0; i < MAX_INSNS; ++i)
+    insns[i].base = &ib[i];
+  cd->insn_table.init_entries = insns;
+  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
+  cd->insn_table.num_init_entries = MAX_INSNS;
+}
+
+/* Subroutine of xc16x_cgen_cpu_open to rebuild the tables.  */
+
+static void
+xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
+{
+  int i;
+  CGEN_BITSET *isas = cd->isas;
+  unsigned int machs = cd->machs;
+
+  cd->int_insn_p = CGEN_INT_INSN_P;
+
+  /* Data derived from the isa spec.  */
+#define UNSET (CGEN_SIZE_UNKNOWN + 1)
+  cd->default_insn_bitsize = UNSET;
+  cd->base_insn_bitsize = UNSET;
+  cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
+  cd->max_insn_bitsize = 0;
+  for (i = 0; i < MAX_ISAS; ++i)
+    if (cgen_bitset_contains (isas, i))
+      {
+	const CGEN_ISA *isa = & xc16x_cgen_isa_table[i];
+
+	/* Default insn sizes of all selected isas must be
+	   equal or we set the result to 0, meaning "unknown".  */
+	if (cd->default_insn_bitsize == UNSET)
+	  cd->default_insn_bitsize = isa->default_insn_bitsize;
+	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
+	  ; /* This is ok.  */
+	else
+	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+	/* Base insn sizes of all selected isas must be equal
+	   or we set the result to 0, meaning "unknown".  */
+	if (cd->base_insn_bitsize == UNSET)
+	  cd->base_insn_bitsize = isa->base_insn_bitsize;
+	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
+	  ; /* This is ok.  */
+	else
+	  cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
+
+	/* Set min,max insn sizes.  */
+	if (isa->min_insn_bitsize < cd->min_insn_bitsize)
+	  cd->min_insn_bitsize = isa->min_insn_bitsize;
+	if (isa->max_insn_bitsize > cd->max_insn_bitsize)
+	  cd->max_insn_bitsize = isa->max_insn_bitsize;
+      }
+
+  /* Data derived from the mach spec.  */
+  for (i = 0; i < MAX_MACHS; ++i)
+    if (((1 << i) & machs) != 0)
+      {
+	const CGEN_MACH *mach = & xc16x_cgen_mach_table[i];
+
+	if (mach->insn_chunk_bitsize != 0)
+	{
+	  if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
+	    {
+	      fprintf (stderr, "xc16x_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
+		       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+	      abort ();
+	    }
+
+ 	  cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
+	}
+      }
+
+  /* Determine which hw elements are used by MACH.  */
+  build_hw_table (cd);
+
+  /* Build the ifield table.  */
+  build_ifield_table (cd);
+
+  /* Determine which operands are used by MACH/ISA.  */
+  build_operand_table (cd);
+
+  /* Build the instruction table.  */
+  build_insn_table (cd);
+}
+
+/* Initialize a cpu table and return a descriptor.
+   It's much like opening a file, and must be the first function called.
+   The arguments are a set of (type/value) pairs, terminated with
+   CGEN_CPU_OPEN_END.
+
+   Currently supported values:
+   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
+   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
+   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
+   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
+   CGEN_CPU_OPEN_END:     terminates arguments
+
+   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
+   precluded.
+
+   ??? We only support ISO C stdargs here, not K&R.
+   Laziness, plus experiment to see if anything requires K&R - eventually
+   K&R will no longer be supported - e.g. GDB is currently trying this.  */
+
+CGEN_CPU_DESC
+xc16x_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
+{
+  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
+  static int init_p;
+  CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
+  unsigned int machs = 0; /* 0 = "unspecified" */
+  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
+  va_list ap;
+
+  if (! init_p)
+    {
+      init_tables ();
+      init_p = 1;
+    }
+
+  memset (cd, 0, sizeof (*cd));
+
+  va_start (ap, arg_type);
+  while (arg_type != CGEN_CPU_OPEN_END)
+    {
+      switch (arg_type)
+	{
+	case CGEN_CPU_OPEN_ISAS :
+	  isas = va_arg (ap, CGEN_BITSET *);
+	  break;
+	case CGEN_CPU_OPEN_MACHS :
+	  machs = va_arg (ap, unsigned int);
+	  break;
+	case CGEN_CPU_OPEN_BFDMACH :
+	  {
+	    const char *name = va_arg (ap, const char *);
+	    const CGEN_MACH *mach =
+	      lookup_mach_via_bfd_name (xc16x_cgen_mach_table, name);
+
+	    machs |= 1 << mach->num;
+	    break;
+	  }
+	case CGEN_CPU_OPEN_ENDIAN :
+	  endian = va_arg (ap, enum cgen_endian);
+	  break;
+	default :
+	  fprintf (stderr, "xc16x_cgen_cpu_open: unsupported argument `%d'\n",
+		   arg_type);
+	  abort (); /* ??? return NULL? */
+	}
+      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
+    }
+  va_end (ap);
+
+  /* Mach unspecified means "all".  */
+  if (machs == 0)
+    machs = (1 << MAX_MACHS) - 1;
+  /* Base mach is always selected.  */
+  machs |= 1;
+  if (endian == CGEN_ENDIAN_UNKNOWN)
+    {
+      /* ??? If target has only one, could have a default.  */
+      fprintf (stderr, "xc16x_cgen_cpu_open: no endianness specified\n");
+      abort ();
+    }
+
+  cd->isas = cgen_bitset_copy (isas);
+  cd->machs = machs;
+  cd->endian = endian;
+  /* FIXME: for the sparc case we can determine insn-endianness statically.
+     The worry here is where both data and insn endian can be independently
+     chosen, in which case this function will need another argument.
+     Actually, will want to allow for more arguments in the future anyway.  */
+  cd->insn_endian = endian;
+
+  /* Table (re)builder.  */
+  cd->rebuild_tables = xc16x_cgen_rebuild_tables;
+  xc16x_cgen_rebuild_tables (cd);
+
+  /* Default to not allowing signed overflow.  */
+  cd->signed_overflow_ok_p = 0;
+  
+  return (CGEN_CPU_DESC) cd;
+}
+
+/* Cover fn to xc16x_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
+   MACH_NAME is the bfd name of the mach.  */
+
+CGEN_CPU_DESC
+xc16x_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
+{
+  return xc16x_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
+			       CGEN_CPU_OPEN_ENDIAN, endian,
+			       CGEN_CPU_OPEN_END);
+}
+
+/* Close a cpu table.
+   ??? This can live in a machine independent file, but there's currently
+   no place to put this file (there's no libcgen).  libopcodes is the wrong
+   place as some simulator ports use this but they don't use libopcodes.  */
+
+void
+xc16x_cgen_cpu_close (CGEN_CPU_DESC cd)
+{
+  unsigned int i;
+  const CGEN_INSN *insns;
+
+  if (cd->macro_insn_table.init_entries)
+    {
+      insns = cd->macro_insn_table.init_entries;
+      for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
+	if (CGEN_INSN_RX ((insns)))
+	  regfree (CGEN_INSN_RX (insns));
+    }
+
+  if (cd->insn_table.init_entries)
+    {
+      insns = cd->insn_table.init_entries;
+      for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
+	if (CGEN_INSN_RX (insns))
+	  regfree (CGEN_INSN_RX (insns));
+    }  
+
+  if (cd->macro_insn_table.init_entries)
+    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
+  if (cd->insn_table.init_entries)
+    free ((CGEN_INSN *) cd->insn_table.init_entries);
+
+  if (cd->hw_table.entries)
+    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+  if (cd->operand_table.entries)
+    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
+  free (cd);
+}
+
diff --git a/opcodes/xc16x-desc.h b/opcodes/xc16x-desc.h
new file mode 100644
index 0000000..c878197
--- /dev/null
+++ b/opcodes/xc16x-desc.h
@@ -0,0 +1,451 @@
+/* CPU data header for xc16x.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2005 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef XC16X_CPU_H
+#define XC16X_CPU_H
+
+#include "opcode/cgen-bitset.h"
+
+#define CGEN_ARCH xc16x
+
+/* Given symbol S, return xc16x_cgen_<S>.  */
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define CGEN_SYM(s) xc16x##_cgen_##s
+#else
+#define CGEN_SYM(s) xc16x/**/_cgen_/**/s
+#endif
+
+
+/* Selected cpu families.  */
+#define HAVE_CPU_XC16XBF
+
+#define CGEN_INSN_LSB0_P 1
+
+/* Minimum size of any insn (in bytes).  */
+#define CGEN_MIN_INSN_SIZE 2
+
+/* Maximum size of any insn (in bytes).  */
+#define CGEN_MAX_INSN_SIZE 4
+
+#define CGEN_INT_INSN_P 1
+
+/* Maximum number of syntax elements in an instruction.  */
+#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
+
+/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
+   e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
+   we can't hash on everything up to the space.  */
+#define CGEN_MNEMONIC_OPERANDS
+
+/* Maximum number of fields in an instruction.  */
+#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
+
+/* Enums.  */
+
+/* Enum declaration for insn format enums.  */
+typedef enum insn_op1 {
+  OP1_0, OP1_1, OP1_2, OP1_3
+ , OP1_4, OP1_5, OP1_6, OP1_7
+ , OP1_8, OP1_9, OP1_10, OP1_11
+ , OP1_12, OP1_13, OP1_14, OP1_15
+} INSN_OP1;
+
+/* Enum declaration for op2 enums.  */
+typedef enum insn_op2 {
+  OP2_0, OP2_1, OP2_2, OP2_3
+ , OP2_4, OP2_5, OP2_6, OP2_7
+ , OP2_8, OP2_9, OP2_10, OP2_11
+ , OP2_12, OP2_13, OP2_14, OP2_15
+} INSN_OP2;
+
+/* Enum declaration for bit set/clear enums.  */
+typedef enum insn_qcond {
+  QBIT_0, QBIT_1, QBIT_2, QBIT_3
+ , QBIT_4, QBIT_5, QBIT_6, QBIT_7
+ , QBIT_8, QBIT_9, QBIT_10, QBIT_11
+ , QBIT_12, QBIT_13, QBIT_14, QBIT_15
+} INSN_QCOND;
+
+/* Enum declaration for relative jump condition code op2 enums.  */
+typedef enum insn_rcond {
+  COND_UC = 0, COND_NET = 1, COND_Z = 2, COND_NE_NZ = 3
+ , COND_V = 4, COND_NV = 5, COND_N = 6, COND_NN = 7
+ , COND_C = 8, COND_NC = 9, COND_SGT = 10, COND_SLE = 11
+ , COND_SLT = 12, COND_SGE = 13, COND_UGT = 14, COND_ULE = 15
+ , COND_EQ = 2, COND_NE = 3, COND_ULT = 8, COND_UGE = 9
+} INSN_RCOND;
+
+/* Enum declaration for .  */
+typedef enum gr_names {
+  H_GR_R0, H_GR_R1, H_GR_R2, H_GR_R3
+ , H_GR_R4, H_GR_R5, H_GR_R6, H_GR_R7
+ , H_GR_R8, H_GR_R9, H_GR_R10, H_GR_R11
+ , H_GR_R12, H_GR_R13, H_GR_R14, H_GR_R15
+} GR_NAMES;
+
+/* Enum declaration for .  */
+typedef enum ext_names {
+  H_EXT_0X1 = 0, H_EXT_0X2 = 1, H_EXT_0X3 = 2, H_EXT_0X4 = 3
+ , H_EXT_1 = 0, H_EXT_2 = 1, H_EXT_3 = 2, H_EXT_4 = 3
+} EXT_NAMES;
+
+/* Enum declaration for .  */
+typedef enum psw_names {
+  H_PSW_IEN = 136, H_PSW_R0_11 = 240, H_PSW_R1_11 = 241, H_PSW_R2_11 = 242
+ , H_PSW_R3_11 = 243, H_PSW_R4_11 = 244, H_PSW_R5_11 = 245, H_PSW_R6_11 = 246
+ , H_PSW_R7_11 = 247, H_PSW_R8_11 = 248, H_PSW_R9_11 = 249, H_PSW_R10_11 = 250
+ , H_PSW_R11_11 = 251, H_PSW_R12_11 = 252, H_PSW_R13_11 = 253, H_PSW_R14_11 = 254
+ , H_PSW_R15_11 = 255
+} PSW_NAMES;
+
+/* Enum declaration for .  */
+typedef enum grb_names {
+  H_GRB_RL0, H_GRB_RH0, H_GRB_RL1, H_GRB_RH1
+ , H_GRB_RL2, H_GRB_RH2, H_GRB_RL3, H_GRB_RH3
+ , H_GRB_RL4, H_GRB_RH4, H_GRB_RL5, H_GRB_RH5
+ , H_GRB_RL6, H_GRB_RH6, H_GRB_RL7, H_GRB_RH7
+} GRB_NAMES;
+
+/* Enum declaration for .  */
+typedef enum conditioncode_names {
+  H_CC_CC_UC = 0, H_CC_CC_NET = 1, H_CC_CC_Z = 2, H_CC_CC_EQ = 2
+ , H_CC_CC_NZ = 3, H_CC_CC_NE = 3, H_CC_CC_V = 4, H_CC_CC_NV = 5
+ , H_CC_CC_N = 6, H_CC_CC_NN = 7, H_CC_CC_ULT = 8, H_CC_CC_UGE = 9
+ , H_CC_CC_C = 8, H_CC_CC_NC = 9, H_CC_CC_SGT = 10, H_CC_CC_SLE = 11
+ , H_CC_CC_SLT = 12, H_CC_CC_SGE = 13, H_CC_CC_UGT = 14, H_CC_CC_ULE = 15
+} CONDITIONCODE_NAMES;
+
+/* Enum declaration for .  */
+typedef enum extconditioncode_names {
+  H_ECC_CC_UC = 0, H_ECC_CC_NET = 2, H_ECC_CC_Z = 4, H_ECC_CC_EQ = 4
+ , H_ECC_CC_NZ = 6, H_ECC_CC_NE = 6, H_ECC_CC_V = 8, H_ECC_CC_NV = 10
+ , H_ECC_CC_N = 12, H_ECC_CC_NN = 14, H_ECC_CC_ULT = 16, H_ECC_CC_UGE = 18
+ , H_ECC_CC_C = 16, H_ECC_CC_NC = 18, H_ECC_CC_SGT = 20, H_ECC_CC_SLE = 22
+ , H_ECC_CC_SLT = 24, H_ECC_CC_SGE = 26, H_ECC_CC_UGT = 28, H_ECC_CC_ULE = 30
+ , H_ECC_CC_NUSR0 = 1, H_ECC_CC_NUSR1 = 3, H_ECC_CC_USR0 = 5, H_ECC_CC_USR1 = 7
+} EXTCONDITIONCODE_NAMES;
+
+/* Enum declaration for .  */
+typedef enum grb8_names {
+  H_GRB8_DPP0 = 0, H_GRB8_DPP1 = 1, H_GRB8_DPP2 = 2, H_GRB8_DPP3 = 3
+ , H_GRB8_PSW = 136, H_GRB8_CP = 8, H_GRB8_MDL = 7, H_GRB8_MDH = 6
+ , H_GRB8_MDC = 135, H_GRB8_SP = 9, H_GRB8_CSP = 4, H_GRB8_VECSEG = 137
+ , H_GRB8_STKOV = 10, H_GRB8_STKUN = 11, H_GRB8_CPUCON1 = 12, H_GRB8_CPUCON2 = 13
+ , H_GRB8_ZEROS = 142, H_GRB8_ONES = 143, H_GRB8_SPSEG = 134, H_GRB8_TFR = 214
+ , H_GRB8_RL0 = 240, H_GRB8_RH0 = 241, H_GRB8_RL1 = 242, H_GRB8_RH1 = 243
+ , H_GRB8_RL2 = 244, H_GRB8_RH2 = 245, H_GRB8_RL3 = 246, H_GRB8_RH3 = 247
+ , H_GRB8_RL4 = 248, H_GRB8_RH4 = 249, H_GRB8_RL5 = 250, H_GRB8_RH5 = 251
+ , H_GRB8_RL6 = 252, H_GRB8_RH6 = 253, H_GRB8_RL7 = 254, H_GRB8_RH7 = 255
+} GRB8_NAMES;
+
+/* Enum declaration for .  */
+typedef enum r8_names {
+  H_R8_DPP0 = 0, H_R8_DPP1 = 1, H_R8_DPP2 = 2, H_R8_DPP3 = 3
+ , H_R8_PSW = 136, H_R8_CP = 8, H_R8_MDL = 7, H_R8_MDH = 6
+ , H_R8_MDC = 135, H_R8_SP = 9, H_R8_CSP = 4, H_R8_VECSEG = 137
+ , H_R8_STKOV = 10, H_R8_STKUN = 11, H_R8_CPUCON1 = 12, H_R8_CPUCON2 = 13
+ , H_R8_ZEROS = 142, H_R8_ONES = 143, H_R8_SPSEG = 134, H_R8_TFR = 214
+ , H_R8_R0 = 240, H_R8_R1 = 241, H_R8_R2 = 242, H_R8_R3 = 243
+ , H_R8_R4 = 244, H_R8_R5 = 245, H_R8_R6 = 246, H_R8_R7 = 247
+ , H_R8_R8 = 248, H_R8_R9 = 249, H_R8_R10 = 250, H_R8_R11 = 251
+ , H_R8_R12 = 252, H_R8_R13 = 253, H_R8_R14 = 254, H_R8_R15 = 255
+} R8_NAMES;
+
+/* Enum declaration for .  */
+typedef enum regmem8_names {
+  H_REGMEM8_DPP0 = 0, H_REGMEM8_DPP1 = 1, H_REGMEM8_DPP2 = 2, H_REGMEM8_DPP3 = 3
+ , H_REGMEM8_PSW = 136, H_REGMEM8_CP = 8, H_REGMEM8_MDL = 7, H_REGMEM8_MDH = 6
+ , H_REGMEM8_MDC = 135, H_REGMEM8_SP = 9, H_REGMEM8_CSP = 4, H_REGMEM8_VECSEG = 137
+ , H_REGMEM8_STKOV = 10, H_REGMEM8_STKUN = 11, H_REGMEM8_CPUCON1 = 12, H_REGMEM8_CPUCON2 = 13
+ , H_REGMEM8_ZEROS = 142, H_REGMEM8_ONES = 143, H_REGMEM8_SPSEG = 134, H_REGMEM8_TFR = 214
+ , H_REGMEM8_R0 = 240, H_REGMEM8_R1 = 241, H_REGMEM8_R2 = 242, H_REGMEM8_R3 = 243
+ , H_REGMEM8_R4 = 244, H_REGMEM8_R5 = 245, H_REGMEM8_R6 = 246, H_REGMEM8_R7 = 247
+ , H_REGMEM8_R8 = 248, H_REGMEM8_R9 = 249, H_REGMEM8_R10 = 250, H_REGMEM8_R11 = 251
+ , H_REGMEM8_R12 = 252, H_REGMEM8_R13 = 253, H_REGMEM8_R14 = 254, H_REGMEM8_R15 = 255
+} REGMEM8_NAMES;
+
+/* Enum declaration for .  */
+typedef enum regdiv8_names {
+  H_REGDIV8_R0 = 0, H_REGDIV8_R1 = 17, H_REGDIV8_R2 = 34, H_REGDIV8_R3 = 51
+ , H_REGDIV8_R4 = 68, H_REGDIV8_R5 = 85, H_REGDIV8_R6 = 102, H_REGDIV8_R7 = 119
+ , H_REGDIV8_R8 = 136, H_REGDIV8_R9 = 153, H_REGDIV8_R10 = 170, H_REGDIV8_R11 = 187
+ , H_REGDIV8_R12 = 204, H_REGDIV8_R13 = 221, H_REGDIV8_R14 = 238, H_REGDIV8_R15 = 255
+} REGDIV8_NAMES;
+
+/* Enum declaration for .  */
+typedef enum reg0_name {
+  H_REG0_0X1 = 1, H_REG0_0X2 = 2, H_REG0_0X3 = 3, H_REG0_0X4 = 4
+ , H_REG0_0X5 = 5, H_REG0_0X6 = 6, H_REG0_0X7 = 7, H_REG0_0X8 = 8
+ , H_REG0_0X9 = 9, H_REG0_0XA = 10, H_REG0_0XB = 11, H_REG0_0XC = 12
+ , H_REG0_0XD = 13, H_REG0_0XE = 14, H_REG0_0XF = 15, H_REG0_1 = 1
+ , H_REG0_2 = 2, H_REG0_3 = 3, H_REG0_4 = 4, H_REG0_5 = 5
+ , H_REG0_6 = 6, H_REG0_7 = 7, H_REG0_8 = 8, H_REG0_9 = 9
+ , H_REG0_10 = 10, H_REG0_11 = 11, H_REG0_12 = 12, H_REG0_13 = 13
+ , H_REG0_14 = 14, H_REG0_15 = 15
+} REG0_NAME;
+
+/* Enum declaration for .  */
+typedef enum reg0_name1 {
+  H_REG01_0X1 = 1, H_REG01_0X2 = 2, H_REG01_0X3 = 3, H_REG01_0X4 = 4
+ , H_REG01_0X5 = 5, H_REG01_0X6 = 6, H_REG01_0X7 = 7, H_REG01_1 = 1
+ , H_REG01_2 = 2, H_REG01_3 = 3, H_REG01_4 = 4, H_REG01_5 = 5
+ , H_REG01_6 = 6, H_REG01_7 = 7
+} REG0_NAME1;
+
+/* Enum declaration for .  */
+typedef enum regbmem8_names {
+  H_REGBMEM8_DPP0 = 0, H_REGBMEM8_DPP1 = 1, H_REGBMEM8_DPP2 = 2, H_REGBMEM8_DPP3 = 3
+ , H_REGBMEM8_PSW = 136, H_REGBMEM8_CP = 8, H_REGBMEM8_MDL = 7, H_REGBMEM8_MDH = 6
+ , H_REGBMEM8_MDC = 135, H_REGBMEM8_SP = 9, H_REGBMEM8_CSP = 4, H_REGBMEM8_VECSEG = 137
+ , H_REGBMEM8_STKOV = 10, H_REGBMEM8_STKUN = 11, H_REGBMEM8_CPUCON1 = 12, H_REGBMEM8_CPUCON2 = 13
+ , H_REGBMEM8_ZEROS = 142, H_REGBMEM8_ONES = 143, H_REGBMEM8_SPSEG = 134, H_REGBMEM8_TFR = 214
+ , H_REGBMEM8_RL0 = 240, H_REGBMEM8_RH0 = 241, H_REGBMEM8_RL1 = 242, H_REGBMEM8_RH1 = 243
+ , H_REGBMEM8_RL2 = 244, H_REGBMEM8_RH2 = 245, H_REGBMEM8_RL3 = 246, H_REGBMEM8_RH3 = 247
+ , H_REGBMEM8_RL4 = 248, H_REGBMEM8_RH4 = 249, H_REGBMEM8_RL5 = 250, H_REGBMEM8_RH5 = 251
+ , H_REGBMEM8_RL6 = 252, H_REGBMEM8_RH6 = 253, H_REGBMEM8_RL7 = 254, H_REGBMEM8_RH7 = 255
+} REGBMEM8_NAMES;
+
+/* Enum declaration for .  */
+typedef enum memgr8_names {
+  H_MEMGR8_DPP0 = 65024, H_MEMGR8_DPP1 = 65026, H_MEMGR8_DPP2 = 65028, H_MEMGR8_DPP3 = 65030
+ , H_MEMGR8_PSW = 65296, H_MEMGR8_CP = 65040, H_MEMGR8_MDL = 65038, H_MEMGR8_MDH = 65036
+ , H_MEMGR8_MDC = 65294, H_MEMGR8_SP = 65042, H_MEMGR8_CSP = 65032, H_MEMGR8_VECSEG = 65298
+ , H_MEMGR8_STKOV = 65044, H_MEMGR8_STKUN = 65046, H_MEMGR8_CPUCON1 = 65048, H_MEMGR8_CPUCON2 = 65050
+ , H_MEMGR8_ZEROS = 65308, H_MEMGR8_ONES = 65310, H_MEMGR8_SPSEG = 65292, H_MEMGR8_TFR = 65452
+} MEMGR8_NAMES;
+
+/* Attributes.  */
+
+/* Enum declaration for machine type selection.  */
+typedef enum mach_attr {
+  MACH_BASE, MACH_XC16X, MACH_MAX
+} MACH_ATTR;
+
+/* Enum declaration for instruction set selection.  */
+typedef enum isa_attr {
+  ISA_XC16X, ISA_MAX
+} ISA_ATTR;
+
+/* Enum declaration for parallel execution pipeline selection.  */
+typedef enum pipe_attr {
+  PIPE_NONE, PIPE_OS
+} PIPE_ATTR;
+
+/* Number of architecture variants.  */
+#define MAX_ISAS  1
+#define MAX_MACHS ((int) MACH_MAX)
+
+/* Ifield support.  */
+
+/* Ifield attribute indices.  */
+
+/* Enum declaration for cgen_ifld attrs.  */
+typedef enum cgen_ifld_attr {
+  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
+ , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS
+ , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
+} CGEN_IFLD_ATTR;
+
+/* Number of non-boolean elements in cgen_ifld_attr.  */
+#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
+
+/* cgen_ifld attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RELOC)) != 0)
+
+/* Enum declaration for xc16x ifield types.  */
+typedef enum ifield_type {
+  XC16X_F_NIL, XC16X_F_ANYOF, XC16X_F_OP1, XC16X_F_OP2
+ , XC16X_F_CONDCODE, XC16X_F_ICONDCODE, XC16X_F_RCOND, XC16X_F_QCOND
+ , XC16X_F_EXTCCODE, XC16X_F_R0, XC16X_F_R1, XC16X_F_R2
+ , XC16X_F_R3, XC16X_F_R4, XC16X_F_UIMM2, XC16X_F_UIMM3
+ , XC16X_F_UIMM4, XC16X_F_UIMM7, XC16X_F_UIMM8, XC16X_F_UIMM16
+ , XC16X_F_MEMORY, XC16X_F_MEMGR8, XC16X_F_REL8, XC16X_F_RELHI8
+ , XC16X_F_REG8, XC16X_F_REGMEM8, XC16X_F_REGOFF8, XC16X_F_REGHI8
+ , XC16X_F_REGB8, XC16X_F_SEG8, XC16X_F_SEGNUM8, XC16X_F_MASK8
+ , XC16X_F_PAGENUM, XC16X_F_DATAHI8, XC16X_F_DATA8, XC16X_F_OFFSET16
+ , XC16X_F_OP_BIT1, XC16X_F_OP_BIT2, XC16X_F_OP_BIT4, XC16X_F_OP_BIT3
+ , XC16X_F_OP_2BIT, XC16X_F_OP_BITONE, XC16X_F_OP_ONEBIT, XC16X_F_OP_1BIT
+ , XC16X_F_OP_LBIT4, XC16X_F_OP_LBIT2, XC16X_F_OP_BIT8, XC16X_F_OP_BIT16
+ , XC16X_F_QBIT, XC16X_F_QLOBIT, XC16X_F_QHIBIT, XC16X_F_QLOBIT2
+ , XC16X_F_POF, XC16X_F_MAX
+} IFIELD_TYPE;
+
+#define MAX_IFLD ((int) XC16X_F_MAX)
+
+/* Hardware attribute indices.  */
+
+/* Enum declaration for cgen_hw attrs.  */
+typedef enum cgen_hw_attr {
+  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
+ , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
+} CGEN_HW_ATTR;
+
+/* Number of non-boolean elements in cgen_hw_attr.  */
+#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
+
+/* cgen_hw attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
+
+/* Enum declaration for xc16x hardware types.  */
+typedef enum cgen_hw_type {
+  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
+ , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_EXT
+ , HW_H_PSW, HW_H_GRB, HW_H_CC, HW_H_ECC
+ , HW_H_GRB8, HW_H_R8, HW_H_REGMEM8, HW_H_REGDIV8
+ , HW_H_R0, HW_H_R01, HW_H_REGBMEM8, HW_H_MEMGR8
+ , HW_H_COND, HW_H_CBIT, HW_H_SGTDIS, HW_MAX
+} CGEN_HW_TYPE;
+
+#define MAX_HW ((int) HW_MAX)
+
+/* Operand attribute indices.  */
+
+/* Enum declaration for cgen_operand attrs.  */
+typedef enum cgen_operand_attr {
+  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
+ , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
+ , CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_DOT_PREFIX, CGEN_OPERAND_POF_PREFIX
+ , CGEN_OPERAND_PAG_PREFIX, CGEN_OPERAND_SOF_PREFIX, CGEN_OPERAND_SEG_PREFIX, CGEN_OPERAND_END_BOOLS
+ , CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
+} CGEN_OPERAND_ATTR;
+
+/* Number of non-boolean elements in cgen_operand_attr.  */
+#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
+
+/* cgen_operand attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_DOT_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_DOT_PREFIX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_POF_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_POF_PREFIX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PAG_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PAG_PREFIX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SOF_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SOF_PREFIX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEG_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEG_PREFIX)) != 0)
+
+/* Enum declaration for xc16x operand types.  */
+typedef enum cgen_operand_type {
+  XC16X_OPERAND_PC, XC16X_OPERAND_SR, XC16X_OPERAND_DR, XC16X_OPERAND_DRI
+ , XC16X_OPERAND_SRB, XC16X_OPERAND_DRB, XC16X_OPERAND_SR2, XC16X_OPERAND_SRC1
+ , XC16X_OPERAND_SRC2, XC16X_OPERAND_SRDIV, XC16X_OPERAND_REGNAM, XC16X_OPERAND_UIMM2
+ , XC16X_OPERAND_UIMM3, XC16X_OPERAND_UIMM4, XC16X_OPERAND_UIMM7, XC16X_OPERAND_UIMM8
+ , XC16X_OPERAND_UIMM16, XC16X_OPERAND_UPOF16, XC16X_OPERAND_REG8, XC16X_OPERAND_REGMEM8
+ , XC16X_OPERAND_REGBMEM8, XC16X_OPERAND_REGOFF8, XC16X_OPERAND_REGHI8, XC16X_OPERAND_REGB8
+ , XC16X_OPERAND_GENREG, XC16X_OPERAND_SEG, XC16X_OPERAND_SEGHI8, XC16X_OPERAND_CADDR
+ , XC16X_OPERAND_REL, XC16X_OPERAND_RELHI, XC16X_OPERAND_CONDBIT, XC16X_OPERAND_BIT1
+ , XC16X_OPERAND_BIT2, XC16X_OPERAND_BIT4, XC16X_OPERAND_LBIT4, XC16X_OPERAND_LBIT2
+ , XC16X_OPERAND_BIT8, XC16X_OPERAND_U4, XC16X_OPERAND_BITONE, XC16X_OPERAND_BIT01
+ , XC16X_OPERAND_COND, XC16X_OPERAND_ICOND, XC16X_OPERAND_EXTCOND, XC16X_OPERAND_MEMORY
+ , XC16X_OPERAND_MEMGR8, XC16X_OPERAND_CBIT, XC16X_OPERAND_QBIT, XC16X_OPERAND_QLOBIT
+ , XC16X_OPERAND_QHIBIT, XC16X_OPERAND_MASK8, XC16X_OPERAND_MASKLO8, XC16X_OPERAND_PAGENUM
+ , XC16X_OPERAND_DATA8, XC16X_OPERAND_DATAHI8, XC16X_OPERAND_SGTDISBIT, XC16X_OPERAND_UPAG16
+ , XC16X_OPERAND_USEG8, XC16X_OPERAND_USEG16, XC16X_OPERAND_USOF16, XC16X_OPERAND_HASH
+ , XC16X_OPERAND_DOT, XC16X_OPERAND_POF, XC16X_OPERAND_PAG, XC16X_OPERAND_SOF
+ , XC16X_OPERAND_SEGM, XC16X_OPERAND_MAX
+} CGEN_OPERAND_TYPE;
+
+/* Number of operands types.  */
+#define MAX_OPERANDS 65
+
+/* Maximum number of operands referenced by any insn.  */
+#define MAX_OPERAND_INSTANCES 8
+
+/* Insn attribute indices.  */
+
+/* Enum declaration for cgen_insn attrs.  */
+typedef enum cgen_insn_attr {
+  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
+ , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
+ , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
+ , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS
+} CGEN_INSN_ATTR;
+
+/* Number of non-boolean elements in cgen_insn_attr.  */
+#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
+
+/* cgen_insn attribute accessor macros.  */
+#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
+
+/* cgen.h uses things we just defined.  */
+#include "opcode/cgen.h"
+
+extern const struct cgen_ifld xc16x_cgen_ifld_table[];
+
+/* Attributes.  */
+extern const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[];
+extern const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[];
+extern const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[];
+extern const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[];
+
+/* Hardware decls.  */
+
+extern CGEN_KEYWORD xc16x_cgen_opval_gr_names;
+extern CGEN_KEYWORD xc16x_cgen_opval_ext_names;
+extern CGEN_KEYWORD xc16x_cgen_opval_psw_names;
+extern CGEN_KEYWORD xc16x_cgen_opval_grb_names;
+extern CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names;
+extern CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names;
+extern CGEN_KEYWORD xc16x_cgen_opval_grb8_names;
+extern CGEN_KEYWORD xc16x_cgen_opval_r8_names;
+extern CGEN_KEYWORD xc16x_cgen_opval_regmem8_names;
+extern CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names;
+extern CGEN_KEYWORD xc16x_cgen_opval_reg0_name;
+extern CGEN_KEYWORD xc16x_cgen_opval_reg0_name1;
+extern CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names;
+extern CGEN_KEYWORD xc16x_cgen_opval_memgr8_names;
+
+extern const CGEN_HW_ENTRY xc16x_cgen_hw_table[];
+
+
+
+#endif /* XC16X_CPU_H */
diff --git a/opcodes/xc16x-dis.c b/opcodes/xc16x-dis.c
new file mode 100644
index 0000000..5d60879
--- /dev/null
+++ b/opcodes/xc16x-dis.c
@@ -0,0 +1,804 @@
+/* Disassembler interface for targets using CGEN. -*- C -*-
+   CGEN: Cpu tools GENerator
+
+   THIS FILE IS MACHINE GENERATED WITH CGEN.
+   - the resultant file is machine generated, cgen-dis.in isn't
+
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
+   Free Software Foundation, Inc.
+
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+   Keep that in mind.  */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "libiberty.h"
+#include "xc16x-desc.h"
+#include "xc16x-opc.h"
+#include "opintl.h"
+
+/* Default text to print if an instruction isn't recognized.  */
+#define UNKNOWN_INSN_MSG _("*unknown*")
+
+static void print_normal
+  (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
+static void print_address
+  (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
+static void print_keyword
+  (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
+static void print_insn_normal
+  (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
+static int print_insn
+  (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
+static int default_print_insn
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
+static int read_insn
+  (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
+   unsigned long *);
+
+/* -- disassembler routines inserted here.  */
+
+/* -- dis.c */
+
+#define CGEN_PRINT_NORMAL(cd, info, value, attrs, pc, length)	\
+  do								\
+    {								\
+      if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_DOT_PREFIX))	\
+        info->fprintf_func (info->stream, ".");			\
+      if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_POF_PREFIX))	\
+        info->fprintf_func (info->stream, "#pof:");		\
+      if (CGEN_BOOL_ATTR ((attrs), CGEN_OPERAND_PAG_PREFIX))	\
+        info->fprintf_func (info->stream, "#pag:");		\
+    }								\
+  while (0)
+
+/* Handle '.' prefixes as operands.  */
+
+static void
+print_pof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   void * dis_info ATTRIBUTE_UNUSED,
+	   long value ATTRIBUTE_UNUSED,
+	   unsigned int attrs ATTRIBUTE_UNUSED,
+	   bfd_vma pc ATTRIBUTE_UNUSED,
+	   int length ATTRIBUTE_UNUSED)
+{
+}
+
+/* Handle '.' prefixes as operands.  */
+
+static void
+print_pag (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   void * dis_info ATTRIBUTE_UNUSED,
+	   long value ATTRIBUTE_UNUSED,
+	   unsigned int attrs ATTRIBUTE_UNUSED,
+	   bfd_vma pc ATTRIBUTE_UNUSED,
+	   int length ATTRIBUTE_UNUSED)
+{
+}
+
+/* Handle '.' prefixes as operands.  */
+
+static void
+print_sof (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   void * dis_info,
+	   long value ATTRIBUTE_UNUSED,
+	   unsigned int attrs ATTRIBUTE_UNUSED,
+	   bfd_vma pc ATTRIBUTE_UNUSED,
+	   int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  info->fprintf_func (info->stream, "sof:");
+}
+
+/* Handle '.' prefixes as operands.  */
+
+static void
+print_seg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   void * dis_info,
+	   long value ATTRIBUTE_UNUSED,
+	   unsigned int attrs ATTRIBUTE_UNUSED,
+	   bfd_vma pc ATTRIBUTE_UNUSED,
+	   int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  info->fprintf_func (info->stream, "seg:");
+}
+
+/* Handle '#' prefixes as operands.  */
+
+static void
+print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    void * dis_info,
+	    long value ATTRIBUTE_UNUSED,
+	    unsigned int attrs ATTRIBUTE_UNUSED,
+	    bfd_vma pc ATTRIBUTE_UNUSED,
+	    int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+  info->fprintf_func (info->stream, "#");
+}
+
+/* Handle '.' prefixes as operands.  */
+
+static void
+print_dot (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   void * dis_info ATTRIBUTE_UNUSED,
+	   long value ATTRIBUTE_UNUSED,
+	   unsigned int attrs ATTRIBUTE_UNUSED,
+	   bfd_vma pc ATTRIBUTE_UNUSED,
+	   int length ATTRIBUTE_UNUSED)
+{
+}
+
+/* -- */
+
+void xc16x_cgen_print_operand
+  (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
+
+/* Main entry point for printing operands.
+   XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
+   of dis-asm.h on cgen.h.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `print_insn_normal', but keeping it
+   separate makes clear the interface between `print_insn_normal' and each of
+   the handlers.  */
+
+void
+xc16x_cgen_print_operand (CGEN_CPU_DESC cd,
+			   int opindex,
+			   void * xinfo,
+			   CGEN_FIELDS *fields,
+			   void const *attrs ATTRIBUTE_UNUSED,
+			   bfd_vma pc,
+			   int length)
+{
+  disassemble_info *info = (disassemble_info *) xinfo;
+
+  switch (opindex)
+    {
+    case XC16X_OPERAND_REGNAM :
+      print_keyword (cd, info, & xc16x_cgen_opval_psw_names, fields->f_reg8, 0);
+      break;
+    case XC16X_OPERAND_BIT01 :
+      print_normal (cd, info, fields->f_op_1bit, 0, pc, length);
+      break;
+    case XC16X_OPERAND_BIT1 :
+      print_normal (cd, info, fields->f_op_bit1, 0, pc, length);
+      break;
+    case XC16X_OPERAND_BIT2 :
+      print_normal (cd, info, fields->f_op_bit2, 0, pc, length);
+      break;
+    case XC16X_OPERAND_BIT4 :
+      print_normal (cd, info, fields->f_op_bit4, 0, pc, length);
+      break;
+    case XC16X_OPERAND_BIT8 :
+      print_normal (cd, info, fields->f_op_bit8, 0, pc, length);
+      break;
+    case XC16X_OPERAND_BITONE :
+      print_normal (cd, info, fields->f_op_onebit, 0, pc, length);
+      break;
+    case XC16X_OPERAND_CADDR :
+      print_address (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
+      break;
+    case XC16X_OPERAND_COND :
+      print_keyword (cd, info, & xc16x_cgen_opval_conditioncode_names, fields->f_condcode, 0);
+      break;
+    case XC16X_OPERAND_DATA8 :
+      print_normal (cd, info, fields->f_data8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_DATAHI8 :
+      print_normal (cd, info, fields->f_datahi8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_DOT :
+      print_dot (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
+    case XC16X_OPERAND_DR :
+      print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r1, 0);
+      break;
+    case XC16X_OPERAND_DRB :
+      print_keyword (cd, info, & xc16x_cgen_opval_grb_names, fields->f_r1, 0);
+      break;
+    case XC16X_OPERAND_DRI :
+      print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r4, 0);
+      break;
+    case XC16X_OPERAND_EXTCOND :
+      print_keyword (cd, info, & xc16x_cgen_opval_extconditioncode_names, fields->f_extccode, 0);
+      break;
+    case XC16X_OPERAND_GENREG :
+      print_keyword (cd, info, & xc16x_cgen_opval_r8_names, fields->f_regb8, 0);
+      break;
+    case XC16X_OPERAND_HASH :
+      print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
+    case XC16X_OPERAND_ICOND :
+      print_keyword (cd, info, & xc16x_cgen_opval_conditioncode_names, fields->f_icondcode, 0);
+      break;
+    case XC16X_OPERAND_LBIT2 :
+      print_normal (cd, info, fields->f_op_lbit2, 0, pc, length);
+      break;
+    case XC16X_OPERAND_LBIT4 :
+      print_normal (cd, info, fields->f_op_lbit4, 0, pc, length);
+      break;
+    case XC16X_OPERAND_MASK8 :
+      print_normal (cd, info, fields->f_mask8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_MASKLO8 :
+      print_normal (cd, info, fields->f_datahi8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_MEMGR8 :
+      print_keyword (cd, info, & xc16x_cgen_opval_memgr8_names, fields->f_memgr8, 0);
+      break;
+    case XC16X_OPERAND_MEMORY :
+      print_address (cd, info, fields->f_memory, 0, pc, length);
+      break;
+    case XC16X_OPERAND_PAG :
+      print_pag (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
+    case XC16X_OPERAND_PAGENUM :
+      print_normal (cd, info, fields->f_pagenum, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_POF :
+      print_pof (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
+    case XC16X_OPERAND_QBIT :
+      print_normal (cd, info, fields->f_qbit, 0|(1<<CGEN_OPERAND_DOT_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_QHIBIT :
+      print_normal (cd, info, fields->f_qhibit, 0|(1<<CGEN_OPERAND_DOT_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_QLOBIT :
+      print_normal (cd, info, fields->f_qlobit, 0|(1<<CGEN_OPERAND_DOT_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_REG8 :
+      print_keyword (cd, info, & xc16x_cgen_opval_r8_names, fields->f_reg8, 0);
+      break;
+    case XC16X_OPERAND_REGB8 :
+      print_keyword (cd, info, & xc16x_cgen_opval_grb8_names, fields->f_regb8, 0);
+      break;
+    case XC16X_OPERAND_REGBMEM8 :
+      print_keyword (cd, info, & xc16x_cgen_opval_regbmem8_names, fields->f_regmem8, 0);
+      break;
+    case XC16X_OPERAND_REGHI8 :
+      print_keyword (cd, info, & xc16x_cgen_opval_r8_names, fields->f_reghi8, 0);
+      break;
+    case XC16X_OPERAND_REGMEM8 :
+      print_keyword (cd, info, & xc16x_cgen_opval_regmem8_names, fields->f_regmem8, 0);
+      break;
+    case XC16X_OPERAND_REGOFF8 :
+      print_keyword (cd, info, & xc16x_cgen_opval_r8_names, fields->f_regoff8, 0);
+      break;
+    case XC16X_OPERAND_REL :
+      print_normal (cd, info, fields->f_rel8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+      break;
+    case XC16X_OPERAND_RELHI :
+      print_normal (cd, info, fields->f_relhi8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+      break;
+    case XC16X_OPERAND_SEG :
+      print_normal (cd, info, fields->f_seg8, 0, pc, length);
+      break;
+    case XC16X_OPERAND_SEGHI8 :
+      print_normal (cd, info, fields->f_segnum8, 0, pc, length);
+      break;
+    case XC16X_OPERAND_SEGM :
+      print_seg (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
+    case XC16X_OPERAND_SOF :
+      print_sof (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
+      break;
+    case XC16X_OPERAND_SR :
+      print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r2, 0);
+      break;
+    case XC16X_OPERAND_SR2 :
+      print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r0, 0);
+      break;
+    case XC16X_OPERAND_SRB :
+      print_keyword (cd, info, & xc16x_cgen_opval_grb_names, fields->f_r2, 0);
+      break;
+    case XC16X_OPERAND_SRC1 :
+      print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r1, 0);
+      break;
+    case XC16X_OPERAND_SRC2 :
+      print_keyword (cd, info, & xc16x_cgen_opval_gr_names, fields->f_r2, 0);
+      break;
+    case XC16X_OPERAND_SRDIV :
+      print_keyword (cd, info, & xc16x_cgen_opval_regdiv8_names, fields->f_reg8, 0);
+      break;
+    case XC16X_OPERAND_U4 :
+      print_keyword (cd, info, & xc16x_cgen_opval_reg0_name, fields->f_uimm4, 0);
+      break;
+    case XC16X_OPERAND_UIMM16 :
+      print_normal (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_UIMM2 :
+      print_keyword (cd, info, & xc16x_cgen_opval_ext_names, fields->f_uimm2, 0|(1<<CGEN_OPERAND_HASH_PREFIX));
+      break;
+    case XC16X_OPERAND_UIMM3 :
+      print_keyword (cd, info, & xc16x_cgen_opval_reg0_name1, fields->f_uimm3, 0|(1<<CGEN_OPERAND_HASH_PREFIX));
+      break;
+    case XC16X_OPERAND_UIMM4 :
+      print_normal (cd, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_UIMM7 :
+      print_normal (cd, info, fields->f_uimm7, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
+      break;
+    case XC16X_OPERAND_UIMM8 :
+      print_normal (cd, info, fields->f_uimm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_UPAG16 :
+      print_normal (cd, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_PAG_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_UPOF16 :
+      print_address (cd, info, fields->f_memory, 0|(1<<CGEN_OPERAND_POF_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_USEG16 :
+      print_normal (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SEG_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
+      break;
+    case XC16X_OPERAND_USEG8 :
+      print_normal (cd, info, fields->f_seg8, 0|(1<<CGEN_OPERAND_SEG_PREFIX), pc, length);
+      break;
+    case XC16X_OPERAND_USOF16 :
+      print_normal (cd, info, fields->f_offset16, 0|(1<<CGEN_OPERAND_SOF_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
+	       opindex);
+    abort ();
+  }
+}
+
+cgen_print_fn * const xc16x_cgen_print_handlers[] = 
+{
+  print_insn_normal,
+};
+
+
+void
+xc16x_cgen_init_dis (CGEN_CPU_DESC cd)
+{
+  xc16x_cgen_init_opcode_table (cd);
+  xc16x_cgen_init_ibld_table (cd);
+  cd->print_handlers = & xc16x_cgen_print_handlers[0];
+  cd->print_operand = xc16x_cgen_print_operand;
+}
+
+
+/* Default print handler.  */
+
+static void
+print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	      void *dis_info,
+	      long value,
+	      unsigned int attrs,
+	      bfd_vma pc ATTRIBUTE_UNUSED,
+	      int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_NORMAL
+  CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length);
+#endif
+
+  /* Print the operand as directed by the attributes.  */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+    ; /* nothing to do */
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+    (*info->fprintf_func) (info->stream, "%ld", value);
+  else
+    (*info->fprintf_func) (info->stream, "0x%lx", value);
+}
+
+/* Default address handler.  */
+
+static void
+print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       bfd_vma value,
+	       unsigned int attrs,
+	       bfd_vma pc ATTRIBUTE_UNUSED,
+	       int length ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+
+#ifdef CGEN_PRINT_ADDRESS
+  CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length);
+#endif
+
+  /* Print the operand as directed by the attributes.  */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
+    ; /* Nothing to do.  */
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
+    (*info->print_address_func) (value, info);
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
+    (*info->print_address_func) (value, info);
+  else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
+    (*info->fprintf_func) (info->stream, "%ld", (long) value);
+  else
+    (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
+}
+
+/* Keyword print handler.  */
+
+static void
+print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	       void *dis_info,
+	       CGEN_KEYWORD *keyword_table,
+	       long value,
+	       unsigned int attrs ATTRIBUTE_UNUSED)
+{
+  disassemble_info *info = (disassemble_info *) dis_info;
+  const CGEN_KEYWORD_ENTRY *ke;
+
+  ke = cgen_keyword_lookup_value (keyword_table, value);
+  if (ke != NULL)
+    (*info->fprintf_func) (info->stream, "%s", ke->name);
+  else
+    (*info->fprintf_func) (info->stream, "???");
+}
+
+/* Default insn printer.
+
+   DIS_INFO is defined as `void *' so the disassembler needn't know anything
+   about disassemble_info.  */
+
+static void
+print_insn_normal (CGEN_CPU_DESC cd,
+		   void *dis_info,
+		   const CGEN_INSN *insn,
+		   CGEN_FIELDS *fields,
+		   bfd_vma pc,
+		   int length)
+{
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  disassemble_info *info = (disassemble_info *) dis_info;
+  const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+  CGEN_INIT_PRINT (cd);
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+    {
+      if (CGEN_SYNTAX_MNEMONIC_P (*syn))
+	{
+	  (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
+	  continue;
+	}
+      if (CGEN_SYNTAX_CHAR_P (*syn))
+	{
+	  (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
+	  continue;
+	}
+
+      /* We have an operand.  */
+      xc16x_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
+				 fields, CGEN_INSN_ATTRS (insn), pc, length);
+    }
+}
+
+/* Subroutine of print_insn. Reads an insn into the given buffers and updates
+   the extract info.
+   Returns 0 if all is well, non-zero otherwise.  */
+
+static int
+read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	   bfd_vma pc,
+	   disassemble_info *info,
+	   bfd_byte *buf,
+	   int buflen,
+	   CGEN_EXTRACT_INFO *ex_info,
+	   unsigned long *insn_value)
+{
+  int status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, pc, info);
+      return -1;
+    }
+
+  ex_info->dis_info = info;
+  ex_info->valid = (1 << buflen) - 1;
+  ex_info->insn_bytes = buf;
+
+  *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
+  return 0;
+}
+
+/* Utility to print an insn.
+   BUF is the base part of the insn, target byte order, BUFLEN bytes long.
+   The result is the size of the insn in bytes or zero for an unknown insn
+   or -1 if an error occurs fetching data (memory_error_func will have
+   been called).  */
+
+static int
+print_insn (CGEN_CPU_DESC cd,
+	    bfd_vma pc,
+	    disassemble_info *info,
+	    bfd_byte *buf,
+	    unsigned int buflen)
+{
+  CGEN_INSN_INT insn_value;
+  const CGEN_INSN_LIST *insn_list;
+  CGEN_EXTRACT_INFO ex_info;
+  int basesize;
+
+  /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
+  basesize = cd->base_insn_bitsize < buflen * 8 ?
+                                     cd->base_insn_bitsize : buflen * 8;
+  insn_value = cgen_get_insn_value (cd, buf, basesize);
+
+
+  /* Fill in ex_info fields like read_insn would.  Don't actually call
+     read_insn, since the incoming buffer is already read (and possibly
+     modified a la m32r).  */
+  ex_info.valid = (1 << buflen) - 1;
+  ex_info.dis_info = info;
+  ex_info.insn_bytes = buf;
+
+  /* The instructions are stored in hash lists.
+     Pick the first one and keep trying until we find the right one.  */
+
+  insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
+  while (insn_list != NULL)
+    {
+      const CGEN_INSN *insn = insn_list->insn;
+      CGEN_FIELDS fields;
+      int length;
+      unsigned long insn_value_cropped;
+
+#ifdef CGEN_VALIDATE_INSN_SUPPORTED 
+      /* Not needed as insn shouldn't be in hash lists if not supported.  */
+      /* Supported by this cpu?  */
+      if (! xc16x_cgen_insn_supported (cd, insn))
+        {
+          insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+	  continue;
+        }
+#endif
+
+      /* Basic bit mask must be correct.  */
+      /* ??? May wish to allow target to defer this check until the extract
+	 handler.  */
+
+      /* Base size may exceed this instruction's size.  Extract the
+         relevant part from the buffer. */
+      if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
+	  (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+	insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 
+					   info->endian == BFD_ENDIAN_BIG);
+      else
+	insn_value_cropped = insn_value;
+
+      if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
+	  == CGEN_INSN_BASE_VALUE (insn))
+	{
+	  /* Printing is handled in two passes.  The first pass parses the
+	     machine insn and extracts the fields.  The second pass prints
+	     them.  */
+
+	  /* Make sure the entire insn is loaded into insn_value, if it
+	     can fit.  */
+	  if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
+	      (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
+	    {
+	      unsigned long full_insn_value;
+	      int rc = read_insn (cd, pc, info, buf,
+				  CGEN_INSN_BITSIZE (insn) / 8,
+				  & ex_info, & full_insn_value);
+	      if (rc != 0)
+		return rc;
+	      length = CGEN_EXTRACT_FN (cd, insn)
+		(cd, insn, &ex_info, full_insn_value, &fields, pc);
+	    }
+	  else
+	    length = CGEN_EXTRACT_FN (cd, insn)
+	      (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
+
+	  /* Length < 0 -> error.  */
+	  if (length < 0)
+	    return length;
+	  if (length > 0)
+	    {
+	      CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
+	      /* Length is in bits, result is in bytes.  */
+	      return length / 8;
+	    }
+	}
+
+      insn_list = CGEN_DIS_NEXT_INSN (insn_list);
+    }
+
+  return 0;
+}
+
+/* Default value for CGEN_PRINT_INSN.
+   The result is the size of the insn in bytes or zero for an unknown insn
+   or -1 if an error occured fetching bytes.  */
+
+#ifndef CGEN_PRINT_INSN
+#define CGEN_PRINT_INSN default_print_insn
+#endif
+
+static int
+default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
+{
+  bfd_byte buf[CGEN_MAX_INSN_SIZE];
+  int buflen;
+  int status;
+
+  /* Attempt to read the base part of the insn.  */
+  buflen = cd->base_insn_bitsize / 8;
+  status = (*info->read_memory_func) (pc, buf, buflen, info);
+
+  /* Try again with the minimum part, if min < base.  */
+  if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
+    {
+      buflen = cd->min_insn_bitsize / 8;
+      status = (*info->read_memory_func) (pc, buf, buflen, info);
+    }
+
+  if (status != 0)
+    {
+      (*info->memory_error_func) (status, pc, info);
+      return -1;
+    }
+
+  return print_insn (cd, pc, info, buf, buflen);
+}
+
+/* Main entry point.
+   Print one instruction from PC on INFO->STREAM.
+   Return the size of the instruction (in bytes).  */
+
+typedef struct cpu_desc_list
+{
+  struct cpu_desc_list *next;
+  CGEN_BITSET *isa;
+  int mach;
+  int endian;
+  CGEN_CPU_DESC cd;
+} cpu_desc_list;
+
+int
+print_insn_xc16x (bfd_vma pc, disassemble_info *info)
+{
+  static cpu_desc_list *cd_list = 0;
+  cpu_desc_list *cl = 0;
+  static CGEN_CPU_DESC cd = 0;
+  static CGEN_BITSET *prev_isa;
+  static int prev_mach;
+  static int prev_endian;
+  int length;
+  CGEN_BITSET *isa;
+  int mach;
+  int endian = (info->endian == BFD_ENDIAN_BIG
+		? CGEN_ENDIAN_BIG
+		: CGEN_ENDIAN_LITTLE);
+  enum bfd_architecture arch;
+
+  /* ??? gdb will set mach but leave the architecture as "unknown" */
+#ifndef CGEN_BFD_ARCH
+#define CGEN_BFD_ARCH bfd_arch_xc16x
+#endif
+  arch = info->arch;
+  if (arch == bfd_arch_unknown)
+    arch = CGEN_BFD_ARCH;
+   
+  /* There's no standard way to compute the machine or isa number
+     so we leave it to the target.  */
+#ifdef CGEN_COMPUTE_MACH
+  mach = CGEN_COMPUTE_MACH (info);
+#else
+  mach = info->mach;
+#endif
+
+#ifdef CGEN_COMPUTE_ISA
+  {
+    static CGEN_BITSET *permanent_isa;
+
+    if (!permanent_isa)
+      permanent_isa = cgen_bitset_create (MAX_ISAS);
+    isa = permanent_isa;
+    cgen_bitset_clear (isa);
+    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
+  }
+#else
+  isa = info->insn_sets;
+#endif
+
+  /* If we've switched cpu's, try to find a handle we've used before */
+  if (cd
+      && (cgen_bitset_compare (isa, prev_isa) != 0
+	  || mach != prev_mach
+	  || endian != prev_endian))
+    {
+      cd = 0;
+      for (cl = cd_list; cl; cl = cl->next)
+	{
+	  if (cgen_bitset_compare (cl->isa, isa) == 0 &&
+	      cl->mach == mach &&
+	      cl->endian == endian)
+	    {
+	      cd = cl->cd;
+ 	      prev_isa = cd->isas;
+	      break;
+	    }
+	}
+    } 
+
+  /* If we haven't initialized yet, initialize the opcode table.  */
+  if (! cd)
+    {
+      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
+      const char *mach_name;
+
+      if (!arch_type)
+	abort ();
+      mach_name = arch_type->printable_name;
+
+      prev_isa = cgen_bitset_copy (isa);
+      prev_mach = mach;
+      prev_endian = endian;
+      cd = xc16x_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
+				 CGEN_CPU_OPEN_BFDMACH, mach_name,
+				 CGEN_CPU_OPEN_ENDIAN, prev_endian,
+				 CGEN_CPU_OPEN_END);
+      if (!cd)
+	abort ();
+
+      /* Save this away for future reference.  */
+      cl = xmalloc (sizeof (struct cpu_desc_list));
+      cl->cd = cd;
+      cl->isa = prev_isa;
+      cl->mach = mach;
+      cl->endian = endian;
+      cl->next = cd_list;
+      cd_list = cl;
+
+      xc16x_cgen_init_dis (cd);
+    }
+
+  /* We try to have as much common code as possible.
+     But at this point some targets need to take over.  */
+  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
+     but if not possible try to move this hook elsewhere rather than
+     have two hooks.  */
+  length = CGEN_PRINT_INSN (cd, pc, info);
+  if (length > 0)
+    return length;
+  if (length < 0)
+    return -1;
+
+  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
+  return cd->default_insn_bitsize / 8;
+}
diff --git a/opcodes/xc16x-ibld.c b/opcodes/xc16x-ibld.c
new file mode 100644
index 0000000..97e6bbc
--- /dev/null
+++ b/opcodes/xc16x-ibld.c
@@ -0,0 +1,1803 @@
+/* Instruction building/extraction support for xc16x. -*- C -*-
+
+   THIS FILE IS MACHINE GENERATED WITH CGEN: Cpu tools GENerator.
+   - the resultant file is machine generated, cgen-ibld.in isn't
+
+   Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2005, 2006
+   Free Software Foundation, Inc.
+
+   This file is part of the GNU Binutils and GDB, the GNU debugger.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
+
+/* ??? Eventually more and more of this stuff can go to cpu-independent files.
+   Keep that in mind.  */
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "xc16x-desc.h"
+#include "xc16x-opc.h"
+#include "opintl.h"
+#include "safe-ctype.h"
+
+#undef  min
+#define min(a,b) ((a) < (b) ? (a) : (b))
+#undef  max
+#define max(a,b) ((a) > (b) ? (a) : (b))
+
+/* Used by the ifield rtx function.  */
+#define FLD(f) (fields->f)
+
+static const char * insert_normal
+  (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR);
+static const char * insert_insn_normal
+  (CGEN_CPU_DESC, const CGEN_INSN *,
+   CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
+static int extract_normal
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
+   unsigned int, unsigned int, unsigned int, unsigned int,
+   unsigned int, unsigned int, bfd_vma, long *);
+static int extract_insn_normal
+  (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
+   CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
+#if CGEN_INT_INSN_P
+static void put_insn_int_value
+  (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT);
+#endif
+#if ! CGEN_INT_INSN_P
+static CGEN_INLINE void insert_1
+  (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *);
+static CGEN_INLINE int fill_cache
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *,  int, int, bfd_vma);
+static CGEN_INLINE long extract_1
+  (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma);
+#endif
+
+/* Operand insertion.  */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of insert_normal.  */
+
+static CGEN_INLINE void
+insert_1 (CGEN_CPU_DESC cd,
+	  unsigned long value,
+	  int start,
+	  int length,
+	  int word_length,
+	  unsigned char *bufp)
+{
+  unsigned long x,mask;
+  int shift;
+
+  x = cgen_get_insn_value (cd, bufp, word_length);
+
+  /* Written this way to avoid undefined behaviour.  */
+  mask = (((1L << (length - 1)) - 1) << 1) | 1;
+  if (CGEN_INSN_LSB0_P)
+    shift = (start + 1) - length;
+  else
+    shift = (word_length - (start + length));
+  x = (x & ~(mask << shift)) | ((value & mask) << shift);
+
+  cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x);
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default insertion routine.
+
+   ATTRS is a mask of the boolean attributes.
+   WORD_OFFSET is the offset in bits from the start of the insn of the value.
+   WORD_LENGTH is the length of the word in bits in which the value resides.
+   START is the starting bit number in the word, architecture origin.
+   LENGTH is the length of VALUE in bits.
+   TOTAL_LENGTH is the total length of the insn in bits.
+
+   The result is an error message or NULL if success.  */
+
+/* ??? This duplicates functionality with bfd's howto table and
+   bfd_install_relocation.  */
+/* ??? This doesn't handle bfd_vma's.  Create another function when
+   necessary.  */
+
+static const char *
+insert_normal (CGEN_CPU_DESC cd,
+	       long value,
+	       unsigned int attrs,
+	       unsigned int word_offset,
+	       unsigned int start,
+	       unsigned int length,
+	       unsigned int word_length,
+	       unsigned int total_length,
+	       CGEN_INSN_BYTES_PTR buffer)
+{
+  static char errbuf[100];
+  /* Written this way to avoid undefined behaviour.  */
+  unsigned long mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+  /* If LENGTH is zero, this operand doesn't contribute to the value.  */
+  if (length == 0)
+    return NULL;
+
+  if (word_length > 32)
+    abort ();
+
+  /* For architectures with insns smaller than the base-insn-bitsize,
+     word_length may be too big.  */
+  if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+    {
+      if (word_offset == 0
+	  && word_length > total_length)
+	word_length = total_length;
+    }
+
+  /* Ensure VALUE will fit.  */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT))
+    {
+      long minval = - (1L << (length - 1));
+      unsigned long maxval = mask;
+      
+      if ((value > 0 && (unsigned long) value > maxval)
+	  || value < minval)
+	{
+	  /* xgettext:c-format */
+	  sprintf (errbuf,
+		   _("operand out of range (%ld not between %ld and %lu)"),
+		   value, minval, maxval);
+	  return errbuf;
+	}
+    }
+  else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED))
+    {
+      unsigned long maxval = mask;
+      
+      if ((unsigned long) value > maxval)
+	{
+	  /* xgettext:c-format */
+	  sprintf (errbuf,
+		   _("operand out of range (%lu not between 0 and %lu)"),
+		   value, maxval);
+	  return errbuf;
+	}
+    }
+  else
+    {
+      if (! cgen_signed_overflow_ok_p (cd))
+	{
+	  long minval = - (1L << (length - 1));
+	  long maxval =   (1L << (length - 1)) - 1;
+	  
+	  if (value < minval || value > maxval)
+	    {
+	      sprintf
+		/* xgettext:c-format */
+		(errbuf, _("operand out of range (%ld not between %ld and %ld)"),
+		 value, minval, maxval);
+	      return errbuf;
+	    }
+	}
+    }
+
+#if CGEN_INT_INSN_P
+
+  {
+    int shift;
+
+    if (CGEN_INSN_LSB0_P)
+      shift = (word_offset + start + 1) - length;
+    else
+      shift = total_length - (word_offset + start + length);
+    *buffer = (*buffer & ~(mask << shift)) | ((value & mask) << shift);
+  }
+
+#else /* ! CGEN_INT_INSN_P */
+
+  {
+    unsigned char *bufp = (unsigned char *) buffer + word_offset / 8;
+
+    insert_1 (cd, value, start, length, word_length, bufp);
+  }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  return NULL;
+}
+
+/* Default insn builder (insert handler).
+   The instruction is recorded in CGEN_INT_INSN_P byte order (meaning
+   that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is
+   recorded in host byte order, otherwise BUFFER is an array of bytes
+   and the value is recorded in target byte order).
+   The result is an error message or NULL if success.  */
+
+static const char *
+insert_insn_normal (CGEN_CPU_DESC cd,
+		    const CGEN_INSN * insn,
+		    CGEN_FIELDS * fields,
+		    CGEN_INSN_BYTES_PTR buffer,
+		    bfd_vma pc)
+{
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  unsigned long value;
+  const CGEN_SYNTAX_CHAR_TYPE * syn;
+
+  CGEN_INIT_INSERT (cd);
+  value = CGEN_INSN_BASE_VALUE (insn);
+
+  /* If we're recording insns as numbers (rather than a string of bytes),
+     target byte order handling is deferred until later.  */
+
+#if CGEN_INT_INSN_P
+
+  put_insn_int_value (cd, buffer, cd->base_insn_bitsize,
+		      CGEN_FIELDS_BITSIZE (fields), value);
+
+#else
+
+  cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize,
+					(unsigned) CGEN_FIELDS_BITSIZE (fields)),
+		       value);
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  /* ??? It would be better to scan the format's fields.
+     Still need to be able to insert a value based on the operand though;
+     e.g. storing a branch displacement that got resolved later.
+     Needs more thought first.  */
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); * syn; ++ syn)
+    {
+      const char *errmsg;
+
+      if (CGEN_SYNTAX_CHAR_P (* syn))
+	continue;
+
+      errmsg = (* cd->insert_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+				       fields, buffer, pc);
+      if (errmsg)
+	return errmsg;
+    }
+
+  return NULL;
+}
+
+#if CGEN_INT_INSN_P
+/* Cover function to store an insn value into an integral insn.  Must go here
+   because it needs <prefix>-desc.h for CGEN_INT_INSN_P.  */
+
+static void
+put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+		    CGEN_INSN_BYTES_PTR buf,
+		    int length,
+		    int insn_length,
+		    CGEN_INSN_INT value)
+{
+  /* For architectures with insns smaller than the base-insn-bitsize,
+     length may be too big.  */
+  if (length > insn_length)
+    *buf = value;
+  else
+    {
+      int shift = insn_length - length;
+      /* Written this way to avoid undefined behaviour.  */
+      CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+      *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift);
+    }
+}
+#endif
+
+/* Operand extraction.  */
+
+#if ! CGEN_INT_INSN_P
+
+/* Subroutine of extract_normal.
+   Ensure sufficient bytes are cached in EX_INFO.
+   OFFSET is the offset in bytes from the start of the insn of the value.
+   BYTES is the length of the needed value.
+   Returns 1 for success, 0 for failure.  */
+
+static CGEN_INLINE int
+fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+	    CGEN_EXTRACT_INFO *ex_info,
+	    int offset,
+	    int bytes,
+	    bfd_vma pc)
+{
+  /* It's doubtful that the middle part has already been fetched so
+     we don't optimize that case.  kiss.  */
+  unsigned int mask;
+  disassemble_info *info = (disassemble_info *) ex_info->dis_info;
+
+  /* First do a quick check.  */
+  mask = (1 << bytes) - 1;
+  if (((ex_info->valid >> offset) & mask) == mask)
+    return 1;
+
+  /* Search for the first byte we need to read.  */
+  for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
+    if (! (mask & ex_info->valid))
+      break;
+
+  if (bytes)
+    {
+      int status;
+
+      pc += offset;
+      status = (*info->read_memory_func)
+	(pc, ex_info->insn_bytes + offset, bytes, info);
+
+      if (status != 0)
+	{
+	  (*info->memory_error_func) (status, pc, info);
+	  return 0;
+	}
+
+      ex_info->valid |= ((1 << bytes) - 1) << offset;
+    }
+
+  return 1;
+}
+
+/* Subroutine of extract_normal.  */
+
+static CGEN_INLINE long
+extract_1 (CGEN_CPU_DESC cd,
+	   CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+	   int start,
+	   int length,
+	   int word_length,
+	   unsigned char *bufp,
+	   bfd_vma pc ATTRIBUTE_UNUSED)
+{
+  unsigned long x;
+  int shift;
+
+  x = cgen_get_insn_value (cd, bufp, word_length);
+
+  if (CGEN_INSN_LSB0_P)
+    shift = (start + 1) - length;
+  else
+    shift = (word_length - (start + length));
+  return x >> shift;
+}
+
+#endif /* ! CGEN_INT_INSN_P */
+
+/* Default extraction routine.
+
+   INSN_VALUE is the first base_insn_bitsize bits of the insn in host order,
+   or sometimes less for cases like the m32r where the base insn size is 32
+   but some insns are 16 bits.
+   ATTRS is a mask of the boolean attributes.  We only need `SIGNED',
+   but for generality we take a bitmask of all of them.
+   WORD_OFFSET is the offset in bits from the start of the insn of the value.
+   WORD_LENGTH is the length of the word in bits in which the value resides.
+   START is the starting bit number in the word, architecture origin.
+   LENGTH is the length of VALUE in bits.
+   TOTAL_LENGTH is the total length of the insn in bits.
+
+   Returns 1 for success, 0 for failure.  */
+
+/* ??? The return code isn't properly used.  wip.  */
+
+/* ??? This doesn't handle bfd_vma's.  Create another function when
+   necessary.  */
+
+static int
+extract_normal (CGEN_CPU_DESC cd,
+#if ! CGEN_INT_INSN_P
+		CGEN_EXTRACT_INFO *ex_info,
+#else
+		CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED,
+#endif
+		CGEN_INSN_INT insn_value,
+		unsigned int attrs,
+		unsigned int word_offset,
+		unsigned int start,
+		unsigned int length,
+		unsigned int word_length,
+		unsigned int total_length,
+#if ! CGEN_INT_INSN_P
+		bfd_vma pc,
+#else
+		bfd_vma pc ATTRIBUTE_UNUSED,
+#endif
+		long *valuep)
+{
+  long value, mask;
+
+  /* If LENGTH is zero, this operand doesn't contribute to the value
+     so give it a standard value of zero.  */
+  if (length == 0)
+    {
+      *valuep = 0;
+      return 1;
+    }
+
+  if (word_length > 32)
+    abort ();
+
+  /* For architectures with insns smaller than the insn-base-bitsize,
+     word_length may be too big.  */
+  if (cd->min_insn_bitsize < cd->base_insn_bitsize)
+    {
+      if (word_offset + word_length > total_length)
+	word_length = total_length - word_offset;
+    }
+
+  /* Does the value reside in INSN_VALUE, and at the right alignment?  */
+
+  if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length))
+    {
+      if (CGEN_INSN_LSB0_P)
+	value = insn_value >> ((word_offset + start + 1) - length);
+      else
+	value = insn_value >> (total_length - ( word_offset + start + length));
+    }
+
+#if ! CGEN_INT_INSN_P
+
+  else
+    {
+      unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
+
+      if (word_length > 32)
+	abort ();
+
+      if (fill_cache (cd, ex_info, word_offset / 8, word_length / 8, pc) == 0)
+	return 0;
+
+      value = extract_1 (cd, ex_info, start, length, word_length, bufp, pc);
+    }
+
+#endif /* ! CGEN_INT_INSN_P */
+
+  /* Written this way to avoid undefined behaviour.  */
+  mask = (((1L << (length - 1)) - 1) << 1) | 1;
+
+  value &= mask;
+  /* sign extend? */
+  if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)
+      && (value & (1L << (length - 1))))
+    value |= ~mask;
+
+  *valuep = value;
+
+  return 1;
+}
+
+/* Default insn extractor.
+
+   INSN_VALUE is the first base_insn_bitsize bits, translated to host order.
+   The extracted fields are stored in FIELDS.
+   EX_INFO is used to handle reading variable length insns.
+   Return the length of the insn in bits, or 0 if no match,
+   or -1 if an error occurs fetching data (memory_error_func will have
+   been called).  */
+
+static int
+extract_insn_normal (CGEN_CPU_DESC cd,
+		     const CGEN_INSN *insn,
+		     CGEN_EXTRACT_INFO *ex_info,
+		     CGEN_INSN_INT insn_value,
+		     CGEN_FIELDS *fields,
+		     bfd_vma pc)
+{
+  const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
+  const CGEN_SYNTAX_CHAR_TYPE *syn;
+
+  CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
+
+  CGEN_INIT_EXTRACT (cd);
+
+  for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
+    {
+      int length;
+
+      if (CGEN_SYNTAX_CHAR_P (*syn))
+	continue;
+
+      length = (* cd->extract_operand) (cd, CGEN_SYNTAX_FIELD (*syn),
+					ex_info, insn_value, fields, pc);
+      if (length <= 0)
+	return length;
+    }
+
+  /* We recognized and successfully extracted this insn.  */
+  return CGEN_INSN_BITSIZE (insn);
+}
+
+/* Machine generated code added here.  */
+
+const char * xc16x_cgen_insert_operand
+  (CGEN_CPU_DESC, int, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma);
+
+/* Main entry point for operand insertion.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `parse_insn_normal', but keeping it
+   separate makes clear the interface between `parse_insn_normal' and each of
+   the handlers.  It's also needed by GAS to insert operands that couldn't be
+   resolved during parsing.  */
+
+const char *
+xc16x_cgen_insert_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     CGEN_INSN_BYTES_PTR buffer,
+			     bfd_vma pc ATTRIBUTE_UNUSED)
+{
+  const char * errmsg = NULL;
+  unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+  switch (opindex)
+    {
+    case XC16X_OPERAND_REGNAM :
+      errmsg = insert_normal (cd, fields->f_reg8, 0, 0, 15, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_BIT01 :
+      errmsg = insert_normal (cd, fields->f_op_1bit, 0, 0, 8, 1, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_BIT1 :
+      errmsg = insert_normal (cd, fields->f_op_bit1, 0, 0, 11, 1, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_BIT2 :
+      errmsg = insert_normal (cd, fields->f_op_bit2, 0, 0, 11, 2, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_BIT4 :
+      errmsg = insert_normal (cd, fields->f_op_bit4, 0, 0, 11, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_BIT8 :
+      errmsg = insert_normal (cd, fields->f_op_bit8, 0, 0, 31, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_BITONE :
+      errmsg = insert_normal (cd, fields->f_op_onebit, 0, 0, 9, 1, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_CADDR :
+      errmsg = insert_normal (cd, fields->f_offset16, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 31, 16, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_COND :
+      errmsg = insert_normal (cd, fields->f_condcode, 0, 0, 7, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_DATA8 :
+      errmsg = insert_normal (cd, fields->f_data8, 0, 0, 23, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_DATAHI8 :
+      errmsg = insert_normal (cd, fields->f_datahi8, 0, 0, 31, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_DOT :
+      break;
+    case XC16X_OPERAND_DR :
+      errmsg = insert_normal (cd, fields->f_r1, 0, 0, 15, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_DRB :
+      errmsg = insert_normal (cd, fields->f_r1, 0, 0, 15, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_DRI :
+      errmsg = insert_normal (cd, fields->f_r4, 0, 0, 11, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_EXTCOND :
+      errmsg = insert_normal (cd, fields->f_extccode, 0, 0, 15, 5, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_GENREG :
+      errmsg = insert_normal (cd, fields->f_regb8, 0, 0, 15, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_HASH :
+      break;
+    case XC16X_OPERAND_ICOND :
+      errmsg = insert_normal (cd, fields->f_icondcode, 0, 0, 15, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_LBIT2 :
+      errmsg = insert_normal (cd, fields->f_op_lbit2, 0, 0, 15, 2, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_LBIT4 :
+      errmsg = insert_normal (cd, fields->f_op_lbit4, 0, 0, 15, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_MASK8 :
+      errmsg = insert_normal (cd, fields->f_mask8, 0, 0, 23, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_MASKLO8 :
+      errmsg = insert_normal (cd, fields->f_datahi8, 0, 0, 31, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_MEMGR8 :
+      errmsg = insert_normal (cd, fields->f_memgr8, 0, 0, 31, 16, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_MEMORY :
+      errmsg = insert_normal (cd, fields->f_memory, 0, 0, 31, 16, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_PAG :
+      break;
+    case XC16X_OPERAND_PAGENUM :
+      errmsg = insert_normal (cd, fields->f_pagenum, 0, 0, 25, 10, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_POF :
+      break;
+    case XC16X_OPERAND_QBIT :
+      errmsg = insert_normal (cd, fields->f_qbit, 0, 0, 7, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_QHIBIT :
+      errmsg = insert_normal (cd, fields->f_qhibit, 0, 0, 27, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_QLOBIT :
+      errmsg = insert_normal (cd, fields->f_qlobit, 0, 0, 31, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_REG8 :
+      errmsg = insert_normal (cd, fields->f_reg8, 0, 0, 15, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_REGB8 :
+      errmsg = insert_normal (cd, fields->f_regb8, 0, 0, 15, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_REGBMEM8 :
+      errmsg = insert_normal (cd, fields->f_regmem8, 0, 0, 15, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_REGHI8 :
+      errmsg = insert_normal (cd, fields->f_reghi8, 0, 0, 23, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_REGMEM8 :
+      errmsg = insert_normal (cd, fields->f_regmem8, 0, 0, 15, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_REGOFF8 :
+      errmsg = insert_normal (cd, fields->f_regoff8, 0, 0, 15, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_REL :
+      errmsg = insert_normal (cd, fields->f_rel8, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_RELHI :
+      errmsg = insert_normal (cd, fields->f_relhi8, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 23, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_SEG :
+      errmsg = insert_normal (cd, fields->f_seg8, 0, 0, 15, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_SEGHI8 :
+      errmsg = insert_normal (cd, fields->f_segnum8, 0, 0, 23, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_SEGM :
+      break;
+    case XC16X_OPERAND_SOF :
+      break;
+    case XC16X_OPERAND_SR :
+      errmsg = insert_normal (cd, fields->f_r2, 0, 0, 11, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_SR2 :
+      errmsg = insert_normal (cd, fields->f_r0, 0, 0, 9, 2, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_SRB :
+      errmsg = insert_normal (cd, fields->f_r2, 0, 0, 11, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_SRC1 :
+      errmsg = insert_normal (cd, fields->f_r1, 0, 0, 15, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_SRC2 :
+      errmsg = insert_normal (cd, fields->f_r2, 0, 0, 11, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_SRDIV :
+      errmsg = insert_normal (cd, fields->f_reg8, 0, 0, 15, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_U4 :
+      errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 15, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_UIMM16 :
+      errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 31, 16, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_UIMM2 :
+      errmsg = insert_normal (cd, fields->f_uimm2, 0, 0, 13, 2, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_UIMM3 :
+      errmsg = insert_normal (cd, fields->f_uimm3, 0, 0, 10, 3, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_UIMM4 :
+      errmsg = insert_normal (cd, fields->f_uimm4, 0, 0, 15, 4, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_UIMM7 :
+      errmsg = insert_normal (cd, fields->f_uimm7, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 7, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_UIMM8 :
+      errmsg = insert_normal (cd, fields->f_uimm8, 0, 0, 23, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_UPAG16 :
+      errmsg = insert_normal (cd, fields->f_uimm16, 0, 0, 31, 16, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_UPOF16 :
+      errmsg = insert_normal (cd, fields->f_memory, 0, 0, 31, 16, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_USEG16 :
+      errmsg = insert_normal (cd, fields->f_offset16, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 31, 16, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_USEG8 :
+      errmsg = insert_normal (cd, fields->f_seg8, 0, 0, 15, 8, 32, total_length, buffer);
+      break;
+    case XC16X_OPERAND_USOF16 :
+      errmsg = insert_normal (cd, fields->f_offset16, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 31, 16, 32, total_length, buffer);
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while building insn.\n"),
+	       opindex);
+      abort ();
+  }
+
+  return errmsg;
+}
+
+int xc16x_cgen_extract_operand
+  (CGEN_CPU_DESC, int, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma);
+
+/* Main entry point for operand extraction.
+   The result is <= 0 for error, >0 for success.
+   ??? Actual values aren't well defined right now.
+
+   This function is basically just a big switch statement.  Earlier versions
+   used tables to look up the function to use, but
+   - if the table contains both assembler and disassembler functions then
+     the disassembler contains much of the assembler and vice-versa,
+   - there's a lot of inlining possibilities as things grow,
+   - using a switch statement avoids the function call overhead.
+
+   This function could be moved into `print_insn_normal', but keeping it
+   separate makes clear the interface between `print_insn_normal' and each of
+   the handlers.  */
+
+int
+xc16x_cgen_extract_operand (CGEN_CPU_DESC cd,
+			     int opindex,
+			     CGEN_EXTRACT_INFO *ex_info,
+			     CGEN_INSN_INT insn_value,
+			     CGEN_FIELDS * fields,
+			     bfd_vma pc)
+{
+  /* Assume success (for those operands that are nops).  */
+  int length = 1;
+  unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
+
+  switch (opindex)
+    {
+    case XC16X_OPERAND_REGNAM :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_reg8);
+      break;
+    case XC16X_OPERAND_BIT01 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 8, 1, 32, total_length, pc, & fields->f_op_1bit);
+      break;
+    case XC16X_OPERAND_BIT1 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 1, 32, total_length, pc, & fields->f_op_bit1);
+      break;
+    case XC16X_OPERAND_BIT2 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 2, 32, total_length, pc, & fields->f_op_bit2);
+      break;
+    case XC16X_OPERAND_BIT4 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_op_bit4);
+      break;
+    case XC16X_OPERAND_BIT8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 8, 32, total_length, pc, & fields->f_op_bit8);
+      break;
+    case XC16X_OPERAND_BITONE :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 1, 32, total_length, pc, & fields->f_op_onebit);
+      break;
+    case XC16X_OPERAND_CADDR :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 31, 16, 32, total_length, pc, & fields->f_offset16);
+      break;
+    case XC16X_OPERAND_COND :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 4, 32, total_length, pc, & fields->f_condcode);
+      break;
+    case XC16X_OPERAND_DATA8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_data8);
+      break;
+    case XC16X_OPERAND_DATAHI8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 8, 32, total_length, pc, & fields->f_datahi8);
+      break;
+    case XC16X_OPERAND_DOT :
+      break;
+    case XC16X_OPERAND_DR :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_r1);
+      break;
+    case XC16X_OPERAND_DRB :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_r1);
+      break;
+    case XC16X_OPERAND_DRI :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_r4);
+      break;
+    case XC16X_OPERAND_EXTCOND :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 5, 32, total_length, pc, & fields->f_extccode);
+      break;
+    case XC16X_OPERAND_GENREG :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regb8);
+      break;
+    case XC16X_OPERAND_HASH :
+      break;
+    case XC16X_OPERAND_ICOND :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_icondcode);
+      break;
+    case XC16X_OPERAND_LBIT2 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 2, 32, total_length, pc, & fields->f_op_lbit2);
+      break;
+    case XC16X_OPERAND_LBIT4 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_op_lbit4);
+      break;
+    case XC16X_OPERAND_MASK8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_mask8);
+      break;
+    case XC16X_OPERAND_MASKLO8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 8, 32, total_length, pc, & fields->f_datahi8);
+      break;
+    case XC16X_OPERAND_MEMGR8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_memgr8);
+      break;
+    case XC16X_OPERAND_MEMORY :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_memory);
+      break;
+    case XC16X_OPERAND_PAG :
+      break;
+    case XC16X_OPERAND_PAGENUM :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 10, 32, total_length, pc, & fields->f_pagenum);
+      break;
+    case XC16X_OPERAND_POF :
+      break;
+    case XC16X_OPERAND_QBIT :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 7, 4, 32, total_length, pc, & fields->f_qbit);
+      break;
+    case XC16X_OPERAND_QHIBIT :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 27, 4, 32, total_length, pc, & fields->f_qhibit);
+      break;
+    case XC16X_OPERAND_QLOBIT :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 4, 32, total_length, pc, & fields->f_qlobit);
+      break;
+    case XC16X_OPERAND_REG8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_reg8);
+      break;
+    case XC16X_OPERAND_REGB8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regb8);
+      break;
+    case XC16X_OPERAND_REGBMEM8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regmem8);
+      break;
+    case XC16X_OPERAND_REGHI8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_reghi8);
+      break;
+    case XC16X_OPERAND_REGMEM8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regmem8);
+      break;
+    case XC16X_OPERAND_REGOFF8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_regoff8);
+      break;
+    case XC16X_OPERAND_REL :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 8, 32, total_length, pc, & fields->f_rel8);
+      break;
+    case XC16X_OPERAND_RELHI :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 23, 8, 32, total_length, pc, & fields->f_relhi8);
+      break;
+    case XC16X_OPERAND_SEG :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_seg8);
+      break;
+    case XC16X_OPERAND_SEGHI8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_segnum8);
+      break;
+    case XC16X_OPERAND_SEGM :
+      break;
+    case XC16X_OPERAND_SOF :
+      break;
+    case XC16X_OPERAND_SR :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_r2);
+      break;
+    case XC16X_OPERAND_SR2 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 9, 2, 32, total_length, pc, & fields->f_r0);
+      break;
+    case XC16X_OPERAND_SRB :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_r2);
+      break;
+    case XC16X_OPERAND_SRC1 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_r1);
+      break;
+    case XC16X_OPERAND_SRC2 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 11, 4, 32, total_length, pc, & fields->f_r2);
+      break;
+    case XC16X_OPERAND_SRDIV :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_reg8);
+      break;
+    case XC16X_OPERAND_U4 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_uimm4);
+      break;
+    case XC16X_OPERAND_UIMM16 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_uimm16);
+      break;
+    case XC16X_OPERAND_UIMM2 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 13, 2, 32, total_length, pc, & fields->f_uimm2);
+      break;
+    case XC16X_OPERAND_UIMM3 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 10, 3, 32, total_length, pc, & fields->f_uimm3);
+      break;
+    case XC16X_OPERAND_UIMM4 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 4, 32, total_length, pc, & fields->f_uimm4);
+      break;
+    case XC16X_OPERAND_UIMM7 :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 7, 32, total_length, pc, & fields->f_uimm7);
+      break;
+    case XC16X_OPERAND_UIMM8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 23, 8, 32, total_length, pc, & fields->f_uimm8);
+      break;
+    case XC16X_OPERAND_UPAG16 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_uimm16);
+      break;
+    case XC16X_OPERAND_UPOF16 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 31, 16, 32, total_length, pc, & fields->f_memory);
+      break;
+    case XC16X_OPERAND_USEG16 :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 31, 16, 32, total_length, pc, & fields->f_offset16);
+      break;
+    case XC16X_OPERAND_USEG8 :
+      length = extract_normal (cd, ex_info, insn_value, 0, 0, 15, 8, 32, total_length, pc, & fields->f_seg8);
+      break;
+    case XC16X_OPERAND_USOF16 :
+      length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_ABS_ADDR), 0, 31, 16, 32, total_length, pc, & fields->f_offset16);
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
+	       opindex);
+      abort ();
+    }
+
+  return length;
+}
+
+cgen_insert_fn * const xc16x_cgen_insert_handlers[] = 
+{
+  insert_insn_normal,
+};
+
+cgen_extract_fn * const xc16x_cgen_extract_handlers[] = 
+{
+  extract_insn_normal,
+};
+
+int xc16x_cgen_get_int_operand     (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+bfd_vma xc16x_cgen_get_vma_operand (CGEN_CPU_DESC, int, const CGEN_FIELDS *);
+
+/* Getting values from cgen_fields is handled by a collection of functions.
+   They are distinguished by the type of the VALUE argument they return.
+   TODO: floating point, inlining support, remove cases where result type
+   not appropriate.  */
+
+int
+xc16x_cgen_get_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
+{
+  int value;
+
+  switch (opindex)
+    {
+    case XC16X_OPERAND_REGNAM :
+      value = fields->f_reg8;
+      break;
+    case XC16X_OPERAND_BIT01 :
+      value = fields->f_op_1bit;
+      break;
+    case XC16X_OPERAND_BIT1 :
+      value = fields->f_op_bit1;
+      break;
+    case XC16X_OPERAND_BIT2 :
+      value = fields->f_op_bit2;
+      break;
+    case XC16X_OPERAND_BIT4 :
+      value = fields->f_op_bit4;
+      break;
+    case XC16X_OPERAND_BIT8 :
+      value = fields->f_op_bit8;
+      break;
+    case XC16X_OPERAND_BITONE :
+      value = fields->f_op_onebit;
+      break;
+    case XC16X_OPERAND_CADDR :
+      value = fields->f_offset16;
+      break;
+    case XC16X_OPERAND_COND :
+      value = fields->f_condcode;
+      break;
+    case XC16X_OPERAND_DATA8 :
+      value = fields->f_data8;
+      break;
+    case XC16X_OPERAND_DATAHI8 :
+      value = fields->f_datahi8;
+      break;
+    case XC16X_OPERAND_DOT :
+      value = 0;
+      break;
+    case XC16X_OPERAND_DR :
+      value = fields->f_r1;
+      break;
+    case XC16X_OPERAND_DRB :
+      value = fields->f_r1;
+      break;
+    case XC16X_OPERAND_DRI :
+      value = fields->f_r4;
+      break;
+    case XC16X_OPERAND_EXTCOND :
+      value = fields->f_extccode;
+      break;
+    case XC16X_OPERAND_GENREG :
+      value = fields->f_regb8;
+      break;
+    case XC16X_OPERAND_HASH :
+      value = 0;
+      break;
+    case XC16X_OPERAND_ICOND :
+      value = fields->f_icondcode;
+      break;
+    case XC16X_OPERAND_LBIT2 :
+      value = fields->f_op_lbit2;
+      break;
+    case XC16X_OPERAND_LBIT4 :
+      value = fields->f_op_lbit4;
+      break;
+    case XC16X_OPERAND_MASK8 :
+      value = fields->f_mask8;
+      break;
+    case XC16X_OPERAND_MASKLO8 :
+      value = fields->f_datahi8;
+      break;
+    case XC16X_OPERAND_MEMGR8 :
+      value = fields->f_memgr8;
+      break;
+    case XC16X_OPERAND_MEMORY :
+      value = fields->f_memory;
+      break;
+    case XC16X_OPERAND_PAG :
+      value = 0;
+      break;
+    case XC16X_OPERAND_PAGENUM :
+      value = fields->f_pagenum;
+      break;
+    case XC16X_OPERAND_POF :
+      value = 0;
+      break;
+    case XC16X_OPERAND_QBIT :
+      value = fields->f_qbit;
+      break;
+    case XC16X_OPERAND_QHIBIT :
+      value = fields->f_qhibit;
+      break;
+    case XC16X_OPERAND_QLOBIT :
+      value = fields->f_qlobit;
+      break;
+    case XC16X_OPERAND_REG8 :
+      value = fields->f_reg8;
+      break;
+    case XC16X_OPERAND_REGB8 :
+      value = fields->f_regb8;
+      break;
+    case XC16X_OPERAND_REGBMEM8 :
+      value = fields->f_regmem8;
+      break;
+    case XC16X_OPERAND_REGHI8 :
+      value = fields->f_reghi8;
+      break;
+    case XC16X_OPERAND_REGMEM8 :
+      value = fields->f_regmem8;
+      break;
+    case XC16X_OPERAND_REGOFF8 :
+      value = fields->f_regoff8;
+      break;
+    case XC16X_OPERAND_REL :
+      value = fields->f_rel8;
+      break;
+    case XC16X_OPERAND_RELHI :
+      value = fields->f_relhi8;
+      break;
+    case XC16X_OPERAND_SEG :
+      value = fields->f_seg8;
+      break;
+    case XC16X_OPERAND_SEGHI8 :
+      value = fields->f_segnum8;
+      break;
+    case XC16X_OPERAND_SEGM :
+      value = 0;
+      break;
+    case XC16X_OPERAND_SOF :
+      value = 0;
+      break;
+    case XC16X_OPERAND_SR :
+      value = fields->f_r2;
+      break;
+    case XC16X_OPERAND_SR2 :
+      value = fields->f_r0;
+      break;
+    case XC16X_OPERAND_SRB :
+      value = fields->f_r2;
+      break;
+    case XC16X_OPERAND_SRC1 :
+      value = fields->f_r1;
+      break;
+    case XC16X_OPERAND_SRC2 :
+      value = fields->f_r2;
+      break;
+    case XC16X_OPERAND_SRDIV :
+      value = fields->f_reg8;
+      break;
+    case XC16X_OPERAND_U4 :
+      value = fields->f_uimm4;
+      break;
+    case XC16X_OPERAND_UIMM16 :
+      value = fields->f_uimm16;
+      break;
+    case XC16X_OPERAND_UIMM2 :
+      value = fields->f_uimm2;
+      break;
+    case XC16X_OPERAND_UIMM3 :
+      value = fields->f_uimm3;
+      break;
+    case XC16X_OPERAND_UIMM4 :
+      value = fields->f_uimm4;
+      break;
+    case XC16X_OPERAND_UIMM7 :
+      value = fields->f_uimm7;
+      break;
+    case XC16X_OPERAND_UIMM8 :
+      value = fields->f_uimm8;
+      break;
+    case XC16X_OPERAND_UPAG16 :
+      value = fields->f_uimm16;
+      break;
+    case XC16X_OPERAND_UPOF16 :
+      value = fields->f_memory;
+      break;
+    case XC16X_OPERAND_USEG16 :
+      value = fields->f_offset16;
+      break;
+    case XC16X_OPERAND_USEG8 :
+      value = fields->f_seg8;
+      break;
+    case XC16X_OPERAND_USOF16 :
+      value = fields->f_offset16;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
+		       opindex);
+      abort ();
+  }
+
+  return value;
+}
+
+bfd_vma
+xc16x_cgen_get_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     const CGEN_FIELDS * fields)
+{
+  bfd_vma value;
+
+  switch (opindex)
+    {
+    case XC16X_OPERAND_REGNAM :
+      value = fields->f_reg8;
+      break;
+    case XC16X_OPERAND_BIT01 :
+      value = fields->f_op_1bit;
+      break;
+    case XC16X_OPERAND_BIT1 :
+      value = fields->f_op_bit1;
+      break;
+    case XC16X_OPERAND_BIT2 :
+      value = fields->f_op_bit2;
+      break;
+    case XC16X_OPERAND_BIT4 :
+      value = fields->f_op_bit4;
+      break;
+    case XC16X_OPERAND_BIT8 :
+      value = fields->f_op_bit8;
+      break;
+    case XC16X_OPERAND_BITONE :
+      value = fields->f_op_onebit;
+      break;
+    case XC16X_OPERAND_CADDR :
+      value = fields->f_offset16;
+      break;
+    case XC16X_OPERAND_COND :
+      value = fields->f_condcode;
+      break;
+    case XC16X_OPERAND_DATA8 :
+      value = fields->f_data8;
+      break;
+    case XC16X_OPERAND_DATAHI8 :
+      value = fields->f_datahi8;
+      break;
+    case XC16X_OPERAND_DOT :
+      value = 0;
+      break;
+    case XC16X_OPERAND_DR :
+      value = fields->f_r1;
+      break;
+    case XC16X_OPERAND_DRB :
+      value = fields->f_r1;
+      break;
+    case XC16X_OPERAND_DRI :
+      value = fields->f_r4;
+      break;
+    case XC16X_OPERAND_EXTCOND :
+      value = fields->f_extccode;
+      break;
+    case XC16X_OPERAND_GENREG :
+      value = fields->f_regb8;
+      break;
+    case XC16X_OPERAND_HASH :
+      value = 0;
+      break;
+    case XC16X_OPERAND_ICOND :
+      value = fields->f_icondcode;
+      break;
+    case XC16X_OPERAND_LBIT2 :
+      value = fields->f_op_lbit2;
+      break;
+    case XC16X_OPERAND_LBIT4 :
+      value = fields->f_op_lbit4;
+      break;
+    case XC16X_OPERAND_MASK8 :
+      value = fields->f_mask8;
+      break;
+    case XC16X_OPERAND_MASKLO8 :
+      value = fields->f_datahi8;
+      break;
+    case XC16X_OPERAND_MEMGR8 :
+      value = fields->f_memgr8;
+      break;
+    case XC16X_OPERAND_MEMORY :
+      value = fields->f_memory;
+      break;
+    case XC16X_OPERAND_PAG :
+      value = 0;
+      break;
+    case XC16X_OPERAND_PAGENUM :
+      value = fields->f_pagenum;
+      break;
+    case XC16X_OPERAND_POF :
+      value = 0;
+      break;
+    case XC16X_OPERAND_QBIT :
+      value = fields->f_qbit;
+      break;
+    case XC16X_OPERAND_QHIBIT :
+      value = fields->f_qhibit;
+      break;
+    case XC16X_OPERAND_QLOBIT :
+      value = fields->f_qlobit;
+      break;
+    case XC16X_OPERAND_REG8 :
+      value = fields->f_reg8;
+      break;
+    case XC16X_OPERAND_REGB8 :
+      value = fields->f_regb8;
+      break;
+    case XC16X_OPERAND_REGBMEM8 :
+      value = fields->f_regmem8;
+      break;
+    case XC16X_OPERAND_REGHI8 :
+      value = fields->f_reghi8;
+      break;
+    case XC16X_OPERAND_REGMEM8 :
+      value = fields->f_regmem8;
+      break;
+    case XC16X_OPERAND_REGOFF8 :
+      value = fields->f_regoff8;
+      break;
+    case XC16X_OPERAND_REL :
+      value = fields->f_rel8;
+      break;
+    case XC16X_OPERAND_RELHI :
+      value = fields->f_relhi8;
+      break;
+    case XC16X_OPERAND_SEG :
+      value = fields->f_seg8;
+      break;
+    case XC16X_OPERAND_SEGHI8 :
+      value = fields->f_segnum8;
+      break;
+    case XC16X_OPERAND_SEGM :
+      value = 0;
+      break;
+    case XC16X_OPERAND_SOF :
+      value = 0;
+      break;
+    case XC16X_OPERAND_SR :
+      value = fields->f_r2;
+      break;
+    case XC16X_OPERAND_SR2 :
+      value = fields->f_r0;
+      break;
+    case XC16X_OPERAND_SRB :
+      value = fields->f_r2;
+      break;
+    case XC16X_OPERAND_SRC1 :
+      value = fields->f_r1;
+      break;
+    case XC16X_OPERAND_SRC2 :
+      value = fields->f_r2;
+      break;
+    case XC16X_OPERAND_SRDIV :
+      value = fields->f_reg8;
+      break;
+    case XC16X_OPERAND_U4 :
+      value = fields->f_uimm4;
+      break;
+    case XC16X_OPERAND_UIMM16 :
+      value = fields->f_uimm16;
+      break;
+    case XC16X_OPERAND_UIMM2 :
+      value = fields->f_uimm2;
+      break;
+    case XC16X_OPERAND_UIMM3 :
+      value = fields->f_uimm3;
+      break;
+    case XC16X_OPERAND_UIMM4 :
+      value = fields->f_uimm4;
+      break;
+    case XC16X_OPERAND_UIMM7 :
+      value = fields->f_uimm7;
+      break;
+    case XC16X_OPERAND_UIMM8 :
+      value = fields->f_uimm8;
+      break;
+    case XC16X_OPERAND_UPAG16 :
+      value = fields->f_uimm16;
+      break;
+    case XC16X_OPERAND_UPOF16 :
+      value = fields->f_memory;
+      break;
+    case XC16X_OPERAND_USEG16 :
+      value = fields->f_offset16;
+      break;
+    case XC16X_OPERAND_USEG8 :
+      value = fields->f_seg8;
+      break;
+    case XC16X_OPERAND_USOF16 :
+      value = fields->f_offset16;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
+		       opindex);
+      abort ();
+  }
+
+  return value;
+}
+
+void xc16x_cgen_set_int_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, int);
+void xc16x_cgen_set_vma_operand  (CGEN_CPU_DESC, int, CGEN_FIELDS *, bfd_vma);
+
+/* Stuffing values in cgen_fields is handled by a collection of functions.
+   They are distinguished by the type of the VALUE argument they accept.
+   TODO: floating point, inlining support, remove cases where argument type
+   not appropriate.  */
+
+void
+xc16x_cgen_set_int_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     int value)
+{
+  switch (opindex)
+    {
+    case XC16X_OPERAND_REGNAM :
+      fields->f_reg8 = value;
+      break;
+    case XC16X_OPERAND_BIT01 :
+      fields->f_op_1bit = value;
+      break;
+    case XC16X_OPERAND_BIT1 :
+      fields->f_op_bit1 = value;
+      break;
+    case XC16X_OPERAND_BIT2 :
+      fields->f_op_bit2 = value;
+      break;
+    case XC16X_OPERAND_BIT4 :
+      fields->f_op_bit4 = value;
+      break;
+    case XC16X_OPERAND_BIT8 :
+      fields->f_op_bit8 = value;
+      break;
+    case XC16X_OPERAND_BITONE :
+      fields->f_op_onebit = value;
+      break;
+    case XC16X_OPERAND_CADDR :
+      fields->f_offset16 = value;
+      break;
+    case XC16X_OPERAND_COND :
+      fields->f_condcode = value;
+      break;
+    case XC16X_OPERAND_DATA8 :
+      fields->f_data8 = value;
+      break;
+    case XC16X_OPERAND_DATAHI8 :
+      fields->f_datahi8 = value;
+      break;
+    case XC16X_OPERAND_DOT :
+      break;
+    case XC16X_OPERAND_DR :
+      fields->f_r1 = value;
+      break;
+    case XC16X_OPERAND_DRB :
+      fields->f_r1 = value;
+      break;
+    case XC16X_OPERAND_DRI :
+      fields->f_r4 = value;
+      break;
+    case XC16X_OPERAND_EXTCOND :
+      fields->f_extccode = value;
+      break;
+    case XC16X_OPERAND_GENREG :
+      fields->f_regb8 = value;
+      break;
+    case XC16X_OPERAND_HASH :
+      break;
+    case XC16X_OPERAND_ICOND :
+      fields->f_icondcode = value;
+      break;
+    case XC16X_OPERAND_LBIT2 :
+      fields->f_op_lbit2 = value;
+      break;
+    case XC16X_OPERAND_LBIT4 :
+      fields->f_op_lbit4 = value;
+      break;
+    case XC16X_OPERAND_MASK8 :
+      fields->f_mask8 = value;
+      break;
+    case XC16X_OPERAND_MASKLO8 :
+      fields->f_datahi8 = value;
+      break;
+    case XC16X_OPERAND_MEMGR8 :
+      fields->f_memgr8 = value;
+      break;
+    case XC16X_OPERAND_MEMORY :
+      fields->f_memory = value;
+      break;
+    case XC16X_OPERAND_PAG :
+      break;
+    case XC16X_OPERAND_PAGENUM :
+      fields->f_pagenum = value;
+      break;
+    case XC16X_OPERAND_POF :
+      break;
+    case XC16X_OPERAND_QBIT :
+      fields->f_qbit = value;
+      break;
+    case XC16X_OPERAND_QHIBIT :
+      fields->f_qhibit = value;
+      break;
+    case XC16X_OPERAND_QLOBIT :
+      fields->f_qlobit = value;
+      break;
+    case XC16X_OPERAND_REG8 :
+      fields->f_reg8 = value;
+      break;
+    case XC16X_OPERAND_REGB8 :
+      fields->f_regb8 = value;
+      break;
+    case XC16X_OPERAND_REGBMEM8 :
+      fields->f_regmem8 = value;
+      break;
+    case XC16X_OPERAND_REGHI8 :
+      fields->f_reghi8 = value;
+      break;
+    case XC16X_OPERAND_REGMEM8 :
+      fields->f_regmem8 = value;
+      break;
+    case XC16X_OPERAND_REGOFF8 :
+      fields->f_regoff8 = value;
+      break;
+    case XC16X_OPERAND_REL :
+      fields->f_rel8 = value;
+      break;
+    case XC16X_OPERAND_RELHI :
+      fields->f_relhi8 = value;
+      break;
+    case XC16X_OPERAND_SEG :
+      fields->f_seg8 = value;
+      break;
+    case XC16X_OPERAND_SEGHI8 :
+      fields->f_segnum8 = value;
+      break;
+    case XC16X_OPERAND_SEGM :
+      break;
+    case XC16X_OPERAND_SOF :
+      break;
+    case XC16X_OPERAND_SR :
+      fields->f_r2 = value;
+      break;
+    case XC16X_OPERAND_SR2 :
+      fields->f_r0 = value;
+      break;
+    case XC16X_OPERAND_SRB :
+      fields->f_r2 = value;
+      break;
+    case XC16X_OPERAND_SRC1 :
+      fields->f_r1 = value;
+      break;
+    case XC16X_OPERAND_SRC2 :
+      fields->f_r2 = value;
+      break;
+    case XC16X_OPERAND_SRDIV :
+      fields->f_reg8 = value;
+      break;
+    case XC16X_OPERAND_U4 :
+      fields->f_uimm4 = value;
+      break;
+    case XC16X_OPERAND_UIMM16 :
+      fields->f_uimm16 = value;
+      break;
+    case XC16X_OPERAND_UIMM2 :
+      fields->f_uimm2 = value;
+      break;
+    case XC16X_OPERAND_UIMM3 :
+      fields->f_uimm3 = value;
+      break;
+    case XC16X_OPERAND_UIMM4 :
+      fields->f_uimm4 = value;
+      break;
+    case XC16X_OPERAND_UIMM7 :
+      fields->f_uimm7 = value;
+      break;
+    case XC16X_OPERAND_UIMM8 :
+      fields->f_uimm8 = value;
+      break;
+    case XC16X_OPERAND_UPAG16 :
+      fields->f_uimm16 = value;
+      break;
+    case XC16X_OPERAND_UPOF16 :
+      fields->f_memory = value;
+      break;
+    case XC16X_OPERAND_USEG16 :
+      fields->f_offset16 = value;
+      break;
+    case XC16X_OPERAND_USEG8 :
+      fields->f_seg8 = value;
+      break;
+    case XC16X_OPERAND_USOF16 :
+      fields->f_offset16 = value;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
+		       opindex);
+      abort ();
+  }
+}
+
+void
+xc16x_cgen_set_vma_operand (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
+			     int opindex,
+			     CGEN_FIELDS * fields,
+			     bfd_vma value)
+{
+  switch (opindex)
+    {
+    case XC16X_OPERAND_REGNAM :
+      fields->f_reg8 = value;
+      break;
+    case XC16X_OPERAND_BIT01 :
+      fields->f_op_1bit = value;
+      break;
+    case XC16X_OPERAND_BIT1 :
+      fields->f_op_bit1 = value;
+      break;
+    case XC16X_OPERAND_BIT2 :
+      fields->f_op_bit2 = value;
+      break;
+    case XC16X_OPERAND_BIT4 :
+      fields->f_op_bit4 = value;
+      break;
+    case XC16X_OPERAND_BIT8 :
+      fields->f_op_bit8 = value;
+      break;
+    case XC16X_OPERAND_BITONE :
+      fields->f_op_onebit = value;
+      break;
+    case XC16X_OPERAND_CADDR :
+      fields->f_offset16 = value;
+      break;
+    case XC16X_OPERAND_COND :
+      fields->f_condcode = value;
+      break;
+    case XC16X_OPERAND_DATA8 :
+      fields->f_data8 = value;
+      break;
+    case XC16X_OPERAND_DATAHI8 :
+      fields->f_datahi8 = value;
+      break;
+    case XC16X_OPERAND_DOT :
+      break;
+    case XC16X_OPERAND_DR :
+      fields->f_r1 = value;
+      break;
+    case XC16X_OPERAND_DRB :
+      fields->f_r1 = value;
+      break;
+    case XC16X_OPERAND_DRI :
+      fields->f_r4 = value;
+      break;
+    case XC16X_OPERAND_EXTCOND :
+      fields->f_extccode = value;
+      break;
+    case XC16X_OPERAND_GENREG :
+      fields->f_regb8 = value;
+      break;
+    case XC16X_OPERAND_HASH :
+      break;
+    case XC16X_OPERAND_ICOND :
+      fields->f_icondcode = value;
+      break;
+    case XC16X_OPERAND_LBIT2 :
+      fields->f_op_lbit2 = value;
+      break;
+    case XC16X_OPERAND_LBIT4 :
+      fields->f_op_lbit4 = value;
+      break;
+    case XC16X_OPERAND_MASK8 :
+      fields->f_mask8 = value;
+      break;
+    case XC16X_OPERAND_MASKLO8 :
+      fields->f_datahi8 = value;
+      break;
+    case XC16X_OPERAND_MEMGR8 :
+      fields->f_memgr8 = value;
+      break;
+    case XC16X_OPERAND_MEMORY :
+      fields->f_memory = value;
+      break;
+    case XC16X_OPERAND_PAG :
+      break;
+    case XC16X_OPERAND_PAGENUM :
+      fields->f_pagenum = value;
+      break;
+    case XC16X_OPERAND_POF :
+      break;
+    case XC16X_OPERAND_QBIT :
+      fields->f_qbit = value;
+      break;
+    case XC16X_OPERAND_QHIBIT :
+      fields->f_qhibit = value;
+      break;
+    case XC16X_OPERAND_QLOBIT :
+      fields->f_qlobit = value;
+      break;
+    case XC16X_OPERAND_REG8 :
+      fields->f_reg8 = value;
+      break;
+    case XC16X_OPERAND_REGB8 :
+      fields->f_regb8 = value;
+      break;
+    case XC16X_OPERAND_REGBMEM8 :
+      fields->f_regmem8 = value;
+      break;
+    case XC16X_OPERAND_REGHI8 :
+      fields->f_reghi8 = value;
+      break;
+    case XC16X_OPERAND_REGMEM8 :
+      fields->f_regmem8 = value;
+      break;
+    case XC16X_OPERAND_REGOFF8 :
+      fields->f_regoff8 = value;
+      break;
+    case XC16X_OPERAND_REL :
+      fields->f_rel8 = value;
+      break;
+    case XC16X_OPERAND_RELHI :
+      fields->f_relhi8 = value;
+      break;
+    case XC16X_OPERAND_SEG :
+      fields->f_seg8 = value;
+      break;
+    case XC16X_OPERAND_SEGHI8 :
+      fields->f_segnum8 = value;
+      break;
+    case XC16X_OPERAND_SEGM :
+      break;
+    case XC16X_OPERAND_SOF :
+      break;
+    case XC16X_OPERAND_SR :
+      fields->f_r2 = value;
+      break;
+    case XC16X_OPERAND_SR2 :
+      fields->f_r0 = value;
+      break;
+    case XC16X_OPERAND_SRB :
+      fields->f_r2 = value;
+      break;
+    case XC16X_OPERAND_SRC1 :
+      fields->f_r1 = value;
+      break;
+    case XC16X_OPERAND_SRC2 :
+      fields->f_r2 = value;
+      break;
+    case XC16X_OPERAND_SRDIV :
+      fields->f_reg8 = value;
+      break;
+    case XC16X_OPERAND_U4 :
+      fields->f_uimm4 = value;
+      break;
+    case XC16X_OPERAND_UIMM16 :
+      fields->f_uimm16 = value;
+      break;
+    case XC16X_OPERAND_UIMM2 :
+      fields->f_uimm2 = value;
+      break;
+    case XC16X_OPERAND_UIMM3 :
+      fields->f_uimm3 = value;
+      break;
+    case XC16X_OPERAND_UIMM4 :
+      fields->f_uimm4 = value;
+      break;
+    case XC16X_OPERAND_UIMM7 :
+      fields->f_uimm7 = value;
+      break;
+    case XC16X_OPERAND_UIMM8 :
+      fields->f_uimm8 = value;
+      break;
+    case XC16X_OPERAND_UPAG16 :
+      fields->f_uimm16 = value;
+      break;
+    case XC16X_OPERAND_UPOF16 :
+      fields->f_memory = value;
+      break;
+    case XC16X_OPERAND_USEG16 :
+      fields->f_offset16 = value;
+      break;
+    case XC16X_OPERAND_USEG8 :
+      fields->f_seg8 = value;
+      break;
+    case XC16X_OPERAND_USOF16 :
+      fields->f_offset16 = value;
+      break;
+
+    default :
+      /* xgettext:c-format */
+      fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
+		       opindex);
+      abort ();
+  }
+}
+
+/* Function to call before using the instruction builder tables.  */
+
+void
+xc16x_cgen_init_ibld_table (CGEN_CPU_DESC cd)
+{
+  cd->insert_handlers = & xc16x_cgen_insert_handlers[0];
+  cd->extract_handlers = & xc16x_cgen_extract_handlers[0];
+
+  cd->insert_operand = xc16x_cgen_insert_operand;
+  cd->extract_operand = xc16x_cgen_extract_operand;
+
+  cd->get_int_operand = xc16x_cgen_get_int_operand;
+  cd->set_int_operand = xc16x_cgen_set_int_operand;
+  cd->get_vma_operand = xc16x_cgen_get_vma_operand;
+  cd->set_vma_operand = xc16x_cgen_set_vma_operand;
+}
diff --git a/opcodes/xc16x-opc.c b/opcodes/xc16x-opc.c
new file mode 100644
index 0000000..8352237
--- /dev/null
+++ b/opcodes/xc16x-opc.c
@@ -0,0 +1,3073 @@
+/* Instruction opcode table for xc16x.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2005 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sysdep.h"
+#include "ansidecl.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "xc16x-desc.h"
+#include "xc16x-opc.h"
+#include "libiberty.h"
+
+/* -- opc.c */
+                                                                                
+/* -- */
+/* The hash functions are recorded here to help keep assembler code out of
+   the disassembler and vice versa.  */
+
+static int asm_hash_insn_p        (const CGEN_INSN *);
+static unsigned int asm_hash_insn (const char *);
+static int dis_hash_insn_p        (const CGEN_INSN *);
+static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT);
+
+/* Instruction formats.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define F(f) & xc16x_cgen_ifld_table[XC16X_##f]
+#else
+#define F(f) & xc16x_cgen_ifld_table[XC16X_/**/f]
+#endif
+static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = {
+  0, 0, 0x0, { { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addrpof ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addbrpof ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addrpag ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_UIMM16) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addbrpag ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_UIMM16) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addrhpof ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_UIMM16) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addrhpof3 ATTRIBUTE_UNUSED = {
+  16, 16, 0x8ff, { { F (F_R1) }, { F (F_OP_BIT1) }, { F (F_UIMM3) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addbrhpag3 ATTRIBUTE_UNUSED = {
+  16, 16, 0x8ff, { { F (F_R1) }, { F (F_OP_BIT1) }, { F (F_UIMM3) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addrbhpof ATTRIBUTE_UNUSED = {
+  32, 32, 0xff0000ff, { { F (F_OP_BIT8) }, { F (F_UIMM8) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addr ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addbr ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_add2 ATTRIBUTE_UNUSED = {
+  16, 16, 0xcff, { { F (F_R1) }, { F (F_OP_BIT2) }, { F (F_R0) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addb2 ATTRIBUTE_UNUSED = {
+  16, 16, 0xcff, { { F (F_R1) }, { F (F_OP_BIT2) }, { F (F_R0) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addrm2 ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_MEMGR8) }, { F (F_REGMEM8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addrm ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addbrm2 ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_MEMGR8) }, { F (F_REGMEM8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_addbrm ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_muls ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_div ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cpl ATTRIBUTE_UNUSED = {
+  16, 16, 0xfff, { { F (F_R1) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cplb ATTRIBUTE_UNUSED = {
+  16, 16, 0xfff, { { F (F_R1) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movri ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_UIMM4) }, { F (F_R4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movbri ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_UIMM4) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movbr2 ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_mov9i ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_UIMM16) }, { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movb9i ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_UIMM16) }, { F (F_R1) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movri11 ATTRIBUTE_UNUSED = {
+  32, 32, 0xf0ff, { { F (F_MEMORY) }, { F (F_OP_LBIT4) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movehm5 ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movehm6 ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_UIMM16) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movehm7 ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movehm8 ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movehm10 ATTRIBUTE_UNUSED = {
+  32, 32, 0xff0000ff, { { F (F_OP_BIT8) }, { F (F_UIMM8) }, { F (F_REGOFF8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movbsrpofm ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGMEM8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_movbspofmr ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_MEMORY) }, { F (F_REGMEM8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jmpa0 ATTRIBUTE_UNUSED = {
+  32, 32, 0x4ff, { { F (F_OFFSET16) }, { F (F_EXTCCODE) }, { F (F_OP_BITONE) }, { F (F_OP_ONEBIT) }, { F (F_OP_1BIT) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jmpa_ ATTRIBUTE_UNUSED = {
+  32, 32, 0x5ff, { { F (F_OFFSET16) }, { F (F_EXTCCODE) }, { F (F_OP_BITONE) }, { F (F_OP_ONEBIT) }, { F (F_OP_1BIT) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jmpi ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_ICONDCODE) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jmpr_nenz ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_REL8) }, { F (F_RCOND) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jmpseg ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_SEG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jmps ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_SEG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_jb ATTRIBUTE_UNUSED = {
+  32, 32, 0xf0000ff, { { F (F_QLOBIT) }, { F (F_QHIBIT) }, { F (F_RELHI8) }, { F (F_REGB8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_calla0 ATTRIBUTE_UNUSED = {
+  32, 32, 0x6ff, { { F (F_OFFSET16) }, { F (F_EXTCCODE) }, { F (F_OP_2BIT) }, { F (F_OP_1BIT) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_calla_ ATTRIBUTE_UNUSED = {
+  32, 32, 0x7ff, { { F (F_OFFSET16) }, { F (F_EXTCCODE) }, { F (F_OP_BIT3) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_callr ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_REL8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_callseg ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_SEG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_pcall ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_OFFSET16) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_trap ATTRIBUTE_UNUSED = {
+  16, 16, 0x1ff, { { F (F_UIMM7) }, { F (F_OP_1BIT) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_ret ATTRIBUTE_UNUSED = {
+  16, 16, 0xff0000ff, { { F (F_OP_BIT8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_retp ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_reti ATTRIBUTE_UNUSED = {
+  16, 16, 0xffff, { { F (F_OP_LBIT4) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_srstm ATTRIBUTE_UNUSED = {
+  32, 32, 0xffffffff, { { F (F_OP_BIT8) }, { F (F_DATA8) }, { F (F_OP_LBIT4) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_atomic ATTRIBUTE_UNUSED = {
+  16, 16, 0xcfff, { { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_extp ATTRIBUTE_UNUSED = {
+  16, 16, 0xc0ff, { { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_extp1 ATTRIBUTE_UNUSED = {
+  32, 32, 0xfc00cfff, { { F (F_QLOBIT) }, { F (F_QLOBIT2) }, { F (F_PAGENUM) }, { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_extpg1 ATTRIBUTE_UNUSED = {
+  32, 32, 0xcfff, { { F (F_UIMM16) }, { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_exts1 ATTRIBUTE_UNUSED = {
+  32, 32, 0xff00cfff, { { F (F_OP_BIT8) }, { F (F_SEGNUM8) }, { F (F_OP_LBIT2) }, { F (F_UIMM2) }, { F (F_OP_BIT4) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bclr18 ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bclr0 ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_REG8) }, { F (F_QCOND) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bmov ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_QLOBIT) }, { F (F_QHIBIT) }, { F (F_REGHI8) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bfldl ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_DATAHI8) }, { F (F_MASK8) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_bfldh ATTRIBUTE_UNUSED = {
+  32, 32, 0xff, { { F (F_DATAHI8) }, { F (F_DATA8) }, { F (F_REG8) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmpri ATTRIBUTE_UNUSED = {
+  16, 16, 0x8ff, { { F (F_R1) }, { F (F_OP_BIT1) }, { F (F_UIMM3) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_cmpd1ri ATTRIBUTE_UNUSED = {
+  16, 16, 0xff, { { F (F_UIMM4) }, { F (F_R2) }, { F (F_OP1) }, { F (F_OP2) }, { 0 } }
+};
+
+#undef F
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) XC16X_OPERAND_##op
+#else
+#define OPERAND(op) XC16X_OPERAND_/**/op
+#endif
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The instruction table.  */
+
+static const CGEN_OPCODE xc16x_cgen_insn_opcode_table[MAX_INSNS] =
+{
+  /* Special null first entry.
+     A `num' value of zero is thus invalid.
+     Also, the special `invalid' insn resides here.  */
+  { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
+/* add $reg8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0x2 }
+  },
+/* sub $reg8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0x22 }
+  },
+/* addb $regb8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addbrpof, { 0x3 }
+  },
+/* subb $regb8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addbrpof, { 0x23 }
+  },
+/* add $reg8,$pag$upag16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (PAG), OP (UPAG16), 0 } },
+    & ifmt_addrpag, { 0x2 }
+  },
+/* sub $reg8,$pag$upag16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (PAG), OP (UPAG16), 0 } },
+    & ifmt_addrpag, { 0x22 }
+  },
+/* addb $regb8,$pag$upag16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } },
+    & ifmt_addbrpag, { 0x3 }
+  },
+/* subb $regb8,$pag$upag16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } },
+    & ifmt_addbrpag, { 0x23 }
+  },
+/* addc $reg8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0x12 }
+  },
+/* subc $reg8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0x32 }
+  },
+/* addcb $regb8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addbrpof, { 0x13 }
+  },
+/* subcb $regb8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addbrpof, { 0x33 }
+  },
+/* addc $reg8,$pag$upag16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (PAG), OP (UPAG16), 0 } },
+    & ifmt_addrpag, { 0x12 }
+  },
+/* subc $reg8,$pag$upag16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (PAG), OP (UPAG16), 0 } },
+    & ifmt_addrpag, { 0x32 }
+  },
+/* addcb $regb8,$pag$upag16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } },
+    & ifmt_addbrpag, { 0x13 }
+  },
+/* subcb $regb8,$pag$upag16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } },
+    & ifmt_addbrpag, { 0x33 }
+  },
+/* add $pof$upof16,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
+    & ifmt_addrpof, { 0x4 }
+  },
+/* sub $pof$upof16,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
+    & ifmt_addrpof, { 0x24 }
+  },
+/* addb $pof$upof16,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
+    & ifmt_addbrpof, { 0x5 }
+  },
+/* subb $pof$upof16,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
+    & ifmt_addbrpof, { 0x25 }
+  },
+/* addc $pof$upof16,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
+    & ifmt_addrpof, { 0x14 }
+  },
+/* subc $pof$upof16,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
+    & ifmt_addrpof, { 0x34 }
+  },
+/* addcb $pof$upof16,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
+    & ifmt_addbrpof, { 0x15 }
+  },
+/* subcb $pof$upof16,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
+    & ifmt_addbrpof, { 0x35 }
+  },
+/* add $reg8,$hash$pof$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (POF), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x6 }
+  },
+/* sub $reg8,$hash$pof$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (POF), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x26 }
+  },
+/* add $reg8,$hash$pag$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (PAG), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x6 }
+  },
+/* sub $reg8,$hash$pag$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (PAG), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x26 }
+  },
+/* add $dr,$hash$pof$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x8 }
+  },
+/* sub $dr,$hash$pof$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x28 }
+  },
+/* addb $drb,$hash$pag$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x9 }
+  },
+/* subb $drb,$hash$pag$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x29 }
+  },
+/* add $dr,$hash$pag$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x8 }
+  },
+/* sub $dr,$hash$pag$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x28 }
+  },
+/* addb $drb,$hash$pof$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x9 }
+  },
+/* subb $drb,$hash$pof$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x29 }
+  },
+/* addb $regb8,$hash$pof$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x7 }
+  },
+/* subb $regb8,$hash$pof$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x27 }
+  },
+/* addb $regb8,$hash$pag$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x7 }
+  },
+/* subb $regb8,$hash$pag$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x27 }
+  },
+/* addc $reg8,$hash$pof$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (POF), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x16 }
+  },
+/* subc $reg8,$hash$pof$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (POF), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x36 }
+  },
+/* addc $reg8,$hash$pag$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (PAG), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x16 }
+  },
+/* subc $reg8,$hash$pag$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (PAG), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x36 }
+  },
+/* addc $dr,$hash$pof$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x18 }
+  },
+/* subc $dr,$hash$pof$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x38 }
+  },
+/* addcb $drb,$hash$pag$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x19 }
+  },
+/* subcb $drb,$hash$pag$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x39 }
+  },
+/* addc $dr,$hash$pag$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x18 }
+  },
+/* subc $dr,$hash$pag$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x38 }
+  },
+/* addcb $drb,$hash$pof$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x19 }
+  },
+/* subcb $drb,$hash$pof$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x39 }
+  },
+/* addcb $regb8,$hash$pof$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x17 }
+  },
+/* subcb $regb8,$hash$pof$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x37 }
+  },
+/* addcb $regb8,$hash$pag$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x17 }
+  },
+/* subcb $regb8,$hash$pag$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x37 }
+  },
+/* add $dr,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x8 }
+  },
+/* sub $dr,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x28 }
+  },
+/* addb $drb,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x9 }
+  },
+/* subb $drb,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x29 }
+  },
+/* add $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x6 }
+  },
+/* sub $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x26 }
+  },
+/* addb $regb8,$hash$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x7 }
+  },
+/* subb $regb8,$hash$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x27 }
+  },
+/* addc $dr,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x18 }
+  },
+/* subc $dr,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x38 }
+  },
+/* addcb $drb,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x19 }
+  },
+/* subcb $drb,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x39 }
+  },
+/* addc $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x16 }
+  },
+/* subc $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x36 }
+  },
+/* addcb $regb8,$hash$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x17 }
+  },
+/* subcb $regb8,$hash$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x37 }
+  },
+/* add $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0x0 }
+  },
+/* sub $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0x20 }
+  },
+/* addb $drb,$srb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
+    & ifmt_addbr, { 0x1 }
+  },
+/* subb $drb,$srb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
+    & ifmt_addbr, { 0x21 }
+  },
+/* add $dr,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_add2, { 0x808 }
+  },
+/* sub $dr,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_add2, { 0x828 }
+  },
+/* addb $drb,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_addb2, { 0x809 }
+  },
+/* subb $drb,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_addb2, { 0x829 }
+  },
+/* add $dr,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_add2, { 0xc08 }
+  },
+/* sub $dr,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_add2, { 0xc28 }
+  },
+/* addb $drb,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_addb2, { 0xc09 }
+  },
+/* subb $drb,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_addb2, { 0xc29 }
+  },
+/* addc $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0x10 }
+  },
+/* subc $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0x30 }
+  },
+/* addcb $drb,$srb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
+    & ifmt_addbr, { 0x11 }
+  },
+/* subcb $drb,$srb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
+    & ifmt_addbr, { 0x31 }
+  },
+/* addc $dr,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_add2, { 0x818 }
+  },
+/* subc $dr,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_add2, { 0x838 }
+  },
+/* addcb $drb,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_addb2, { 0x819 }
+  },
+/* subcb $drb,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_addb2, { 0x839 }
+  },
+/* addc $dr,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_add2, { 0xc18 }
+  },
+/* subc $dr,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_add2, { 0xc38 }
+  },
+/* addcb $drb,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_addb2, { 0xc19 }
+  },
+/* subcb $drb,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_addb2, { 0xc39 }
+  },
+/* add $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0x2 }
+  },
+/* add $memgr8,$regmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
+    & ifmt_addrm2, { 0x4 }
+  },
+/* add $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0x2 }
+  },
+/* add $memory,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
+    & ifmt_addrm, { 0x4 }
+  },
+/* sub $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0x22 }
+  },
+/* sub $memgr8,$regmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
+    & ifmt_addrm2, { 0x24 }
+  },
+/* sub $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0x22 }
+  },
+/* sub $memory,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
+    & ifmt_addrm, { 0x24 }
+  },
+/* addb $regbmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addbrm2, { 0x3 }
+  },
+/* addb $memgr8,$regbmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
+    & ifmt_addbrm2, { 0x5 }
+  },
+/* addb $regb8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
+    & ifmt_addbrm, { 0x3 }
+  },
+/* addb $memory,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
+    & ifmt_addbrm, { 0x5 }
+  },
+/* subb $regbmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addbrm2, { 0x23 }
+  },
+/* subb $memgr8,$regbmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
+    & ifmt_addbrm2, { 0x25 }
+  },
+/* subb $regb8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
+    & ifmt_addbrm, { 0x23 }
+  },
+/* subb $memory,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
+    & ifmt_addbrm, { 0x25 }
+  },
+/* addc $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0x12 }
+  },
+/* addc $memgr8,$regmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
+    & ifmt_addrm2, { 0x14 }
+  },
+/* addc $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0x12 }
+  },
+/* addc $memory,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
+    & ifmt_addrm, { 0x14 }
+  },
+/* subc $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0x32 }
+  },
+/* subc $memgr8,$regmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
+    & ifmt_addrm2, { 0x34 }
+  },
+/* subc $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0x32 }
+  },
+/* subc $memory,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
+    & ifmt_addrm, { 0x34 }
+  },
+/* addcb $regbmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addbrm2, { 0x13 }
+  },
+/* addcb $memgr8,$regbmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
+    & ifmt_addbrm2, { 0x15 }
+  },
+/* addcb $regb8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
+    & ifmt_addbrm, { 0x13 }
+  },
+/* addcb $memory,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
+    & ifmt_addbrm, { 0x15 }
+  },
+/* subcb $regbmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addbrm2, { 0x33 }
+  },
+/* subcb $memgr8,$regbmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
+    & ifmt_addbrm2, { 0x35 }
+  },
+/* subcb $regb8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
+    & ifmt_addbrm, { 0x33 }
+  },
+/* subcb $memory,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
+    & ifmt_addbrm, { 0x35 }
+  },
+/* mul $src1,$src2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+    & ifmt_muls, { 0xb }
+  },
+/* mulu $src1,$src2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+    & ifmt_muls, { 0x1b }
+  },
+/* div $srdiv */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRDIV), 0 } },
+    & ifmt_div, { 0x4b }
+  },
+/* divl $srdiv */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRDIV), 0 } },
+    & ifmt_div, { 0x6b }
+  },
+/* divlu $srdiv */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRDIV), 0 } },
+    & ifmt_div, { 0x7b }
+  },
+/* divu $srdiv */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRDIV), 0 } },
+    & ifmt_div, { 0x5b }
+  },
+/* cpl $dr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), 0 } },
+    & ifmt_cpl, { 0x91 }
+  },
+/* cplb $drb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), 0 } },
+    & ifmt_cplb, { 0xb1 }
+  },
+/* neg $dr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), 0 } },
+    & ifmt_cpl, { 0x81 }
+  },
+/* negb $drb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), 0 } },
+    & ifmt_cplb, { 0xa1 }
+  },
+/* and $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0x60 }
+  },
+/* or $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0x70 }
+  },
+/* xor $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0x50 }
+  },
+/* andb $drb,$srb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
+    & ifmt_addbr, { 0x61 }
+  },
+/* orb $drb,$srb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
+    & ifmt_addbr, { 0x71 }
+  },
+/* xorb $drb,$srb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
+    & ifmt_addbr, { 0x51 }
+  },
+/* and $dr,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x68 }
+  },
+/* or $dr,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x78 }
+  },
+/* xor $dr,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addrhpof3, { 0x58 }
+  },
+/* andb $drb,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x69 }
+  },
+/* orb $drb,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x79 }
+  },
+/* xorb $drb,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x59 }
+  },
+/* and $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x66 }
+  },
+/* or $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x76 }
+  },
+/* xor $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x56 }
+  },
+/* andb $regb8,$hash$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x67 }
+  },
+/* orb $regb8,$hash$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x77 }
+  },
+/* xorb $regb8,$hash$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x57 }
+  },
+/* and $dr,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_add2, { 0x868 }
+  },
+/* or $dr,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_add2, { 0x878 }
+  },
+/* xor $dr,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_add2, { 0x858 }
+  },
+/* andb $drb,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_addb2, { 0x869 }
+  },
+/* orb $drb,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_addb2, { 0x879 }
+  },
+/* xorb $drb,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_addb2, { 0x859 }
+  },
+/* and $dr,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_add2, { 0xc68 }
+  },
+/* or $dr,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_add2, { 0xc78 }
+  },
+/* xor $dr,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_add2, { 0xc58 }
+  },
+/* andb $drb,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_addb2, { 0xc69 }
+  },
+/* orb $drb,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_addb2, { 0xc79 }
+  },
+/* xorb $drb,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_addb2, { 0xc59 }
+  },
+/* and $pof$reg8,$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (REG8), ',', OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0x62 }
+  },
+/* or $pof$reg8,$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (REG8), ',', OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0x72 }
+  },
+/* xor $pof$reg8,$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (REG8), ',', OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0x52 }
+  },
+/* andb $pof$regb8,$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (REGB8), ',', OP (UPOF16), 0 } },
+    & ifmt_addbrpof, { 0x63 }
+  },
+/* orb $pof$regb8,$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (REGB8), ',', OP (UPOF16), 0 } },
+    & ifmt_addbrpof, { 0x73 }
+  },
+/* xorb $pof$regb8,$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (REGB8), ',', OP (UPOF16), 0 } },
+    & ifmt_addbrpof, { 0x53 }
+  },
+/* and $pof$upof16,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
+    & ifmt_addrpof, { 0x64 }
+  },
+/* or $pof$upof16,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
+    & ifmt_addrpof, { 0x74 }
+  },
+/* xor $pof$upof16,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REG8), 0 } },
+    & ifmt_addrpof, { 0x54 }
+  },
+/* andb $pof$upof16,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
+    & ifmt_addbrpof, { 0x65 }
+  },
+/* orb $pof$upof16,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
+    & ifmt_addbrpof, { 0x75 }
+  },
+/* xorb $pof$upof16,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
+    & ifmt_addbrpof, { 0x55 }
+  },
+/* and $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0x62 }
+  },
+/* and $memgr8,$regmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
+    & ifmt_addrm2, { 0x64 }
+  },
+/* and $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0x62 }
+  },
+/* and $memory,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
+    & ifmt_addrm, { 0x64 }
+  },
+/* or $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0x72 }
+  },
+/* or $memgr8,$regmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
+    & ifmt_addrm2, { 0x74 }
+  },
+/* or $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0x72 }
+  },
+/* or $memory,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
+    & ifmt_addrm, { 0x74 }
+  },
+/* xor $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0x52 }
+  },
+/* xor $memgr8,$regmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
+    & ifmt_addrm2, { 0x54 }
+  },
+/* xor $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0x52 }
+  },
+/* xor $memory,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
+    & ifmt_addrm, { 0x54 }
+  },
+/* andb $regbmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addbrm2, { 0x63 }
+  },
+/* andb $memgr8,$regbmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
+    & ifmt_addbrm2, { 0x65 }
+  },
+/* andb $regb8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
+    & ifmt_addbrm, { 0x63 }
+  },
+/* andb $memory,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
+    & ifmt_addbrm, { 0x65 }
+  },
+/* orb $regbmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addbrm2, { 0x73 }
+  },
+/* orb $memgr8,$regbmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
+    & ifmt_addbrm2, { 0x75 }
+  },
+/* orb $regb8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
+    & ifmt_addbrm, { 0x73 }
+  },
+/* orb $memory,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
+    & ifmt_addbrm, { 0x75 }
+  },
+/* xorb $regbmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addbrm2, { 0x53 }
+  },
+/* xorb $memgr8,$regbmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
+    & ifmt_addbrm2, { 0x55 }
+  },
+/* xorb $regb8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
+    & ifmt_addbrm, { 0x53 }
+  },
+/* xorb $memory,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
+    & ifmt_addbrm, { 0x55 }
+  },
+/* mov $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0xf0 }
+  },
+/* movb $drb,$srb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
+    & ifmt_addbr, { 0xf1 }
+  },
+/* mov $dri,$hash$u4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRI), ',', OP (HASH), OP (U4), 0 } },
+    & ifmt_movri, { 0xe0 }
+  },
+/* movb $srb,$hash$u4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRB), ',', OP (HASH), OP (U4), 0 } },
+    & ifmt_movbri, { 0xe1 }
+  },
+/* mov $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0xe6 }
+  },
+/* movb $regb8,$hash$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0xe7 }
+  },
+/* mov $dr,[$sr] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR), ']', 0 } },
+    & ifmt_addr, { 0xa8 }
+  },
+/* movb $drb,[$sr] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR), ']', 0 } },
+    & ifmt_movbr2, { 0xa9 }
+  },
+/* mov [$sr],$dr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (SR), ']', ',', OP (DR), 0 } },
+    & ifmt_addr, { 0xb8 }
+  },
+/* movb [$sr],$drb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (SR), ']', ',', OP (DRB), 0 } },
+    & ifmt_movbr2, { 0xb9 }
+  },
+/* mov [-$sr],$dr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', '-', OP (SR), ']', ',', OP (DR), 0 } },
+    & ifmt_addr, { 0x88 }
+  },
+/* movb [-$sr],$drb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', '-', OP (SR), ']', ',', OP (DRB), 0 } },
+    & ifmt_movbr2, { 0x89 }
+  },
+/* mov $dr,[$sr+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR), '+', ']', 0 } },
+    & ifmt_addr, { 0x98 }
+  },
+/* movb $drb,[$sr+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR), '+', ']', 0 } },
+    & ifmt_movbr2, { 0x99 }
+  },
+/* mov [$dr],[$sr] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (DR), ']', ',', '[', OP (SR), ']', 0 } },
+    & ifmt_addr, { 0xc8 }
+  },
+/* movb [$dr],[$sr] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (DR), ']', ',', '[', OP (SR), ']', 0 } },
+    & ifmt_addr, { 0xc9 }
+  },
+/* mov [$dr+],[$sr] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (DR), '+', ']', ',', '[', OP (SR), ']', 0 } },
+    & ifmt_addr, { 0xd8 }
+  },
+/* movb [$dr+],[$sr] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (DR), '+', ']', ',', '[', OP (SR), ']', 0 } },
+    & ifmt_addr, { 0xd9 }
+  },
+/* mov [$dr],[$sr+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (DR), ']', ',', '[', OP (SR), '+', ']', 0 } },
+    & ifmt_addr, { 0xe8 }
+  },
+/* movb [$dr],[$sr+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (DR), ']', ',', '[', OP (SR), '+', ']', 0 } },
+    & ifmt_addr, { 0xe9 }
+  },
+/* mov $dr,[$sr+$hash$uimm16] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR), '+', OP (HASH), OP (UIMM16), ']', 0 } },
+    & ifmt_mov9i, { 0xd4 }
+  },
+/* movb $drb,[$sr+$hash$uimm16] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR), '+', OP (HASH), OP (UIMM16), ']', 0 } },
+    & ifmt_movb9i, { 0xf4 }
+  },
+/* mov [$sr+$hash$uimm16],$dr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (SR), '+', OP (HASH), OP (UIMM16), ']', ',', OP (DR), 0 } },
+    & ifmt_mov9i, { 0xc4 }
+  },
+/* movb [$sr+$hash$uimm16],$drb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (SR), '+', OP (HASH), OP (UIMM16), ']', ',', OP (DRB), 0 } },
+    & ifmt_movb9i, { 0xe4 }
+  },
+/* mov [$src2],$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (SRC2), ']', ',', OP (MEMORY), 0 } },
+    & ifmt_movri11, { 0x84 }
+  },
+/* movb [$src2],$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', '[', OP (SRC2), ']', ',', OP (MEMORY), 0 } },
+    & ifmt_movri11, { 0xa4 }
+  },
+/* mov $memory,[$src2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', '[', OP (SRC2), ']', 0 } },
+    & ifmt_movri11, { 0x94 }
+  },
+/* movb $memory,[$src2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', '[', OP (SRC2), ']', 0 } },
+    & ifmt_movri11, { 0xb4 }
+  },
+/* mov $regoff8,$hash$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (POF), OP (UPOF16), 0 } },
+    & ifmt_movehm5, { 0xe6 }
+  },
+/* mov $regoff8,$hash$pag$upag16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (PAG), OP (UPAG16), 0 } },
+    & ifmt_movehm6, { 0xe6 }
+  },
+/* mov $regoff8,$hash$segm$useg16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (SEGM), OP (USEG16), 0 } },
+    & ifmt_movehm7, { 0xe6 }
+  },
+/* mov $regoff8,$hash$sof$usof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (SOF), OP (USOF16), 0 } },
+    & ifmt_movehm8, { 0xe6 }
+  },
+/* movb $regb8,$hash$pof$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (POF), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0xe7 }
+  },
+/* movb $regoff8,$hash$pag$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGOFF8), ',', OP (HASH), OP (PAG), OP (UIMM8), 0 } },
+    & ifmt_movehm10, { 0xe7 }
+  },
+/* mov $regoff8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGOFF8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_movehm5, { 0xf2 }
+  },
+/* movb $regb8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addbrpof, { 0xf3 }
+  },
+/* mov $regoff8,$pag$upag16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGOFF8), ',', OP (PAG), OP (UPAG16), 0 } },
+    & ifmt_movehm6, { 0xf2 }
+  },
+/* movb $regb8,$pag$upag16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (PAG), OP (UPAG16), 0 } },
+    & ifmt_addbrpag, { 0xf3 }
+  },
+/* mov $pof$upof16,$regoff8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGOFF8), 0 } },
+    & ifmt_movehm5, { 0xf6 }
+  },
+/* movb $pof$upof16,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
+    & ifmt_addbrpof, { 0xf7 }
+  },
+/* mov $dri,$hash$pof$u4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRI), ',', OP (HASH), OP (POF), OP (U4), 0 } },
+    & ifmt_movri, { 0xe0 }
+  },
+/* movb $srb,$hash$pof$u4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRB), ',', OP (HASH), OP (POF), OP (U4), 0 } },
+    & ifmt_movbri, { 0xe1 }
+  },
+/* mov $dri,$hash$pag$u4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRI), ',', OP (HASH), OP (PAG), OP (U4), 0 } },
+    & ifmt_movri, { 0xe0 }
+  },
+/* movb $srb,$hash$pag$u4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRB), ',', OP (HASH), OP (PAG), OP (U4), 0 } },
+    & ifmt_movbri, { 0xe1 }
+  },
+/* mov $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0xf2 }
+  },
+/* mov $memgr8,$regmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGMEM8), 0 } },
+    & ifmt_addrm2, { 0xf6 }
+  },
+/* mov $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0xf2 }
+  },
+/* mov $memory,$reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REG8), 0 } },
+    & ifmt_addrm, { 0xf6 }
+  },
+/* movb $regbmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addbrm2, { 0xf3 }
+  },
+/* movb $memgr8,$regbmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
+    & ifmt_addbrm2, { 0xf7 }
+  },
+/* movb $regb8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
+    & ifmt_addbrm, { 0xf3 }
+  },
+/* movb $memory,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
+    & ifmt_addbrm, { 0xf7 }
+  },
+/* movbs $sr,$drb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (DRB), 0 } },
+    & ifmt_movbr2, { 0xd0 }
+  },
+/* movbz $sr,$drb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (DRB), 0 } },
+    & ifmt_movbr2, { 0xc0 }
+  },
+/* movbs $regmem8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_movbsrpofm, { 0xd2 }
+  },
+/* movbs $pof$upof16,$regbmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGBMEM8), 0 } },
+    & ifmt_movbspofmr, { 0xd5 }
+  },
+/* movbz $reg8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0xc2 }
+  },
+/* movbz $pof$upof16,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (POF), OP (UPOF16), ',', OP (REGB8), 0 } },
+    & ifmt_addbrpof, { 0xc5 }
+  },
+/* movbs $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0xd2 }
+  },
+/* movbs $memgr8,$regbmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
+    & ifmt_addbrm2, { 0xd5 }
+  },
+/* movbs $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0xd2 }
+  },
+/* movbs $memory,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
+    & ifmt_addbrm, { 0xd5 }
+  },
+/* movbz $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0xc2 }
+  },
+/* movbz $memgr8,$regbmem8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMGR8), ',', OP (REGBMEM8), 0 } },
+    & ifmt_addbrm2, { 0xc5 }
+  },
+/* movbz $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0xc2 }
+  },
+/* movbz $memory,$regb8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (MEMORY), ',', OP (REGB8), 0 } },
+    & ifmt_addbrm, { 0xc5 }
+  },
+/* movbs $sr,$drb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (DRB), 0 } },
+    & ifmt_movbr2, { 0xd0 }
+  },
+/* movbz $sr,$drb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (DRB), 0 } },
+    & ifmt_movbr2, { 0xc0 }
+  },
+/* jmpa+ $extcond,$caddr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } },
+    & ifmt_jmpa0, { 0xea }
+  },
+/* jmpa $extcond,$caddr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } },
+    & ifmt_jmpa0, { 0xea }
+  },
+/* jmpa- $extcond,$caddr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } },
+    & ifmt_jmpa_, { 0x1ea }
+  },
+/* jmpi $icond,[$sr] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (ICOND), ',', '[', OP (SR), ']', 0 } },
+    & ifmt_jmpi, { 0x9c }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0x3d }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0xad }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0x2d }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0x4d }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0x5d }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0x6d }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0x7d }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0x8d }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0x9d }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0x2d }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0x3d }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0x8d }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0xfd }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0x9d }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0xed }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0xbd }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0xdd }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0x1d }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0xd }
+  },
+/* jmpr $cond,$rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (COND), ',', OP (REL), 0 } },
+    & ifmt_jmpr_nenz, { 0xcd }
+  },
+/* jmps $hash$segm$useg8,$hash$sof$usof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (HASH), OP (SEGM), OP (USEG8), ',', OP (HASH), OP (SOF), OP (USOF16), 0 } },
+    & ifmt_jmpseg, { 0xfa }
+  },
+/* jmps $seg,$caddr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SEG), ',', OP (CADDR), 0 } },
+    & ifmt_jmps, { 0xfa }
+  },
+/* jb $genreg$dot$qlobit,$relhi */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (GENREG), OP (DOT), OP (QLOBIT), ',', OP (RELHI), 0 } },
+    & ifmt_jb, { 0x8a }
+  },
+/* jbc $genreg$dot$qlobit,$relhi */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (GENREG), OP (DOT), OP (QLOBIT), ',', OP (RELHI), 0 } },
+    & ifmt_jb, { 0xaa }
+  },
+/* jnb $genreg$dot$qlobit,$relhi */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (GENREG), OP (DOT), OP (QLOBIT), ',', OP (RELHI), 0 } },
+    & ifmt_jb, { 0x9a }
+  },
+/* jnbs $genreg$dot$qlobit,$relhi */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (GENREG), OP (DOT), OP (QLOBIT), ',', OP (RELHI), 0 } },
+    & ifmt_jb, { 0xba }
+  },
+/* calla+ $extcond,$caddr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } },
+    & ifmt_calla0, { 0xca }
+  },
+/* calla $extcond,$caddr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } },
+    & ifmt_calla0, { 0xca }
+  },
+/* calla- $extcond,$caddr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (EXTCOND), ',', OP (CADDR), 0 } },
+    & ifmt_calla_, { 0x1ca }
+  },
+/* calli $icond,[$sr] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (ICOND), ',', '[', OP (SR), ']', 0 } },
+    & ifmt_jmpi, { 0xab }
+  },
+/* callr $rel */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REL), 0 } },
+    & ifmt_callr, { 0xbb }
+  },
+/* calls $hash$segm$useg8,$hash$sof$usof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (HASH), OP (SEGM), OP (USEG8), ',', OP (HASH), OP (SOF), OP (USOF16), 0 } },
+    & ifmt_callseg, { 0xda }
+  },
+/* calls $seg,$caddr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SEG), ',', OP (CADDR), 0 } },
+    & ifmt_jmps, { 0xda }
+  },
+/* pcall $reg8,$caddr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (CADDR), 0 } },
+    & ifmt_pcall, { 0xe2 }
+  },
+/* trap $hash$uimm7 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (HASH), OP (UIMM7), 0 } },
+    & ifmt_trap, { 0x9b }
+  },
+/* ret */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_ret, { 0xcb }
+  },
+/* rets */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_ret, { 0xdb }
+  },
+/* retp $reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), 0 } },
+    & ifmt_retp, { 0xeb }
+  },
+/* reti */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_reti, { 0x88fb }
+  },
+/* pop $reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), 0 } },
+    & ifmt_retp, { 0xfc }
+  },
+/* push $reg8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), 0 } },
+    & ifmt_retp, { 0xec }
+  },
+/* scxt $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0xc6 }
+  },
+/* scxt $reg8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0xd6 }
+  },
+/* scxt $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0xd6 }
+  },
+/* scxt $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0xd6 }
+  },
+/* nop */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_ret, { 0xcc }
+  },
+/* srst */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_srstm, { 0xb7b748b7 }
+  },
+/* idle */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_srstm, { 0x87877887 }
+  },
+/* pwrdn */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_srstm, { 0x97976897 }
+  },
+/* diswdt */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_srstm, { 0xa5a55aa5 }
+  },
+/* enwdt */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_srstm, { 0x85857a85 }
+  },
+/* einit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_srstm, { 0xb5b54ab5 }
+  },
+/* srvwdt */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_srstm, { 0xa7a758a7 }
+  },
+/* sbrk */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, 0 } },
+    & ifmt_ret, { 0x8c }
+  },
+/* atomic $hash$uimm2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (HASH), OP (UIMM2), 0 } },
+    & ifmt_atomic, { 0xd1 }
+  },
+/* extr $hash$uimm2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (HASH), OP (UIMM2), 0 } },
+    & ifmt_atomic, { 0x80d1 }
+  },
+/* extp $sr,$hash$uimm2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM2), 0 } },
+    & ifmt_extp, { 0x40dc }
+  },
+/* extp $hash$pagenum,$hash$uimm2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (HASH), OP (PAGENUM), ',', OP (HASH), OP (UIMM2), 0 } },
+    & ifmt_extp1, { 0x40d7 }
+  },
+/* extp $hash$pag$upag16,$hash$uimm2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (HASH), OP (PAG), OP (UPAG16), ',', OP (HASH), OP (UIMM2), 0 } },
+    & ifmt_extpg1, { 0x40d7 }
+  },
+/* extpr $sr,$hash$uimm2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM2), 0 } },
+    & ifmt_extp, { 0xc0dc }
+  },
+/* extpr $hash$pagenum,$hash$uimm2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (HASH), OP (PAGENUM), ',', OP (HASH), OP (UIMM2), 0 } },
+    & ifmt_extp1, { 0xc0d7 }
+  },
+/* exts $sr,$hash$uimm2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM2), 0 } },
+    & ifmt_extp, { 0xdc }
+  },
+/* exts $hash$seghi8,$hash$uimm2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (HASH), OP (SEGHI8), ',', OP (HASH), OP (UIMM2), 0 } },
+    & ifmt_exts1, { 0xd7 }
+  },
+/* extsr $sr,$hash$uimm2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM2), 0 } },
+    & ifmt_extp, { 0x80dc }
+  },
+/* extsr $hash$seghi8,$hash$uimm2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (HASH), OP (SEGHI8), ',', OP (HASH), OP (UIMM2), 0 } },
+    & ifmt_exts1, { 0x80d7 }
+  },
+/* prior $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0x2b }
+  },
+/* bclr $RegNam */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGNAM), 0 } },
+    & ifmt_bclr18, { 0xbe }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xe }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x1e }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x2e }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x3e }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x4e }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x5e }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x6e }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x7e }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x8e }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x9e }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xae }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xbe }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xce }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xde }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xee }
+  },
+/* bclr $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xfe }
+  },
+/* bset $RegNam */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGNAM), 0 } },
+    & ifmt_bclr18, { 0xbf }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xf }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x1f }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x2f }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x3f }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x4f }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x5f }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x6f }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x7f }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x8f }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0x9f }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xaf }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xbf }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xcf }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xdf }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xef }
+  },
+/* bset $reg8$dot$qbit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), OP (DOT), OP (QBIT), 0 } },
+    & ifmt_bclr0, { 0xff }
+  },
+/* bmov $reghi8$dot$qhibit,$reg8$dot$qlobit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } },
+    & ifmt_bmov, { 0x4a }
+  },
+/* bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } },
+    & ifmt_bmov, { 0x3a }
+  },
+/* band $reghi8$dot$qhibit,$reg8$dot$qlobit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } },
+    & ifmt_bmov, { 0x6a }
+  },
+/* bor $reghi8$dot$qhibit,$reg8$dot$qlobit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } },
+    & ifmt_bmov, { 0x5a }
+  },
+/* bxor $reghi8$dot$qhibit,$reg8$dot$qlobit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } },
+    & ifmt_bmov, { 0x7a }
+  },
+/* bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGHI8), OP (DOT), OP (QHIBIT), ',', OP (REG8), OP (DOT), OP (QLOBIT), 0 } },
+    & ifmt_bmov, { 0x2a }
+  },
+/* bfldl $reg8,$hash$mask8,$hash$datahi8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (MASK8), ',', OP (HASH), OP (DATAHI8), 0 } },
+    & ifmt_bfldl, { 0xa }
+  },
+/* bfldh $reg8,$hash$masklo8,$hash$data8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (MASKLO8), ',', OP (HASH), OP (DATA8), 0 } },
+    & ifmt_bfldh, { 0x1a }
+  },
+/* cmp $src1,$src2 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 } },
+    & ifmt_muls, { 0x40 }
+  },
+/* cmpb $drb,$srb */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (SRB), 0 } },
+    & ifmt_addbr, { 0x41 }
+  },
+/* cmp $src1,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SRC1), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_cmpri, { 0x48 }
+  },
+/* cmpb $drb,$hash$uimm3 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', OP (HASH), OP (UIMM3), 0 } },
+    & ifmt_addbrhpag3, { 0x49 }
+  },
+/* cmp $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x46 }
+  },
+/* cmpb $regb8,$hash$uimm8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (HASH), OP (UIMM8), 0 } },
+    & ifmt_addrbhpof, { 0x47 }
+  },
+/* cmp $dr,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_add2, { 0x848 }
+  },
+/* cmpb $drb,[$sr2] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), ']', 0 } },
+    & ifmt_addb2, { 0x849 }
+  },
+/* cmp $dr,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_add2, { 0xc48 }
+  },
+/* cmpb $drb,[$sr2+] */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DRB), ',', '[', OP (SR2), '+', ']', 0 } },
+    & ifmt_addb2, { 0xc49 }
+  },
+/* cmp $reg8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0x42 }
+  },
+/* cmpb $regb8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addbrpof, { 0x43 }
+  },
+/* cmp $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0x42 }
+  },
+/* cmp $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0x42 }
+  },
+/* cmpb $regbmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGBMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addbrm2, { 0x43 }
+  },
+/* cmpb $regb8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGB8), ',', OP (MEMORY), 0 } },
+    & ifmt_addbrm, { 0x43 }
+  },
+/* cmpd1 $sr,$hash$uimm4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
+    & ifmt_cmpd1ri, { 0xa0 }
+  },
+/* cmpd2 $sr,$hash$uimm4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
+    & ifmt_cmpd1ri, { 0xb0 }
+  },
+/* cmpi1 $sr,$hash$uimm4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
+    & ifmt_cmpd1ri, { 0x80 }
+  },
+/* cmpi2 $sr,$hash$uimm4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
+    & ifmt_cmpd1ri, { 0x90 }
+  },
+/* cmpd1 $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0xa6 }
+  },
+/* cmpd2 $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0xb6 }
+  },
+/* cmpi1 $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x86 }
+  },
+/* cmpi2 $reg8,$hash$uimm16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (HASH), OP (UIMM16), 0 } },
+    & ifmt_addrhpof, { 0x96 }
+  },
+/* cmpd1 $reg8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0xa2 }
+  },
+/* cmpd2 $reg8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0xb2 }
+  },
+/* cmpi1 $reg8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0x82 }
+  },
+/* cmpi2 $reg8,$pof$upof16 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (POF), OP (UPOF16), 0 } },
+    & ifmt_addrpof, { 0x92 }
+  },
+/* cmpd1 $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0xa2 }
+  },
+/* cmpd2 $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0xb2 }
+  },
+/* cmpi1 $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0x82 }
+  },
+/* cmpi2 $regmem8,$memgr8 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REGMEM8), ',', OP (MEMGR8), 0 } },
+    & ifmt_addrm2, { 0x92 }
+  },
+/* cmpd1 $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0xa2 }
+  },
+/* cmpd2 $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0xb2 }
+  },
+/* cmpi1 $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0x82 }
+  },
+/* cmpi2 $reg8,$memory */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (REG8), ',', OP (MEMORY), 0 } },
+    & ifmt_addrm, { 0x92 }
+  },
+/* shl $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0x4c }
+  },
+/* shr $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0x6c }
+  },
+/* rol $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0xc }
+  },
+/* ror $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0x2c }
+  },
+/* ashr $dr,$sr */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } },
+    & ifmt_addr, { 0xac }
+  },
+/* shl $sr,$hash$uimm4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
+    & ifmt_cmpd1ri, { 0x5c }
+  },
+/* shr $sr,$hash$uimm4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
+    & ifmt_cmpd1ri, { 0x7c }
+  },
+/* rol $sr,$hash$uimm4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
+    & ifmt_cmpd1ri, { 0x1c }
+  },
+/* ror $sr,$hash$uimm4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
+    & ifmt_cmpd1ri, { 0x3c }
+  },
+/* ashr $sr,$hash$uimm4 */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (SR), ',', OP (HASH), OP (UIMM4), 0 } },
+    & ifmt_cmpd1ri, { 0xbc }
+  },
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+/* Formats for ALIAS macro-insns.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define F(f) & xc16x_cgen_ifld_table[XC16X_##f]
+#else
+#define F(f) & xc16x_cgen_ifld_table[XC16X_/**/f]
+#endif
+#undef F
+
+/* Each non-simple macro entry points to an array of expansion possibilities.  */
+
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) XC16X_OPERAND_##op
+#else
+#define OPERAND(op) XC16X_OPERAND_/**/op
+#endif
+#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+
+/* The macro instruction table.  */
+
+static const CGEN_IBASE xc16x_cgen_macro_insn_table[] =
+{
+};
+
+/* The macro instruction opcode table.  */
+
+static const CGEN_OPCODE xc16x_cgen_macro_insn_opcode_table[] =
+{
+};
+
+#undef A
+#undef OPERAND
+#undef MNEM
+#undef OP
+
+#ifndef CGEN_ASM_HASH_P
+#define CGEN_ASM_HASH_P(insn) 1
+#endif
+
+#ifndef CGEN_DIS_HASH_P
+#define CGEN_DIS_HASH_P(insn) 1
+#endif
+
+/* Return non-zero if INSN is to be added to the hash table.
+   Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file.  */
+
+static int
+asm_hash_insn_p (insn)
+     const CGEN_INSN *insn ATTRIBUTE_UNUSED;
+{
+  return CGEN_ASM_HASH_P (insn);
+}
+
+static int
+dis_hash_insn_p (insn)
+     const CGEN_INSN *insn;
+{
+  /* If building the hash table and the NO-DIS attribute is present,
+     ignore.  */
+  if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS))
+    return 0;
+  return CGEN_DIS_HASH_P (insn);
+}
+
+#ifndef CGEN_ASM_HASH
+#define CGEN_ASM_HASH_SIZE 127
+#ifdef CGEN_MNEMONIC_OPERANDS
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
+#else
+#define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
+#endif
+#endif
+
+/* It doesn't make much sense to provide a default here,
+   but while this is under development we do.
+   BUFFER is a pointer to the bytes of the insn, target order.
+   VALUE is the first base_insn_bitsize bits as an int in host order.  */
+
+#ifndef CGEN_DIS_HASH
+#define CGEN_DIS_HASH_SIZE 256
+#define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
+#endif
+
+/* The result is the hash value of the insn.
+   Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file.  */
+
+static unsigned int
+asm_hash_insn (mnem)
+     const char * mnem;
+{
+  return CGEN_ASM_HASH (mnem);
+}
+
+/* BUF is a pointer to the bytes of the insn, target order.
+   VALUE is the first base_insn_bitsize bits as an int in host order.  */
+
+static unsigned int
+dis_hash_insn (buf, value)
+     const char * buf ATTRIBUTE_UNUSED;
+     CGEN_INSN_INT value ATTRIBUTE_UNUSED;
+{
+  return CGEN_DIS_HASH (buf, value);
+}
+
+/* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
+
+static void
+set_fields_bitsize (CGEN_FIELDS *fields, int size)
+{
+  CGEN_FIELDS_BITSIZE (fields) = size;
+}
+
+/* Function to call before using the operand instance table.
+   This plugs the opcode entries and macro instructions into the cpu table.  */
+
+void
+xc16x_cgen_init_opcode_table (CGEN_CPU_DESC cd)
+{
+  int i;
+  int num_macros = (sizeof (xc16x_cgen_macro_insn_table) /
+		    sizeof (xc16x_cgen_macro_insn_table[0]));
+  const CGEN_IBASE *ib = & xc16x_cgen_macro_insn_table[0];
+  const CGEN_OPCODE *oc = & xc16x_cgen_macro_insn_opcode_table[0];
+  CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN));
+
+  memset (insns, 0, num_macros * sizeof (CGEN_INSN));
+  for (i = 0; i < num_macros; ++i)
+    {
+      insns[i].base = &ib[i];
+      insns[i].opcode = &oc[i];
+      xc16x_cgen_build_insn_regex (& insns[i]);
+    }
+  cd->macro_insn_table.init_entries = insns;
+  cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
+  cd->macro_insn_table.num_init_entries = num_macros;
+
+  oc = & xc16x_cgen_insn_opcode_table[0];
+  insns = (CGEN_INSN *) cd->insn_table.init_entries;
+  for (i = 0; i < MAX_INSNS; ++i)
+    {
+      insns[i].opcode = &oc[i];
+      xc16x_cgen_build_insn_regex (& insns[i]);
+    }
+
+  cd->sizeof_fields = sizeof (CGEN_FIELDS);
+  cd->set_fields_bitsize = set_fields_bitsize;
+
+  cd->asm_hash_p = asm_hash_insn_p;
+  cd->asm_hash = asm_hash_insn;
+  cd->asm_hash_size = CGEN_ASM_HASH_SIZE;
+
+  cd->dis_hash_p = dis_hash_insn_p;
+  cd->dis_hash = dis_hash_insn;
+  cd->dis_hash_size = CGEN_DIS_HASH_SIZE;
+}
diff --git a/opcodes/xc16x-opc.h b/opcodes/xc16x-opc.h
new file mode 100644
index 0000000..e368123
--- /dev/null
+++ b/opcodes/xc16x-opc.h
@@ -0,0 +1,225 @@
+/* Instruction opcode header for xc16x.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2005 Free Software Foundation, Inc.
+
+This file is part of the GNU Binutils and/or GDB, the GNU debugger.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#ifndef XC16X_OPC_H
+#define XC16X_OPC_H
+
+/* -- opc.h */
+
+#define CGEN_DIS_HASH_SIZE 8
+#define CGEN_DIS_HASH(buf,value) (((* (unsigned char*) (buf)) >> 3) % CGEN_DIS_HASH_SIZE)
+
+/* -- */
+/* Enum declaration for xc16x instruction types.  */
+typedef enum cgen_insn_type {
+  XC16X_INSN_INVALID, XC16X_INSN_ADDRPOF, XC16X_INSN_SUBRPOF, XC16X_INSN_ADDBRPOF
+ , XC16X_INSN_SUBBRPOF, XC16X_INSN_ADDRPAG, XC16X_INSN_SUBRPAG, XC16X_INSN_ADDBRPAG
+ , XC16X_INSN_SUBBRPAG, XC16X_INSN_ADDCRPOF, XC16X_INSN_SUBCRPOF, XC16X_INSN_ADDCBRPOF
+ , XC16X_INSN_SUBCBRPOF, XC16X_INSN_ADDCRPAG, XC16X_INSN_SUBCRPAG, XC16X_INSN_ADDCBRPAG
+ , XC16X_INSN_SUBCBRPAG, XC16X_INSN_ADDRPOFR, XC16X_INSN_SUBRPOFR, XC16X_INSN_ADDBRPOFR
+ , XC16X_INSN_SUBBRPOFR, XC16X_INSN_ADDCRPOFR, XC16X_INSN_SUBCRPOFR, XC16X_INSN_ADDCBRPOFR
+ , XC16X_INSN_SUBCBRPOFR, XC16X_INSN_ADDRHPOF, XC16X_INSN_SUBRHPOF, XC16X_INSN_ADDBRHPOF
+ , XC16X_INSN_SUBBRHPOF, XC16X_INSN_ADDRHPOF3, XC16X_INSN_SUBRHPOF3, XC16X_INSN_ADDBRHPAG3
+ , XC16X_INSN_SUBBRHPAG3, XC16X_INSN_ADDRHPAG3, XC16X_INSN_SUBRHPAG3, XC16X_INSN_ADDBRHPOF3
+ , XC16X_INSN_SUBBRHPOF3, XC16X_INSN_ADDRBHPOF, XC16X_INSN_SUBRBHPOF, XC16X_INSN_ADDBRHPAG
+ , XC16X_INSN_SUBBRHPAG, XC16X_INSN_ADDCRHPOF, XC16X_INSN_SUBCRHPOF, XC16X_INSN_ADDCBRHPOF
+ , XC16X_INSN_SUBCBRHPOF, XC16X_INSN_ADDCRHPOF3, XC16X_INSN_SUBCRHPOF3, XC16X_INSN_ADDCBRHPAG3
+ , XC16X_INSN_SUBCBRHPAG3, XC16X_INSN_ADDCRHPAG3, XC16X_INSN_SUBCRHPAG3, XC16X_INSN_ADDCBRHPOF3
+ , XC16X_INSN_SUBCBRHPOF3, XC16X_INSN_ADDCRBHPOF, XC16X_INSN_SUBCRBHPOF, XC16X_INSN_ADDCBRHPAG
+ , XC16X_INSN_SUBCBRHPAG, XC16X_INSN_ADDRI, XC16X_INSN_SUBRI, XC16X_INSN_ADDBRI
+ , XC16X_INSN_SUBBRI, XC16X_INSN_ADDRIM, XC16X_INSN_SUBRIM, XC16X_INSN_ADDBRIM
+ , XC16X_INSN_SUBBRIM, XC16X_INSN_ADDCRI, XC16X_INSN_SUBCRI, XC16X_INSN_ADDCBRI
+ , XC16X_INSN_SUBCBRI, XC16X_INSN_ADDCRIM, XC16X_INSN_SUBCRIM, XC16X_INSN_ADDCBRIM
+ , XC16X_INSN_SUBCBRIM, XC16X_INSN_ADDR, XC16X_INSN_SUBR, XC16X_INSN_ADDBR
+ , XC16X_INSN_SUBBR, XC16X_INSN_ADD2, XC16X_INSN_SUB2, XC16X_INSN_ADDB2
+ , XC16X_INSN_SUBB2, XC16X_INSN_ADD2I, XC16X_INSN_SUB2I, XC16X_INSN_ADDB2I
+ , XC16X_INSN_SUBB2I, XC16X_INSN_ADDCR, XC16X_INSN_SUBCR, XC16X_INSN_ADDBCR
+ , XC16X_INSN_SUBBCR, XC16X_INSN_ADDCR2, XC16X_INSN_SUBCR2, XC16X_INSN_ADDBCR2
+ , XC16X_INSN_SUBBCR2, XC16X_INSN_ADDCR2I, XC16X_INSN_SUBCR2I, XC16X_INSN_ADDBCR2I
+ , XC16X_INSN_SUBBCR2I, XC16X_INSN_ADDRM2, XC16X_INSN_ADDRM3, XC16X_INSN_ADDRM
+ , XC16X_INSN_ADDRM1, XC16X_INSN_SUBRM3, XC16X_INSN_SUBRM2, XC16X_INSN_SUBRM1
+ , XC16X_INSN_SUBRM, XC16X_INSN_ADDBRM2, XC16X_INSN_ADDBRM3, XC16X_INSN_ADDBRM
+ , XC16X_INSN_ADDBRM1, XC16X_INSN_SUBBRM3, XC16X_INSN_SUBBRM2, XC16X_INSN_SUBBRM1
+ , XC16X_INSN_SUBBRM, XC16X_INSN_ADDCRM2, XC16X_INSN_ADDCRM3, XC16X_INSN_ADDCRM
+ , XC16X_INSN_ADDCRM1, XC16X_INSN_SUBCRM3, XC16X_INSN_SUBCRM2, XC16X_INSN_SUBCRM1
+ , XC16X_INSN_SUBCRM, XC16X_INSN_ADDCBRM2, XC16X_INSN_ADDCBRM3, XC16X_INSN_ADDCBRM
+ , XC16X_INSN_ADDCBRM1, XC16X_INSN_SUBCBRM3, XC16X_INSN_SUBCBRM2, XC16X_INSN_SUBCBRM1
+ , XC16X_INSN_SUBCBRM, XC16X_INSN_MULS, XC16X_INSN_MULU, XC16X_INSN_DIV
+ , XC16X_INSN_DIVL, XC16X_INSN_DIVLU, XC16X_INSN_DIVU, XC16X_INSN_CPL
+ , XC16X_INSN_CPLB, XC16X_INSN_NEG, XC16X_INSN_NEGB, XC16X_INSN_ANDR
+ , XC16X_INSN_ORR, XC16X_INSN_XORR, XC16X_INSN_ANDBR, XC16X_INSN_ORBR
+ , XC16X_INSN_XORBR, XC16X_INSN_ANDRI, XC16X_INSN_ORRI, XC16X_INSN_XORRI
+ , XC16X_INSN_ANDBRI, XC16X_INSN_ORBRI, XC16X_INSN_XORBRI, XC16X_INSN_ANDRIM
+ , XC16X_INSN_ORRIM, XC16X_INSN_XORRIM, XC16X_INSN_ANDBRIM, XC16X_INSN_ORBRIM
+ , XC16X_INSN_XORBRIM, XC16X_INSN_AND2, XC16X_INSN_OR2, XC16X_INSN_XOR2
+ , XC16X_INSN_ANDB2, XC16X_INSN_ORB2, XC16X_INSN_XORB2, XC16X_INSN_AND2I
+ , XC16X_INSN_OR2I, XC16X_INSN_XOR2I, XC16X_INSN_ANDB2I, XC16X_INSN_ORB2I
+ , XC16X_INSN_XORB2I, XC16X_INSN_ANDPOFR, XC16X_INSN_ORPOFR, XC16X_INSN_XORPOFR
+ , XC16X_INSN_ANDBPOFR, XC16X_INSN_ORBPOFR, XC16X_INSN_XORBPOFR, XC16X_INSN_ANDRPOFR
+ , XC16X_INSN_ORRPOFR, XC16X_INSN_XORRPOFR, XC16X_INSN_ANDBRPOFR, XC16X_INSN_ORBRPOFR
+ , XC16X_INSN_XORBRPOFR, XC16X_INSN_ANDRM2, XC16X_INSN_ANDRM3, XC16X_INSN_ANDRM
+ , XC16X_INSN_ANDRM1, XC16X_INSN_ORRM3, XC16X_INSN_ORRM2, XC16X_INSN_ORRM1
+ , XC16X_INSN_ORRM, XC16X_INSN_XORRM3, XC16X_INSN_XORRM2, XC16X_INSN_XORRM1
+ , XC16X_INSN_XORRM, XC16X_INSN_ANDBRM2, XC16X_INSN_ANDBRM3, XC16X_INSN_ANDBRM
+ , XC16X_INSN_ANDBRM1, XC16X_INSN_ORBRM3, XC16X_INSN_ORBRM2, XC16X_INSN_ORBRM1
+ , XC16X_INSN_ORBRM, XC16X_INSN_XORBRM3, XC16X_INSN_XORBRM2, XC16X_INSN_XORBRM1
+ , XC16X_INSN_XORBRM, XC16X_INSN_MOVR, XC16X_INSN_MOVRB, XC16X_INSN_MOVRI
+ , XC16X_INSN_MOVBRI, XC16X_INSN_MOVI, XC16X_INSN_MOVBI, XC16X_INSN_MOVR2
+ , XC16X_INSN_MOVBR2, XC16X_INSN_MOVRI2, XC16X_INSN_MOVBRI2, XC16X_INSN_MOVRI3
+ , XC16X_INSN_MOVBRI3, XC16X_INSN_MOV2I, XC16X_INSN_MOVB2I, XC16X_INSN_MOV6I
+ , XC16X_INSN_MOVB6I, XC16X_INSN_MOV7I, XC16X_INSN_MOVB7I, XC16X_INSN_MOV8I
+ , XC16X_INSN_MOVB8I, XC16X_INSN_MOV9I, XC16X_INSN_MOVB9I, XC16X_INSN_MOV10I
+ , XC16X_INSN_MOVB10I, XC16X_INSN_MOVRI11, XC16X_INSN_MOVBRI11, XC16X_INSN_MOVRI12
+ , XC16X_INSN_MOVBRI12, XC16X_INSN_MOVEHM5, XC16X_INSN_MOVEHM6, XC16X_INSN_MOVEHM7
+ , XC16X_INSN_MOVEHM8, XC16X_INSN_MOVEHM9, XC16X_INSN_MOVEHM10, XC16X_INSN_MOVRMP
+ , XC16X_INSN_MOVRMP1, XC16X_INSN_MOVRMP2, XC16X_INSN_MOVRMP3, XC16X_INSN_MOVRMP4
+ , XC16X_INSN_MOVRMP5, XC16X_INSN_MOVEHM1, XC16X_INSN_MOVEHM2, XC16X_INSN_MOVEHM3
+ , XC16X_INSN_MOVEHM4, XC16X_INSN_MVE12, XC16X_INSN_MVE13, XC16X_INSN_MOVER12
+ , XC16X_INSN_MVR13, XC16X_INSN_MVER12, XC16X_INSN_MVER13, XC16X_INSN_MOVR12
+ , XC16X_INSN_MOVR13, XC16X_INSN_MOVBSRR, XC16X_INSN_MOVBZRR, XC16X_INSN_MOVBSRPOFM
+ , XC16X_INSN_MOVBSPOFMR, XC16X_INSN_MOVBZRPOFM, XC16X_INSN_MOVBZPOFMR, XC16X_INSN_MOVEBS14
+ , XC16X_INSN_MOVEBS15, XC16X_INSN_MOVERBS14, XC16X_INSN_MOVRBS15, XC16X_INSN_MOVEBZ14
+ , XC16X_INSN_MOVEBZ15, XC16X_INSN_MOVERBZ14, XC16X_INSN_MOVRBZ15, XC16X_INSN_MOVRBS
+ , XC16X_INSN_MOVRBZ, XC16X_INSN_JMPA0, XC16X_INSN_JMPA1, XC16X_INSN_JMPA_
+ , XC16X_INSN_JMPI, XC16X_INSN_JMPR_NENZ, XC16X_INSN_JMPR_SGT, XC16X_INSN_JMPR_Z
+ , XC16X_INSN_JMPR_V, XC16X_INSN_JMPR_NV, XC16X_INSN_JMPR_N, XC16X_INSN_JMPR_NN
+ , XC16X_INSN_JMPR_C, XC16X_INSN_JMPR_NC, XC16X_INSN_JMPR_EQ, XC16X_INSN_JMPR_NE
+ , XC16X_INSN_JMPR_ULT, XC16X_INSN_JMPR_ULE, XC16X_INSN_JMPR_UGE, XC16X_INSN_JMPR_UGT
+ , XC16X_INSN_JMPR_SLE, XC16X_INSN_JMPR_SGE, XC16X_INSN_JMPR_NET, XC16X_INSN_JMPR_UC
+ , XC16X_INSN_JMPR_SLT, XC16X_INSN_JMPSEG, XC16X_INSN_JMPS, XC16X_INSN_JB
+ , XC16X_INSN_JBC, XC16X_INSN_JNB, XC16X_INSN_JNBS, XC16X_INSN_CALLA0
+ , XC16X_INSN_CALLA1, XC16X_INSN_CALLA_, XC16X_INSN_CALLI, XC16X_INSN_CALLR
+ , XC16X_INSN_CALLSEG, XC16X_INSN_CALLS, XC16X_INSN_PCALL, XC16X_INSN_TRAP
+ , XC16X_INSN_RET, XC16X_INSN_RETS, XC16X_INSN_RETP, XC16X_INSN_RETI
+ , XC16X_INSN_POP, XC16X_INSN_PUSH, XC16X_INSN_SCXTI, XC16X_INSN_SCXTRPOFM
+ , XC16X_INSN_SCXTMG, XC16X_INSN_SCXTM, XC16X_INSN_NOP, XC16X_INSN_SRSTM
+ , XC16X_INSN_IDLEM, XC16X_INSN_PWRDNM, XC16X_INSN_DISWDTM, XC16X_INSN_ENWDTM
+ , XC16X_INSN_EINITM, XC16X_INSN_SRVWDTM, XC16X_INSN_SBRK, XC16X_INSN_ATOMIC
+ , XC16X_INSN_EXTR, XC16X_INSN_EXTP, XC16X_INSN_EXTP1, XC16X_INSN_EXTPG1
+ , XC16X_INSN_EXTPR, XC16X_INSN_EXTPR1, XC16X_INSN_EXTS, XC16X_INSN_EXTS1
+ , XC16X_INSN_EXTSR, XC16X_INSN_EXTSR1, XC16X_INSN_PRIOR, XC16X_INSN_BCLR18
+ , XC16X_INSN_BCLR0, XC16X_INSN_BCLR1, XC16X_INSN_BCLR2, XC16X_INSN_BCLR3
+ , XC16X_INSN_BCLR4, XC16X_INSN_BCLR5, XC16X_INSN_BCLR6, XC16X_INSN_BCLR7
+ , XC16X_INSN_BCLR8, XC16X_INSN_BCLR9, XC16X_INSN_BCLR10, XC16X_INSN_BCLR11
+ , XC16X_INSN_BCLR12, XC16X_INSN_BCLR13, XC16X_INSN_BCLR14, XC16X_INSN_BCLR15
+ , XC16X_INSN_BSET19, XC16X_INSN_BSET0, XC16X_INSN_BSET1, XC16X_INSN_BSET2
+ , XC16X_INSN_BSET3, XC16X_INSN_BSET4, XC16X_INSN_BSET5, XC16X_INSN_BSET6
+ , XC16X_INSN_BSET7, XC16X_INSN_BSET8, XC16X_INSN_BSET9, XC16X_INSN_BSET10
+ , XC16X_INSN_BSET11, XC16X_INSN_BSET12, XC16X_INSN_BSET13, XC16X_INSN_BSET14
+ , XC16X_INSN_BSET15, XC16X_INSN_BMOV, XC16X_INSN_BMOVN, XC16X_INSN_BAND
+ , XC16X_INSN_BOR, XC16X_INSN_BXOR, XC16X_INSN_BCMP, XC16X_INSN_BFLDL
+ , XC16X_INSN_BFLDH, XC16X_INSN_CMPR, XC16X_INSN_CMPBR, XC16X_INSN_CMPRI
+ , XC16X_INSN_CMPBRI, XC16X_INSN_CMPI, XC16X_INSN_CMPBI, XC16X_INSN_CMPR2
+ , XC16X_INSN_CMPBR2, XC16X_INSN_CMP2I, XC16X_INSN_CMPB2I, XC16X_INSN_CMP04
+ , XC16X_INSN_CMPB4, XC16X_INSN_CMP004, XC16X_INSN_CMP0004, XC16X_INSN_CMPB04
+ , XC16X_INSN_CMPB004, XC16X_INSN_CMPD1RI, XC16X_INSN_CMPD2RI, XC16X_INSN_CMPI1RI
+ , XC16X_INSN_CMPI2RI, XC16X_INSN_CMPD1RIM, XC16X_INSN_CMPD2RIM, XC16X_INSN_CMPI1RIM
+ , XC16X_INSN_CMPI2RIM, XC16X_INSN_CMPD1RP, XC16X_INSN_CMPD2RP, XC16X_INSN_CMPI1RP
+ , XC16X_INSN_CMPI2RP, XC16X_INSN_CMPD1RM, XC16X_INSN_CMPD2RM, XC16X_INSN_CMPI1RM
+ , XC16X_INSN_CMPI2RM, XC16X_INSN_CMPD1RMI, XC16X_INSN_CMPD2RMI, XC16X_INSN_CMPI1RMI
+ , XC16X_INSN_CMPI2RMI, XC16X_INSN_SHLR, XC16X_INSN_SHRR, XC16X_INSN_ROLR
+ , XC16X_INSN_RORR, XC16X_INSN_ASHRR, XC16X_INSN_SHLRI, XC16X_INSN_SHRRI
+ , XC16X_INSN_ROLRI, XC16X_INSN_RORRI, XC16X_INSN_ASHRRI
+} CGEN_INSN_TYPE;
+
+/* Index of `invalid' insn place holder.  */
+#define CGEN_INSN_INVALID XC16X_INSN_INVALID
+
+/* Total number of insns in table.  */
+#define MAX_INSNS ((int) XC16X_INSN_ASHRRI + 1)
+
+/* This struct records data prior to insertion or after extraction.  */
+struct cgen_fields
+{
+  int length;
+  long f_nil;
+  long f_anyof;
+  long f_op1;
+  long f_op2;
+  long f_condcode;
+  long f_icondcode;
+  long f_rcond;
+  long f_qcond;
+  long f_extccode;
+  long f_r0;
+  long f_r1;
+  long f_r2;
+  long f_r3;
+  long f_r4;
+  long f_uimm2;
+  long f_uimm3;
+  long f_uimm4;
+  long f_uimm7;
+  long f_uimm8;
+  long f_uimm16;
+  long f_memory;
+  long f_memgr8;
+  long f_rel8;
+  long f_relhi8;
+  long f_reg8;
+  long f_regmem8;
+  long f_regoff8;
+  long f_reghi8;
+  long f_regb8;
+  long f_seg8;
+  long f_segnum8;
+  long f_mask8;
+  long f_pagenum;
+  long f_datahi8;
+  long f_data8;
+  long f_offset16;
+  long f_op_bit1;
+  long f_op_bit2;
+  long f_op_bit4;
+  long f_op_bit3;
+  long f_op_2bit;
+  long f_op_bitone;
+  long f_op_onebit;
+  long f_op_1bit;
+  long f_op_lbit4;
+  long f_op_lbit2;
+  long f_op_bit8;
+  long f_op_bit16;
+  long f_qbit;
+  long f_qlobit;
+  long f_qhibit;
+  long f_qlobit2;
+  long f_pof;
+};
+
+#define CGEN_INIT_PARSE(od) \
+{\
+}
+#define CGEN_INIT_INSERT(od) \
+{\
+}
+#define CGEN_INIT_EXTRACT(od) \
+{\
+}
+#define CGEN_INIT_PRINT(od) \
+{\
+}
+
+
+#endif /* XC16X_OPC_H */