aboutsummaryrefslogtreecommitdiff
path: root/opcodes
diff options
context:
space:
mode:
authorDoug Evans <dje@google.com>2009-11-04 06:18:27 +0000
committerDoug Evans <dje@google.com>2009-11-04 06:18:27 +0000
commitd51b88d344bee97bcc464c442d5240183907c598 (patch)
tree2c5501a6fa04bd06d483fae837b9947a12c20712 /opcodes
parentfb067cad5a9db4b965304bcd276c2f18a8cf2cbb (diff)
downloadgdb-d51b88d344bee97bcc464c442d5240183907c598.zip
gdb-d51b88d344bee97bcc464c442d5240183907c598.tar.gz
gdb-d51b88d344bee97bcc464c442d5240183907c598.tar.bz2
* m32c-desc.c: Regenerate.
* mep-desc.c: Regenerate.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/m32c-desc.c2
-rw-r--r--opcodes/mep-desc.c2
3 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c8f9195..715cea5 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2009-11-03 Doug Evans <dje@sebabeach.org>
+
+ * m32c-desc.c: Regenerate.
+ * mep-desc.c: Regenerate.
+
2009-11-02 Paul Brook <paul@codesourcery.com>
* arm-dis.c (coprocessor_opcodes): Update to use new feature flags.
diff --git a/opcodes/m32c-desc.c b/opcodes/m32c-desc.c
index d69929b..39d3b13 100644
--- a/opcodes/m32c-desc.c
+++ b/opcodes/m32c-desc.c
@@ -1180,7 +1180,7 @@ const CGEN_OPERAND m32c_cgen_operand_table[] =
/* pc: program counter */
{ "pc", M32C_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_NIL] } },
- { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { RL_TYPE_NONE, 0 } } } } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { RL_TYPE_NONE, 0 } } } } },
/* Src16RnQI: general register QI view */
{ "Src16RnQI", M32C_OPERAND_SRC16RNQI, HW_H_GR_QI, 10, 2,
{ 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
diff --git a/opcodes/mep-desc.c b/opcodes/mep-desc.c
index e56194e..7d938a4 100644
--- a/opcodes/mep-desc.c
+++ b/opcodes/mep-desc.c
@@ -897,7 +897,7 @@ const CGEN_OPERAND mep_cgen_operand_table[] =
/* pc: program counter */
{ "pc", MEP_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_NIL] } },
- { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* r0: register 0 */
{ "r0", MEP_OPERAND_R0, HW_H_GPR, 0, 0,
{ 0, { (const PTR) 0 } },