[ARC] Fix assembler relaxation.

Fix assembler relaxation step for add, ld, mov, mpy and sub
instructions. Add tests to it.

gas/
2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/tc-arc.c (md_convert_frag): Remove @pcl relocation
	information from input expression.
	(assemble_insn): Make sure pcrel is correctly set.
	(arc_pcrel_adjust): Compensate for PCL rounding.
	* testsuite/gas/arc/relax-add01.d: New file.
	* testsuite/gas/arc/relax-add01.s: Likewise.
	* testsuite/gas/arc/relax-add02.d: Likewise.
	* testsuite/gas/arc/relax-add02.s: Likewise.
	* testsuite/gas/arc/relax-add03.d: Likewise.
	* testsuite/gas/arc/relax-add03.s: Likewise.
	* testsuite/gas/arc/relax-add04.d: Likewise.
	* testsuite/gas/arc/relax-add04.s: Likewise.
	* testsuite/gas/arc/relax-ld01.d: Likewise.
	* testsuite/gas/arc/relax-ld01.s: Likewise.
	* testsuite/gas/arc/relax-ld02.d: Likewise.
	* testsuite/gas/arc/relax-ld02.s: Likewise.
	* testsuite/gas/arc/relax-mov01.d: Likewise.
	* testsuite/gas/arc/relax-mov01.s: Likewise.
	* testsuite/gas/arc/relax-mov02.d: Likewise.
	* testsuite/gas/arc/relax-mov02.s: Likewise.
	* testsuite/gas/arc/relax-mpy01.d: Likewise.
	* testsuite/gas/arc/relax-mpy01.s: Likewise.
	* testsuite/gas/arc/relax-sub01.d: Likewise.
	* testsuite/gas/arc/relax-sub01.s: Likewise.
	* testsuite/gas/arc/relax-sub02.d: Likewise.
	* testsuite/gas/arc/relax-sub02.s: Likewise.
	* testsuite/gas/arc/relax-sub03.d: Likewise.
	* testsuite/gas/arc/relax-sub03.s: Likewise.
	* testsuite/gas/arc/relax-sub04.d: Likewise.
	* testsuite/gas/arc/relax-sub04.s: Likewise.

opcodes/
2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (UIMM6_20R): Define.
	(SIMM12_20): Use above.
	(SIMM12_20R): Define.
	(SIMM3_5_S): Use above.
	(UIMM7_A32_11R_S): Define.
	(UIMM7_9_S): Use above.
	(UIMM3_13R_S): Define.
	(SIMM11_A32_7_S): Use above.
	(SIMM9_8R): Define.
	(UIMM10_A32_8_S): Use above.
	(UIMM8_8R_S): Define.
	(W6): Use above.
	(arc_relax_opcodes): Use all above defines.

2 files changed, 75 insertions, 34 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index cff458a..1bb7b42 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,19 @@
+2017-02-15  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* arc-opc.c (UIMM6_20R): Define.
+	(SIMM12_20): Use above.
+	(SIMM12_20R): Define.
+	(SIMM3_5_S): Use above.
+	(UIMM7_A32_11R_S): Define.
+	(UIMM7_9_S): Use above.
+	(UIMM3_13R_S): Define.
+	(SIMM11_A32_7_S): Use above.
+	(SIMM9_8R): Define.
+	(UIMM10_A32_8_S): Use above.
+	(UIMM8_8R_S): Define.
+	(W6): Use above.
+	(arc_relax_opcodes): Use all above defines.
+
 2017-02-15  Vineet Gupta <vgupta@synopsys.com>
 
 	* arc-regs.h: Distinguish some of the registers different on
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index 295d92f..2d72b12 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -1727,12 +1727,22 @@ const struct arc_operand arc_operands[] =
 #define UIMM6_20       (FKT_NT + 1)
   {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
 
+  /* Exactly like the above but used by relaxation.  */
+#define UIMM6_20R      (UIMM6_20 + 1)
+  {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
+   insert_uimm6_20, extract_uimm6_20},
+
   /* SIMM12_20 mask = 00000000000000000000111111222222.  */
-#define SIMM12_20	(UIMM6_20 + 1)
+#define SIMM12_20	(UIMM6_20R + 1)
   {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
 
+  /* Exactly like the above but used by relaxation.  */
+#define SIMM12_20R	(SIMM12_20 + 1)
+  {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,
+   insert_simm12_20, extract_simm12_20},
+
   /* SIMM3_5_S mask = 0000011100000000.  */
-#define SIMM3_5_S	(SIMM12_20 + 1)
+#define SIMM3_5_S	(SIMM12_20R + 1)
   {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
    insert_simm3s, extract_simm3s},
 
@@ -1742,16 +1752,27 @@ const struct arc_operand arc_operands[] =
    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
    extract_uimm7_a32_11_s},
 
+  /* The same as above but used by relaxation.  */
+#define UIMM7_A32_11R_S	     (UIMM7_A32_11_S + 1)
+  {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
+   | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL,
+   insert_uimm7_a32_11_s, extract_uimm7_a32_11_s},
+
   /* UIMM7_9_S mask = 0000000001111111.  */
-#define UIMM7_9_S	(UIMM7_A32_11_S + 1)
+#define UIMM7_9_S	(UIMM7_A32_11R_S + 1)
   {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
 
   /* UIMM3_13_S mask = 0000000000000111.  */
 #define UIMM3_13_S	 (UIMM7_9_S + 1)
   {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
 
+  /* Exactly like the above but used for relaxation.  */
+#define UIMM3_13R_S	 (UIMM3_13_S + 1)
+  {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
+   insert_uimm3_13_s, extract_uimm3_13_s},
+
   /* SIMM11_A32_7_S mask = 0000000111111111.  */
-#define SIMM11_A32_7_S	     (UIMM3_13_S + 1)
+#define SIMM11_A32_7_S	     (UIMM3_13R_S + 1)
   {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
    | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
 
@@ -1842,8 +1863,13 @@ const struct arc_operand arc_operands[] =
   {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
    insert_simm9_8, extract_simm9_8},
 
+  /* The same as above but used by relaxation.  */
+#define SIMM9_8R      (SIMM9_8 + 1)
+  {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE
+   | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8},
+
   /* UIMM10_A32_8_S mask = 0000000011111111.  */
-#define UIMM10_A32_8_S	     (SIMM9_8 + 1)
+#define UIMM10_A32_8_S	     (SIMM9_8R + 1)
   {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
    | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
    extract_uimm10_a32_8_s},
@@ -1899,8 +1925,13 @@ const struct arc_operand arc_operands[] =
 #define UIMM8_8_S	(SIMM13_A16_20 + 1)
   {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
 
+  /* The same as above but used for relaxation.  */
+#define UIMM8_8R_S	(UIMM8_8_S + 1)
+  {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
+   insert_uimm8_8_s, extract_uimm8_8_s},
+
   /* W6 mask = 00000000000000000000111111000000.  */
-#define W6	 (UIMM8_8_S + 1)
+#define W6	 (UIMM8_8R_S + 1)
   {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
 
   /* UIMM6_5_S mask = 0000011111100000.  */
@@ -2485,32 +2516,31 @@ const struct arc_opcode arc_relax_opcodes[] =
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
     { SIMM25_A16_5 }, { C_D }},
 
-  /* add_s c,b,u3 01101bbbccc00uuu.  Wants UIMM3_13_S_PCREL.  */
+  /* add_s c,b,u3 01101bbbccc00uuu.  */
   { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
-    { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+    { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
 
-  /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA.  Wants
-     UIMM6_20_PCREL.  */
+  /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA.  */
   { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
-    { RA, RB, UIMM6_20 }, { C_F }},
+    { RA, RB, UIMM6_20R }, { C_F }},
 
   /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA.  */
   { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
     { RA, RB, LIMM }, { C_F }},
 
-  /* ld_s c,b,u7 10000bbbcccuuuuu.  Wants UIMM7_A32_11_S_PCREL.  */
+  /* ld_s c,b,u7 10000bbbcccuuuuu.  */
   { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
-    { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+    { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }},
 
   /* ld<.di><.aa><.x><zz> a,b,s9
-     00010bbbssssssssSBBBDaaZZXAAAAAA.  Wants SIMM9_8_PCREL.  */
+     00010bbbssssssssSBBBDaaZZXAAAAAA.  */
   { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
-    { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
+    { RA, BRAKET, RB, SIMM9_8R, BRAKETdup },
     { C_ZZ23, C_DI20, C_AA21, C_X25 }},
 
   /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA.  */
@@ -2519,63 +2549,58 @@ const struct arc_opcode arc_relax_opcodes[] =
     { RA, BRAKET, RB, LIMM, BRAKETdup },
     { C_ZZ13, C_DI16, C_AA8, C_X15 }},
 
-  /* mov_s b,u8 11011bbbuuuuuuuu.  Wants UIMM8_8_S_PCREL.  */
+  /* mov_s b,u8 11011bbbuuuuuuuu.  */
   { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
-    { RB_S, UIMM8_8_S }, { 0 }},
+    { RB_S, UIMM8_8R_S }, { 0 }},
 
-  /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS.  Wants
-     SIMM12_20_PCREL.  */
+  /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS.  */
   { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
-    { RB, SIMM12_20 }, { C_F }},
+    { RB, SIMM12_20R }, { C_F }},
 
   /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR.  */
   { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
     { RB, LIMM }, { C_F }},
 
-  /* sub_s c,b,u3 01101bbbccc01uuu.  UIMM3_13_S_PCREL.  */
+  /* sub_s c,b,u3 01101bbbccc01uuu.  */
   { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
-    { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+    { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
 
-  /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
-     UIMM6_20_PCREL.  */
+  /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.  */
   { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
-    { RA, RB, UIMM6_20 }, { C_F }},
+    { RA, RB, UIMM6_20R }, { C_F }},
 
   /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA.  */
   { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
     { RA, RB, LIMM }, { C_F }},
 
-  /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
-     UIMM6_20_PCREL.  */
+  /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.  */
   { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
-    | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
+    | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }},
 
   /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA.  */
   { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
     | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
 
-  /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
-     UIMM6_20_PCREL.  */
+  /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.  */
   { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
-    { RB, UIMM6_20 }, { C_F, C_CC }},
+    { RB, UIMM6_20R }, { C_F, C_CC }},
 
   /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ.  */
   { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
     { RB, LIMM }, { C_F, C_CC }},
 
-  /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
-     UIMM6_20_PCREL.  */
+  /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.  */
   { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
     | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
-    { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+    { RB, RBdup, UIMM6_20R }, { C_F, C_CC }},
 
   /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ.  */
   { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700