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| author | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2017-01-18 17:08:34 +0000 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2017-01-18 17:08:34 +0000 |
| commit | c13a63b04677906020ee72a28d5869d979e36a6f (patch) | |
| tree | f7226c7bf6fab48fe431804570effeead9956d01 /opcodes | |
| parent | d1dff2266d29c4739aee6f68c8c587d44b03a717 (diff) | |
| download | gdb-c13a63b04677906020ee72a28d5869d979e36a6f.zip gdb-c13a63b04677906020ee72a28d5869d979e36a6f.tar.gz gdb-c13a63b04677906020ee72a28d5869d979e36a6f.tar.bz2 | |
[ARM] Fix the decoding of indexed element VCMLA instruction
Bit 24 of the indexed element vcmla decode mask was incorrectly
left unset. This could cause incorrect disassembly of some
currently undefined instructions as vcmla.
Rotatation immediates were not printed correctly in the disassembly
(could print 170 and 280 instead of 180 and 270).
opcodes/
* arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
gas/
* testsuite/gas/arm/armv8_3-a-simd.s: Add vcmla tests.
* testsuite/gas/arm/armv8_3-a-simd.d: Update.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 8 |
2 files changed, 8 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index d4f35bd..5a98859 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com> + + * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly. + 2017-01-13 Yao Qi <yao.qi@linaro.org> * m68k-dis.c (match_insn_m68k): Extend comments. Return -1 diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 167c668..2987403 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -897,13 +897,13 @@ static const struct opcode32 coprocessor_opcodes[] = {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"}, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfe000800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"}, + 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"}, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfe200800, 0xfea00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%23?780"}, + 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"}, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfe800800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"}, + 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"}, {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A), - 0xfea00800, 0xfea00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%23?780"}, + 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"}, /* V5 coprocessor instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), |