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| author | Philipp Tomsich <prt@gnu.org> | 2021-01-07 15:53:25 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2021-01-07 16:45:43 +0800 |
| commit | aa881ecde48c7a0224b92e2cfa43b37ee9ec9fa2 (patch) | |
| tree | 1b0e0814c4a7ed9567d8d49aad19de327ea78682 /opcodes | |
| parent | 4d4490b8d772321e9634541b81be25095a5a06ef (diff) | |
| download | gdb-aa881ecde48c7a0224b92e2cfa43b37ee9ec9fa2.zip gdb-aa881ecde48c7a0224b92e2cfa43b37ee9ec9fa2.tar.gz gdb-aa881ecde48c7a0224b92e2cfa43b37ee9ec9fa2.tar.bz2 | |
RISC-V: Add pause hint instruction.
Add support for the pause hint instruction, as specified in the
Zihintpause extension. The pause instruction is encoded as a
special form of a memory fence (which is available as part of the
base instruction set). The chosen encoding does not mandate any
particular memory ordering and therefore is a true hint.
bfd/
* elfxx-riscv.c (riscv_std_z_ext_strtab): Added zihintpause.
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Added
INSN_CLASS_ZIHINTPAUSE.
* testsuite/gas/riscv/pause.d: New testcase. Adding coverage for
the pause hint instruction.
* testsuite/gas/riscv/pause.s: Likewise.
include/
* opcode/riscv-opc.h: Added MATCH_PAUSE, MASK_PAUSE and DECLARE_INSN
for pause hint instruction.
* opcode/riscv.h (enum riscv_insn_class): Added INSN_CLASS_ZIHINTPAUSE.
opcodes/
* riscv-opc.c (riscv_opcodes): Add pause hint instruction.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 4 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 3 |
2 files changed, 7 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4f4e54e..2add0e7 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,7 @@ +2021-01-07 Philipp Tomsich <prt@gnu.org> + + * riscv-opc.c (riscv_opcodes): Add pause hint instruction. + 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com> Jim Wilson <jimw@sifive.com> Andrew Waterman <andrew@sifive.com> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index cb980f2..7c262dd 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -345,6 +345,7 @@ const struct riscv_opcode riscv_opcodes[] = {"sw", 0, INSN_CLASS_C, "Ct,Ck(Cs)", MATCH_C_SW, MASK_C_SW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"sw", 0, INSN_CLASS_I, "t,q(s)", MATCH_SW, MASK_SW, match_opcode, INSN_DREF|INSN_4_BYTE }, {"sw", 0, INSN_CLASS_I, "t,A,s", 0, (int) M_SW, match_never, INSN_MACRO }, +{"pause", 0, INSN_CLASS_ZIHINTPAUSE, "", MATCH_PAUSE, MASK_PAUSE, match_opcode, 0 }, {"fence", 0, INSN_CLASS_I, "", MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS }, {"fence", 0, INSN_CLASS_I, "P,Q", MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 }, {"fence.i", 0, INSN_CLASS_ZIFENCEI, "", MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 }, @@ -977,6 +978,8 @@ const struct riscv_ext_version riscv_ext_version_table[] = {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0}, {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0}, +{"zihintpause", ISA_SPEC_CLASS_DRAFT, 1, 0}, + {"zba", ISA_SPEC_CLASS_DRAFT, 0, 93}, {"zbb", ISA_SPEC_CLASS_DRAFT, 0, 93}, {"zbc", ISA_SPEC_CLASS_DRAFT, 0, 93}, |