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| author | Matthew Fortune <matthew.fortune@imgtec.com> | 2014-11-26 11:15:01 +0000 |
|---|---|---|
| committer | Matthew Fortune <matthew.fortune@imgtec.com> | 2016-05-11 17:06:13 +0100 |
| commit | 8f4f9071ad5fe6076c3554a75d59536e74e6a3fe (patch) | |
| tree | 858141fe81e243719690d3e6674945869db441b2 /opcodes | |
| parent | a464198b013940745d43cff029330b9e7dda71c2 (diff) | |
| download | gdb-8f4f9071ad5fe6076c3554a75d59536e74e6a3fe.zip gdb-8f4f9071ad5fe6076c3554a75d59536e74e6a3fe.tar.gz gdb-8f4f9071ad5fe6076c3554a75d59536e74e6a3fe.tar.bz2 | |
Add MIPS32 DSPr3 support.
bfd/
* elfxx-mips.c (print_mips_ases): Add DSPR3.
binutils/
* readelf.c (print_mips_ases): Add DSPR3.
gas/
* config/tc-mips.c (options): Add OPTION_DSPR3 and
OPTION_NO_DSPR3.
(md_longopts): Likewise.
(md_show_usage): Add help for -mdspr3 and -mno-dspr3.
(mips_ases): Define availability for DSPr3.
(mips_ase_groups): Add ASE_DSPR3 to the DSP group.
(mips_convert_ase_flags): Map ASE_DSPR3 to AFL_ASE_DSPR3.
* doc/as.texinfo: Document -mdspr3, -mno-dspr3. Fix -mdspr2
formatting.
* doc/c-mips.texi: Document -mdspr3, -mno-dspr3, .set dspr3 and
.set nodspr3. Fix -mdspr2 formatting.
* testsuite/gas/mips/mips32-dspr3.d: New file.
* testsuite/gas/mips/mips32-dspr3.s: Likewise.
* testsuite/gas/mips/mips.exp: Run mips32-dspr3 test.
include/
* elf/mips.h (AFL_ASE_DSPR3): New macro.
(AFL_ASE_MASK): Update to include AFL_ASE_DSPR3.
* opcode/mips.h (ASE_DSPR3): New macro.
opcodes/
* mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
mips64r6.
* mips-opc.c (D34): New macro.
(mips_builtin_opcodes): Define bposge32c for DSPr3.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 7 | ||||
| -rw-r--r-- | opcodes/mips-dis.c | 4 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 2 |
3 files changed, 11 insertions, 2 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 89ea01a..da823ac 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com> + + * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and + mips64r6. + * mips-opc.c (D34): New macro. + (mips_builtin_opcodes): Define bposge32c for DSPr3. + 2016-05-10 Alexander Fomin <alexander.fomin@intel.com> * i386-dis.c (prefix_table): Add RDPID instruction. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 7822295..535c14a 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -563,7 +563,7 @@ const struct mips_arch_choice mips_arch_choices[] = { "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6, ISA_MIPS32R6, (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP - | ASE_DSPR2), + | ASE_DSPR2 | ASE_DSPR3), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, @@ -602,7 +602,7 @@ const struct mips_arch_choice mips_arch_choices[] = { "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6, ISA_MIPS64R6, (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64 - | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2), + | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 79a8417..a95eff1 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -374,6 +374,7 @@ decode_mips_operand (const char *p) #define DSP_VOLA INSN_NO_DELAY_SLOT #define D32 ASE_DSP #define D33 ASE_DSPR2 +#define D34 ASE_DSPR3 #define D64 ASE_DSP64 /* MIPS MT ASE support. */ @@ -2149,6 +2150,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 }, {"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_1|RD_2, 0, 0, D32, 0 }, {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, 0, D32, 0 }, +{"bposge32c", "p", 0x04180000, 0xffff0000, NODS, FS, 0, D34, 0 }, {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, 0, D64, 0 }, {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 }, {"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_1|RD_2, 0, 0, D64, 0 }, |