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author | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:51:30 +0100 |
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committer | Richard Sandiford <richard.sandiford@arm.com> | 2016-09-21 16:51:30 +0100 |
commit | 8a7f0c1b5ae35d041886855ac7ca9b9533e8788a (patch) | |
tree | a5fd8f6ab0456658d89c30c129b065be1898c4e8 /opcodes | |
parent | aa2aa4c69429444836821a92cb99396d02dcb996 (diff) | |
download | gdb-8a7f0c1b5ae35d041886855ac7ca9b9533e8788a.zip gdb-8a7f0c1b5ae35d041886855ac7ca9b9533e8788a.tar.gz gdb-8a7f0c1b5ae35d041886855ac7ca9b9533e8788a.tar.bz2 |
[AArch64][SVE 17/32] Add a prefix parameter to print_register_list
This patch generalises the interface to print_register_list so
that it can print register lists involving SVE z registers as
well as AdvSIMD v ones.
opcodes/
* aarch64-opc.c (print_register_list): Add a prefix parameter.
(aarch64_print_operand): Update accordingly.
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/ChangeLog | 5 | ||||
-rw-r--r-- | opcodes/aarch64-opc.c | 29 |
2 files changed, 21 insertions, 13 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 672c1b5..9a5cafb 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * aarch64-opc.c (print_register_list): Add a prefix parameter. + (aarch64_print_operand): Update accordingly. + +2016-09-21 Richard Sandiford <richard.sandiford@arm.com> + * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm for FPIMM. * aarch64-asm.h (ins_fpimm): New inserter. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 84da821..6eac70a 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -2261,9 +2261,11 @@ expand_fp_imm (int size, uint32_t imm8) } /* Produce the string representation of the register list operand *OPND - in the buffer pointed by BUF of size SIZE. */ + in the buffer pointed by BUF of size SIZE. PREFIX is the part of + the register name that comes before the register number, such as "v". */ static void -print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd) +print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd, + const char *prefix) { const int num_regs = opnd->reglist.num_regs; const int first_reg = opnd->reglist.first_regno; @@ -2284,8 +2286,8 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd) more than two registers in the list, and the register numbers are monotonically increasing in increments of one. */ if (num_regs > 2 && last_reg > first_reg) - snprintf (buf, size, "{v%d.%s-v%d.%s}%s", first_reg, qlf_name, - last_reg, qlf_name, tb); + snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name, + prefix, last_reg, qlf_name, tb); else { const int reg0 = first_reg; @@ -2296,20 +2298,21 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd) switch (num_regs) { case 1: - snprintf (buf, size, "{v%d.%s}%s", reg0, qlf_name, tb); + snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb); break; case 2: - snprintf (buf, size, "{v%d.%s, v%d.%s}%s", reg0, qlf_name, - reg1, qlf_name, tb); + snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name, + prefix, reg1, qlf_name, tb); break; case 3: - snprintf (buf, size, "{v%d.%s, v%d.%s, v%d.%s}%s", reg0, qlf_name, - reg1, qlf_name, reg2, qlf_name, tb); + snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s", + prefix, reg0, qlf_name, prefix, reg1, qlf_name, + prefix, reg2, qlf_name, tb); break; case 4: - snprintf (buf, size, "{v%d.%s, v%d.%s, v%d.%s, v%d.%s}%s", - reg0, qlf_name, reg1, qlf_name, reg2, qlf_name, - reg3, qlf_name, tb); + snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s", + prefix, reg0, qlf_name, prefix, reg1, qlf_name, + prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb); break; } } @@ -2513,7 +2516,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_LVt: case AARCH64_OPND_LVt_AL: case AARCH64_OPND_LEt: - print_register_list (buf, size, opnd); + print_register_list (buf, size, opnd, "v"); break; case AARCH64_OPND_Cn: |