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author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-01-15 09:35:55 +0000 |
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committer | Nick Clifton <nickc@redhat.com> | 2024-01-15 11:45:41 +0000 |
commit | 88601c2d941b004b443dc4bfdf3b93ea1983d136 (patch) | |
tree | d2ed31930c0f82a30e5090f3a1b70e3a8f3ca681 /opcodes | |
parent | 89e06ec1521898892e27615714f51d30703d5139 (diff) | |
download | gdb-88601c2d941b004b443dc4bfdf3b93ea1983d136.zip gdb-88601c2d941b004b443dc4bfdf3b93ea1983d136.tar.gz gdb-88601c2d941b004b443dc4bfdf3b93ea1983d136.tar.bz2 |
aarch64: Add support for FEAT_SVE2p1.
Hi,
This patch add support for FEAT_SVE2p1 (SVE2.1 Extension) feature
along with +sve2p1 optional flag to enabe this feature.
Also support for following SVE2p1 instructions is added
addqv, andqv, smaxqv, sminqv, umaxqv, uminqv and uminqv.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/aarch64-asm.c | 14 | ||||
-rw-r--r-- | opcodes/aarch64-dis.c | 10 | ||||
-rw-r--r-- | opcodes/aarch64-tbl.h | 29 |
3 files changed, 53 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 3fac127..1dfd59d 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1981,6 +1981,20 @@ do_special_encoding (struct aarch64_inst *inst) gen_sub_field (FLD_imm5, 0, num + 1, &field); insert_field_2 (&field, &inst->value, 1 << num, inst->opcode->mask); } + + if ((inst->opcode->flags & F_OPD_SIZE) && inst->opcode->iclass == sve2_urqvs) + { + enum aarch64_opnd_qualifier qualifier[1]; + aarch64_insn value1 = 0; + idx = 0; + qualifier[0] = inst->operands[idx].qualifier; + qualifier[1] = inst->operands[idx+2].qualifier; + value = aarch64_get_qualifier_standard_value (qualifier[0]); + value1 = aarch64_get_qualifier_standard_value (qualifier[1]); + assert ((value >> 1) == value1); + insert_field (FLD_size, &inst->value, value1, inst->opcode->mask); + } + if (inst->opcode->flags & F_GPRSIZE_IN_Q) { /* Use Rt to encode in the case of e.g. diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index a14b2ca..d395438 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -2609,6 +2609,16 @@ do_special_decoding (aarch64_inst *inst) get_vreg_qualifier_from_value ((num << 1) | Q); } + if ((inst->opcode->flags & F_OPD_SIZE) && inst->opcode->iclass == sve2_urqvs) + { + unsigned size; + size = (unsigned) extract_field (FLD_size, inst->value, + inst->opcode->mask); + inst->operands[0].qualifier + = get_vreg_qualifier_from_value (1 + (size << 1)); + inst->operands[2].qualifier = get_sreg_qualifier_from_value (size); + } + if (inst->opcode->flags & F_GPRSIZE_IN_Q) { /* Use Rt to encode in the case of e.g. diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 9c7648b..f433257 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1487,6 +1487,10 @@ - P: the operand has a /[ZM] suffix and the choice of suffix is not the same for all variants. + - v: the operand has a V_[16B|8H|4S|2D] qualifier and the choice of + qualifier suffix is not the same for all variants. This is used for + the same kinds of operands as [BHSD] above. + The _<sizes>, if present, give the subset of [BHSD] that are accepted by the V entries in <operands>. */ #define OP_SVE_B \ @@ -1911,6 +1915,13 @@ QLF3(S_S,S_H,NIL), \ QLF3(S_D,S_S,NIL), \ } +#define OP_SVE_vUS_BHSD_BHSD \ +{ \ + QLF3(V_16B,NIL,S_B), \ + QLF3(V_8H,NIL,S_H), \ + QLF3(V_4S,NIL,S_S), \ + QLF3(V_2D,NIL,S_D), \ +} #define OP_SVE_VMV_SD \ { \ QLF3(S_S,P_M,S_S), \ @@ -2620,6 +2631,8 @@ static const aarch64_feature_set aarch64_feature_b16b16 = AARCH64_FEATURE (B16B16); static const aarch64_feature_set aarch64_feature_sme2p1 = AARCH64_FEATURE (SME2p1); +static const aarch64_feature_set aarch64_feature_sve2p1 = + AARCH64_FEATURE (SVE2p1); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2684,6 +2697,7 @@ static const aarch64_feature_set aarch64_feature_sme2p1 = #define D128_THE &aarch64_feature_d128_the #define B16B16 &aarch64_feature_b16b16 #define SME2p1 &aarch64_feature_sme2p1 +#define SVE2p1 &aarch64_feature_sve2p1 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2762,6 +2776,12 @@ static const aarch64_feature_set aarch64_feature_sme2p1 = #define B16B16_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, B16B16, OPS, QUALS, \ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } +#define SVE2p1_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \ + FLAGS | F_STRICT, 0, TIED, NULL } +#define SVE2p1_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SVE2p1, OPS, QUALS, \ + FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \ FLAGS | F_STRICT, 0, TIED, NULL } @@ -6309,6 +6329,15 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2p1_INSN ("movaz", 0xc0460200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsh_1), OP_SVE_HH, 0, 0), SME2p1_INSN ("movaz", 0xc0860200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrss_1), OP_SVE_SS, 0, 0), SME2p1_INSN ("movaz", 0xc0c60200, 0xffff1f01, sme2_movaz, 0, OP2 (SME_Zdnx2, SME_ZA_array_vrsd_1), OP_SVE_DD, 0, 0), + +/* SVE2p1 Instructions. */ + SVE2p1_INSNC("addqv",0x04052000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("andqv",0x041e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("smaxqv",0x040c2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("sminqv",0x040e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("umaxqv",0x040d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("uminqv",0x040f2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; |