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authorJan Beulich <jbeulich@suse.com>2022-05-27 08:45:56 +0200
committerJan Beulich <jbeulich@suse.com>2022-05-27 08:45:56 +0200
commit811f61d4c453934b765c73bde78fc29ea22c0c7d (patch)
tree2ce5662a5ae5fb9d95115aa71584087e274f8eaa /opcodes
parent2a2cb7cf2c7f0d380ee9cb9ef361223b8770c508 (diff)
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x86/Intel: adjust representation of embedded broadcast
MASM doesn't support the {1to<n>} form; DWORD BCST (paralleling DWORD PTR) and alike are to be used there instead. Make the disassembler follow this first, before also adjusting the assembler (such that it'll be easy to see that the assembler change doesn't alter generated code). For VFPCLASSP{S,D,H} and vector conversions with shrinking element sizes the original {1to<n>} operand suffix is retained, to disambiguate output. I have no insight (yet) into how MASM expects those to be disambiguated.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/i386-dis.c15
1 files changed, 11 insertions, 4 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 608bddc..5f887f2 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -267,6 +267,7 @@ struct instr_info
#define EVEX_b_used 1
+#define EVEX_len_used 2
/* Flags stored in PREFIXES. */
#define PREFIX_REPZ 1
@@ -10931,14 +10932,14 @@ intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
case x_mode:
case evex_half_bcst_xmmq_mode:
if (ins->vex.w)
- oappend (ins, "QWORD PTR ");
+ oappend (ins, "QWORD BCST ");
else
- oappend (ins, "DWORD PTR ");
+ oappend (ins, "DWORD BCST ");
break;
case xh_mode:
case evex_half_bcst_xmmqh_mode:
case evex_half_bcst_xmmqdh_mode:
- oappend (ins, "WORD PTR ");
+ oappend (ins, "WORD BCST ");
break;
default:
ins->vex.no_broadcast = true;
@@ -11768,7 +11769,8 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
if (ins->obufp == ins->op_out[0])
ins->vex.no_broadcast = true;
- if (!ins->vex.no_broadcast)
+ if (!ins->vex.no_broadcast
+ && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
{
if (bytemode == xh_mode)
{
@@ -12484,6 +12486,7 @@ print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
break;
case 512:
names = att_names_ymm;
+ ins->evex_used |= EVEX_len_used;
break;
default:
abort ();
@@ -12512,6 +12515,7 @@ print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
&& bytemode != d_mode
&& bytemode != q_mode)
{
+ ins->evex_used |= EVEX_len_used;
switch (ins->vex.length)
{
case 128:
@@ -13237,6 +13241,7 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
case x_mode:
names = att_names_xmm;
+ ins->evex_used |= EVEX_len_used;
break;
case dq_mode:
if (ins->rex & REX_W)
@@ -13263,6 +13268,7 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
case x_mode:
names = att_names_ymm;
+ ins->evex_used |= EVEX_len_used;
break;
case mask_bd_mode:
case mask_mode:
@@ -13281,6 +13287,7 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
break;
case 512:
names = att_names_zmm;
+ ins->evex_used |= EVEX_len_used;
break;
default:
abort ();