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| author | Alan Modra <amodra@gmail.com> | 2017-02-14 20:38:21 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2017-02-14 21:12:07 +1030 |
| commit | 7e0de605cbacbbbb2531bb70506c0843aea13111 (patch) | |
| tree | 70e16baeeedac264df23c6d884e95743dcbc570f /opcodes | |
| parent | 606a935e3a9066ab11308b8c934c9bdec7f128d3 (diff) | |
| download | gdb-7e0de605cbacbbbb2531bb70506c0843aea13111.zip gdb-7e0de605cbacbbbb2531bb70506c0843aea13111.tar.gz gdb-7e0de605cbacbbbb2531bb70506c0843aea13111.tar.bz2 | |
PowerPC register expression checks
This stops powerpc gas blithely accepting such nonsense as
"addi %f4,%cr3,%r31".
PR 21118
gas/
* NEWS: Mention powerpc register checks.
* config/tc-ppc.c (struct pd_reg): Make value a short. Add flags.
(pre_defined_registers): Delete fpscr and pmr entries. Set
register type in flags.
(cr_names): Set type in flags.
(reg_name_search): Return pointer to struct pd_reg rather than value.
(register_name): Adjust to suit. Set X_md from flags.
(ppc_parse_name): Likewise.
(ppc_optimize_expr): New function.
(md_assemble): Verify expresion reg flags match operand.
* config/tc-ppc.h (md_optimize_expr): Define.
(ppc_optimize_expr): Declare.
include/
* opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
(PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
opcodes/
* ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/ppc-opc.c | 10 |
2 files changed, 11 insertions, 5 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index fc6637b..eafd7d2 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2017-02-14 Alan Modra <amodra@gmail.com> + + PR 21118 + * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries + with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR. + 2017-02-11 Stafford Horne <shorne@gmail.com> Alan Modra <amodra@gmail.com> diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 9ac779c..68d978b 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -667,7 +667,7 @@ const struct powerpc_operand powerpc_operands[] = #define PMR SPR #define TMR SPR #define SPR_MASK (0x3ff << 11) - { 0x3ff, 11, insert_spr, extract_spr, 0 }, + { 0x3ff, 11, insert_spr, extract_spr, PPC_OPERAND_SPR }, /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ #define SPRBAT SPR + 1 @@ -676,7 +676,7 @@ const struct powerpc_operand powerpc_operands[] = /* The SPRG register number in an XFX form m[ft]sprg instruction. */ #define SPRG SPRBAT + 1 - { 0x1f, 16, insert_sprg, extract_sprg, 0 }, + { 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR }, /* The SR field in an X form instruction. */ #define SR SPRG + 1 @@ -704,7 +704,7 @@ const struct powerpc_operand powerpc_operands[] = field, but it is optional. */ #define TBR SV + 1 { 0x3ff, 11, insert_tbr, extract_tbr, - PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, + PPC_OPERAND_SPR | PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL_VALUE}, /* If the TBR operand is ommitted, use the value 268. */ { -1, 268, NULL, NULL, 0}, @@ -806,11 +806,11 @@ const struct powerpc_operand powerpc_operands[] = /* IDX bits for quantization in the pair singles instructions. */ #define PSQ PSWM + 1 - { 0x7, 12, 0, 0, 0 }, + { 0x7, 12, 0, 0, PPC_OPERAND_GQR }, /* IDX bits for quantization in the pair singles x-type instructions. */ #define PSQM PSQ + 1 - { 0x7, 7, 0, 0, 0 }, + { 0x7, 7, 0, 0, PPC_OPERAND_GQR }, /* Smaller D field for quantization in the pair singles instructions. */ #define PSD PSQM + 1 |