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| author | Richard Sandiford <richard.sandiford@arm.com> | 2017-02-15 16:54:21 +0000 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2017-02-15 16:54:21 +0000 |
| commit | 773fb663445646ebe45298e255d263f9520b2e2e (patch) | |
| tree | 5fe4c3e1d8f6f8ea65885da0fc6dd841b483e865 /opcodes | |
| parent | 7a2114e7a4ee1fbb5a0611733c72a2a7acc733c7 (diff) | |
| download | gdb-773fb663445646ebe45298e255d263f9520b2e2e.zip gdb-773fb663445646ebe45298e255d263f9520b2e2e.tar.gz gdb-773fb663445646ebe45298e255d263f9520b2e2e.tar.bz2 | |
[AArch64] Add SVE system registers
This patch adds the SVE-specific system registers.
opcodes/
* aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
(aarch64_sys_reg_supported_p): Handle them.
gas/
* testsuite/gas/aarch64/sve-sysreg.s,
testsuite/gas/aarch64/sve-sysreg.d,
testsuite/gas/aarch64/sve-sysreg-invalid.d,
testsuite/gas/aarch64/sve-sysreg-invalid.l: New tests.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 16 |
2 files changed, 21 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1bb7b42..4e58d6c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2017-02-15 Richard Sandiford <richard.sandiford@arm.com> + + * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. + (aarch64_sys_reg_supported_p): Handle them. + 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> * arc-opc.c (UIMM6_20R): Define. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 314bcb4..dac6159 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3670,6 +3670,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT }, /* RO */ { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), 0 }, /* RO */ { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), 0 }, /* RO */ + { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT }, /* RO */ { "clidr_el1", CPENC(3,1,C0,C0,1), 0 }, /* RO */ { "csselr_el1", CPENC(3,2,C0,C0,0), 0 }, /* RO */ { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 }, @@ -3691,6 +3692,11 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "mdcr_el3", CPENC(3,6,C1,C3,1), 0 }, { "hstr_el2", CPENC(3,4,C1,C1,3), 0 }, { "hacr_el2", CPENC(3,4,C1,C1,7), 0 }, + { "zcr_el1", CPENC (3, 0, C1, C2, 0), F_ARCHEXT }, + { "zcr_el12", CPENC (3, 5, C1, C2, 0), F_ARCHEXT }, + { "zcr_el2", CPENC (3, 4, C1, C2, 0), F_ARCHEXT }, + { "zcr_el3", CPENC (3, 6, C1, C2, 0), F_ARCHEXT }, + { "zidr_el1", CPENC (3, 0, C0, C0, 7), F_ARCHEXT }, { "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 }, { "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 }, { "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 }, @@ -4104,6 +4110,16 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features, && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3)) return FALSE; + /* SVE. */ + if ((reg->value == CPENC (3, 0, C0, C4, 4) + || reg->value == CPENC (3, 0, C1, C2, 0) + || reg->value == CPENC (3, 4, C1, C2, 0) + || reg->value == CPENC (3, 6, C1, C2, 0) + || reg->value == CPENC (3, 5, C1, C2, 0) + || reg->value == CPENC (3, 0, C0, C0, 7)) + && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE)) + return FALSE; + return TRUE; } |