* mcore-dis.c (print_insn_mcore): Protect "fprintf" var against

	macro expansion.

2 files changed, 36 insertions, 28 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 17f7529..a12d8c9 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2007-10-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* mcore-dis.c (print_insn_mcore): Protect "fprintf" var against
+	macro expansion.
+
 2007-10-12  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* i386-gen.c (opcode_modifiers): Add FirstXmm0.
diff --git a/opcodes/mcore-dis.c b/opcodes/mcore-dis.c
index ee698ff..63f65ba 100644
--- a/opcodes/mcore-dis.c
+++ b/opcodes/mcore-dis.c
@@ -122,12 +122,12 @@ print_insn_mcore (memaddr, info)
       break;
 
   if (op->name == 0)
-    fprintf (stream, ".short 0x%04x", inst);
+    (*fprintf) (stream, ".short 0x%04x", inst);
   else
     {
       const char *name = grname[inst & 0x0F];
 
-      fprintf (stream, "%s", op->name);
+      (*fprintf) (stream, "%s", op->name);
 
       switch (op->opclass)
 	{
@@ -135,42 +135,42 @@ print_insn_mcore (memaddr, info)
 	  break;
 
 	case OT:
-	  fprintf (stream, "\t%d", inst & 0x3);
+	  (*fprintf) (stream, "\t%d", inst & 0x3);
 	  break;
 
 	case O1:
 	case JMP:
 	case JSR:
-	  fprintf (stream, "\t%s", name);
+	  (*fprintf) (stream, "\t%s", name);
 	  break;
 
 	case OC:
-	  fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]);
+	  (*fprintf) (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]);
 	  break;
 
 	case O1R1:
-	  fprintf (stream, "\t%s, r1", name);
+	  (*fprintf) (stream, "\t%s, r1", name);
 	  break;
 
 	case MULSH:
 	case O2:
-	  fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]);
+	  (*fprintf) (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]);
 	  break;
 
 	case X1:
-	  fprintf (stream, "\tr1, %s", name);
+	  (*fprintf) (stream, "\tr1, %s", name);
 	  break;
 
 	case OI:
-	  fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1);
+	  (*fprintf) (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1);
 	  break;
 
 	case RM:
-	  fprintf (stream, "\t%s-r15, (r0)", name);
+	  (*fprintf) (stream, "\t%s-r15, (r0)", name);
 	  break;
 
 	case RQ:
-	  fprintf (stream, "\tr4-r7, (%s)", name);
+	  (*fprintf) (stream, "\tr4-r7, (%s)", name);
 	  break;
 
 	case OB:
@@ -182,16 +182,16 @@ print_insn_mcore (memaddr, info)
 	case OMa:
 	case OMb:
 	case OMc:
-	  fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F);
+	  (*fprintf) (stream, "\t%s, %d", name, (inst >> 4) & 0x1F);
 	  break;
 
 	case I7:
-	  fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F);
+	  (*fprintf) (stream, "\t%s, %d", name, (inst >> 4) & 0x7F);
 	  break;
 
 	case LS:
-	  fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
-		   name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
+	  (*fprintf) (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
+		      name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
 	  break;
 
 	case BR:
@@ -201,7 +201,7 @@ print_insn_mcore (memaddr, info)
 	    if (inst & 0x400)
 	      val |= 0xFFFFFC00;
 
-	    fprintf (stream, "\t0x%lx", (long)(memaddr + 2 + (val << 1)));
+	    (*fprintf) (stream, "\t0x%lx", (long)(memaddr + 2 + (val << 1)));
 
 	    if (strcmp (op->name, "bsr") == 0)
 	      {
@@ -210,7 +210,7 @@ print_insn_mcore (memaddr, info)
 
 		if (info->print_address_func && val != 0)
 		  {
-		    fprintf (stream, "\t// ");
+		    (*fprintf) (stream, "\t// ");
 		    info->print_address_func (val, info);
 		  }
 	      }
@@ -221,8 +221,9 @@ print_insn_mcore (memaddr, info)
 	  {
 	    long val;
 	    val = (inst & 0x000F);
-	    fprintf (stream, "\t%s, 0x%lx",
-		     grname[(inst >> 4) & 0xF], (long)(memaddr - (val << 1)));
+	    (*fprintf) (stream, "\t%s, 0x%lx",
+			grname[(inst >> 4) & 0xF],
+			(long) (memaddr - (val << 1)));
 	  }
 	  break;
 
@@ -247,11 +248,12 @@ print_insn_mcore (memaddr, info)
 		| (ibytes[2] << 8) | (ibytes[3]);
 
 	    /* Removed [] around literal value to match ABI syntax 12/95.  */
-	    fprintf (stream, "\t%s, 0x%lX", grname[(inst >> 8) & 0xF], val);
+	    (*fprintf) (stream, "\t%s, 0x%lX", grname[(inst >> 8) & 0xF], val);
 
 	    if (val == 0)
-	      fprintf (stream, "\t// from address pool at 0x%lx",
-		       (long)(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
+	      (*fprintf) (stream, "\t// from address pool at 0x%lx",
+			  (long) (memaddr + 2
+				  + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
 	  }
 	  break;
 
@@ -276,17 +278,18 @@ print_insn_mcore (memaddr, info)
 		| (ibytes[2] << 8) | (ibytes[3]);
 
 	    /* Removed [] around literal value to match ABI syntax 12/95.  */
-	    fprintf (stream, "\t0x%lX", val);
+	    (*fprintf) (stream, "\t0x%lX", val);
 	    /* For jmpi/jsri, we'll try to get a symbol for the target.  */
 	    if (info->print_address_func && val != 0)
 	      {
-		fprintf (stream, "\t// ");
+		(*fprintf) (stream, "\t// ");
 		info->print_address_func (val, info);
 	      }
 	    else
 	      {
-		fprintf (stream, "\t// from address pool at 0x%lx",
-			 (long)(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
+		(*fprintf) (stream, "\t// from address pool at 0x%lx",
+			    (long) (memaddr + 2
+				    + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
 	      }
 	  }
 	  break;
@@ -298,13 +301,13 @@ print_insn_mcore (memaddr, info)
 	      "ee", "ee,ie", "ee,fe", "ee,fe,ie"
 	    };
 
-	    fprintf (stream, "\t%s", fields[inst & 0x7]);
+	    (*fprintf) (stream, "\t%s", fields[inst & 0x7]);
 	  }
 	  break;
 
 	default:
 	  /* If the disassembler lags the instruction set.  */
-	  fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
+	  (*fprintf) (stream, "\tundecoded operands, inst is 0x%04x", inst);
 	  break;
 	}
     }