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| author | Jeff Law <law@redhat.com> | 1996-10-11 22:06:47 +0000 |
|---|---|---|
| committer | Jeff Law <law@redhat.com> | 1996-10-11 22:06:47 +0000 |
| commit | 63dc694d2956f245e42e525cf9d4e6958d4d4554 (patch) | |
| tree | b914c71376810c86c506e34eff27db6b08e32e32 /opcodes | |
| parent | 913a7c4cc4e7e97d9149e7cd10f3402be9abfe4b (diff) | |
| download | gdb-63dc694d2956f245e42e525cf9d4e6958d4d4554.zip gdb-63dc694d2956f245e42e525cf9d4e6958d4d4554.tar.gz gdb-63dc694d2956f245e42e525cf9d4e6958d4d4554.tar.bz2 | |
* mn10300-opc.c (mn10300_opcodes): Fix typo in opcode
field for movhu instruction.
Bug found by gas testsuite.
* v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands,
cast value to "long" not "signed long" to keep hpux10
compiler quiet.
Found in an attempt to build the v850 on hpux10 with the HP
compiler.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 11 | ||||
| -rw-r--r-- | opcodes/mn10300-opc.c | 2 |
2 files changed, 12 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ddd4006..dfd29fb 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,14 @@ +Fri Oct 11 16:03:49 1996 Jeffrey A Law (law@cygnus.com) + + * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode + field for movhu instruction. +start-sanitize-v850 + + * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands, + cast value to "long" not "signed long" to keep hpux10 + compiler quiet. +end-sanitize-v850 + Thu Oct 10 10:25:58 1996 Jeffrey A Law (law@cygnus.com) * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field diff --git a/opcodes/mn10300-opc.c b/opcodes/mn10300-opc.c index 5084749..6795eac 100644 --- a/opcodes/mn10300-opc.c +++ b/opcodes/mn10300-opc.c @@ -211,7 +211,7 @@ const struct mn10300_opcode mn10300_opcodes[] = { { "movhu", 0xfabc0000, 0xfffc0000, FMT_D2, {MEM2(D16, SP), DN0}}, { "movhu", 0xfcbc0000, 0xfffc0000, FMT_D4, {MEM2(D32, SP), DN0}}, { "movhu", 0xf480, 0xffc0, FMT_D0, {MEM2(DI, AM0), DN0}}, -{ "movhu", 0xc80000, 0xfc0000, FMT_S2, {MEM(ABS16), DN0}}, +{ "movhu", 0x380000, 0xfc0000, FMT_S2, {MEM(ABS16), DN0}}, { "movhu", 0xfcac0000, 0xfffc0000, FMT_D4, {MEM(ABS32), DN0}}, { "movhu", 0xf070, 0xfff0, FMT_D0, {DM1, MEM(AN0)}}, { "movhu", 0xf87000, 0xfff000, FMT_D1, {DM1, MEM2(SD8, AN0)}}, |