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| author | Thomas Preud'homme <thomas.preudhomme@arm.com> | 2016-08-26 11:53:30 +0100 |
|---|---|---|
| committer | Thomas Preud'homme <thomas.preudhomme@arm.com> | 2016-08-26 11:53:30 +0100 |
| commit | 1a336194b70b712074a3f5479a01cc221003a152 (patch) | |
| tree | 77d4f16fb202dd9a8805b0e081d87a683a90e13e /opcodes | |
| parent | 980aa3e6dfeb0f018915f65be4b2987667f31fe9 (diff) | |
| download | gdb-1a336194b70b712074a3f5479a01cc221003a152.zip gdb-1a336194b70b712074a3f5479a01cc221003a152.tar.gz gdb-1a336194b70b712074a3f5479a01cc221003a152.tar.bz2 | |
Add missing ARMv8-M special registers
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
gas/
* config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS,
PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and
their lowecase counterpart special registers. Write register
identifier in hex.
* testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per
operation, special register and then case. Use different register for
each operation. Add tests for new special registers.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result
accordingly.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
opcodes/
* arm-dis.c (psr_name): Use hex as case labels. Add detection for
MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 37 |
2 files changed, 29 insertions, 14 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8ebbbfa..fe78a5f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * arm-dis.c (psr_name): Use hex as case labels. Add detection for + MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, + FAULTMASK_NS, CONTROL_NS and SP_NS special registers. + 2016-08-24 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index db59b84..fc9ac61 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -5427,22 +5427,31 @@ psr_name (int regno) { switch (regno) { - case 0: return "APSR"; - case 1: return "IAPSR"; - case 2: return "EAPSR"; - case 3: return "PSR"; - case 5: return "IPSR"; - case 6: return "EPSR"; - case 7: return "IEPSR"; - case 8: return "MSP"; - case 9: return "PSP"; - case 16: return "PRIMASK"; - case 17: return "BASEPRI"; - case 18: return "BASEPRI_MAX"; - case 19: return "FAULTMASK"; - case 20: return "CONTROL"; + case 0x0: return "APSR"; + case 0x1: return "IAPSR"; + case 0x2: return "EAPSR"; + case 0x3: return "PSR"; + case 0x5: return "IPSR"; + case 0x6: return "EPSR"; + case 0x7: return "IEPSR"; + case 0x8: return "MSP"; + case 0x9: return "PSP"; + case 0xa: return "MSPLIM"; + case 0xb: return "PSPLIM"; + case 0x10: return "PRIMASK"; + case 0x11: return "BASEPRI"; + case 0x12: return "BASEPRI_MAX"; + case 0x13: return "FAULTMASK"; + case 0x14: return "CONTROL"; case 0x88: return "MSP_NS"; case 0x89: return "PSP_NS"; + case 0x8a: return "MSPLIM_NS"; + case 0x8b: return "PSPLIM_NS"; + case 0x90: return "PRIMASK_NS"; + case 0x91: return "BASEPRI_NS"; + case 0x93: return "FAULTMASK_NS"; + case 0x94: return "CONTROL_NS"; + case 0x98: return "SP_NS"; default: return "<unknown>"; } } |