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| author | Tamar Christina <tamar.christina@arm.com> | 2018-05-16 12:13:42 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2018-05-16 12:14:19 +0100 |
| commit | ff329288d503d392de11f34ce64c7fdd3c62e50f (patch) | |
| tree | 2c0b79c01b84fd29596a18bb414cb9fd1bc398b5 /opcodes/aarch64-tbl.h | |
| parent | 0255c1a349ebd368c4c1bafd95118e7cc71eb973 (diff) | |
| download | gdb-ff329288d503d392de11f34ce64c7fdd3c62e50f.zip gdb-ff329288d503d392de11f34ce64c7fdd3c62e50f.tar.gz gdb-ff329288d503d392de11f34ce64c7fdd3c62e50f.tar.bz2 | |
Fix disassembly mask for vector sdot on AArch64.
This patch corrects the disassembly masks for by element dot product
instructions. The bit 10 was wrong and supposed to be 1.
This caused incorrect disassembly of instructions in the unallocated space to
disassemble as dot product instructions.
No encoding errors can arrise from this issue.
opcodes/
PR binutils/23109
* aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
* aarch64-dis-2.c: Regenerate.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 1e1b2e4..b416ded 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4313,8 +4313,8 @@ struct aarch64_opcode aarch64_opcode_table[] = /* SIMD Dot Product (optional in v8.2-A). */ DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), - DOT_INSN ("udot", 0x2f00e000, 0xbf00f000, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), - DOT_INSN ("sdot", 0xf00e000, 0xbf00f000, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), + DOT_INSN ("udot", 0x2f00e000, 0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), + DOT_INSN ("sdot", 0xf00e000, 0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ), /* Crypto SHA2 (optional in ARMv8.2-a). */ SHA2_INSN ("sha512h", 0xce608000, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0), SHA2_INSN ("sha512h2", 0xce608400, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0), |