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author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-05-21 14:49:03 +0100 |
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committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2019-05-21 14:53:49 +0100 |
commit | e6f65e7573a317ac4efff26fe0e49fe1b9e7a596 (patch) | |
tree | e12394a240761592fb54c179256bf96004ffe34e /ld | |
parent | 739b5c9c778dee9e2f54d864f83a81ecb0639535 (diff) | |
download | gdb-e6f65e7573a317ac4efff26fe0e49fe1b9e7a596.zip gdb-e6f65e7573a317ac4efff26fe0e49fe1b9e7a596.tar.gz gdb-e6f65e7573a317ac4efff26fe0e49fe1b9e7a596.tar.bz2 |
[binutils][Arm] Fix Branch Future relocation handling and testisms
bfd/ChangeLog:
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
PR/target 24460
* elf32-arm.c (get_value_helper): Remove.
(elf32_arm_final_link_relocate): Fix branch future relocations.
gas/ChangeLog:
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
* testsuite/gas/arm/armv8_1-m-bf.d: Allow different branch target naming
conventions.
* testsuite/gas/arm/armv8_1-m-bfl.d: Likewise.
* testsuite/gas/arm/armv8_1-m-bfcsel.d: Likewise.
* testsuite/gas/arm/armv8_1-m-loloop.d: Likewise.
* testsuite/gas/arm/armv8_1-m-bf-rel.d: Skip for vxworks.
* testsuite/gas/arm/armv8_1-m-bf-rela.d: New test.
* testsuite/gas/arm/armv8_1-m-bfl-rel.d: Skip for vxworks.
* testsuite/gas/arm/armv8_1-m-bfl-rela.d: New test.
ld/ChangeLog:
2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com>
* testsuite/ld-arm/arm-elf.exp: Add tests
* testsuite/ld-arm/bfs-0.s: New test.
* testsuite/ld-arm/bfs-1.s: New test.
* testsuite/ld-arm/branch-futures.d: New test.
Diffstat (limited to 'ld')
-rw-r--r-- | ld/ChangeLog | 7 | ||||
-rw-r--r-- | ld/testsuite/ld-arm/arm-elf.exp | 9 | ||||
-rw-r--r-- | ld/testsuite/ld-arm/bfs-0.s | 12 | ||||
-rw-r--r-- | ld/testsuite/ld-arm/bfs-1.s | 9 | ||||
-rw-r--r-- | ld/testsuite/ld-arm/branch-futures.d | 17 |
5 files changed, 54 insertions, 0 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog index 77beea0..05af393 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,10 @@ +2019-05-21 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * testsuite/ld-arm/arm-elf.exp: Add tests + * testsuite/ld-arm/bfs-0.s: New test. + * testsuite/ld-arm/bfs-1.s: New test. + * testsuite/ld-arm/branch-futures.d: New test. + 2019-05-21 Tamar Christina <tamar.christina@arm.com> PR ld/24373 diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp index 5471895..7d3217f 100644 --- a/ld/testsuite/ld-arm/arm-elf.exp +++ b/ld/testsuite/ld-arm/arm-elf.exp @@ -42,6 +42,11 @@ if {[istarget "arm-*-vxworks"]} { "" {vxworks2.s} {{readelf --segments vxworks2-static.sd}} "vxworks2"} + {"Branch future relocations for armv8.1-m.main target" + "-static -T arm.ld" + "" "" {bfs-0.s bfs-1.s} + {{objdump -dw branch-futures.d}} + "branch-futures"} } run_ld_link_tests $armvxworkstests run_dump_test "vxworks1-static" @@ -260,6 +265,10 @@ set armelftests_common_3 { {"ADDS thumb1 relocations for armv7-m target" "-static -T arm.ld" "" "" {thumb1-adds-armv7-m.s} {{objdump -dw thumb1-adds.d}} "thumb1-adds"} + {"Branch future relocations for armv8.1-m.main target" "-static -T arm.ld" + "" "" {bfs-0.s bfs-1.s} + {{objdump -dw branch-futures.d}} + "branch-futures"} } run_ld_link_tests $armelftests_common_1 diff --git a/ld/testsuite/ld-arm/bfs-0.s b/ld/testsuite/ld-arm/bfs-0.s new file mode 100644 index 0000000..844417a --- /dev/null +++ b/ld/testsuite/ld-arm/bfs-0.s @@ -0,0 +1,12 @@ +.arch armv8.1-m.main +.text +.syntax unified +.thumb +future: + bf branch, target + bfcsel branch, target, else, eq + bfl branch, target + add r0, r0, r1 +branch: + b target +else: diff --git a/ld/testsuite/ld-arm/bfs-1.s b/ld/testsuite/ld-arm/bfs-1.s new file mode 100644 index 0000000..2b72819 --- /dev/null +++ b/ld/testsuite/ld-arm/bfs-1.s @@ -0,0 +1,9 @@ +.arch armv8.1-m.main +.text +.syntax unified +.thumb +.global _start +.global target +_start: +target: + add r0, r0, r1 diff --git a/ld/testsuite/ld-arm/branch-futures.d b/ld/testsuite/ld-arm/branch-futures.d new file mode 100644 index 0000000..427ecce --- /dev/null +++ b/ld/testsuite/ld-arm/branch-futures.d @@ -0,0 +1,17 @@ + +.*: file format elf32-.* + + +Disassembly of section .text: + +0[0-9a-f]+ <future>: + [0-9a-f]+: f2c0 e807 bf a, 8012 <_start> + [0-9a-f]+: f182 e805 bfcsel 6, 8012 <_start>, a, eq + [0-9a-f]+: f080 c803 bfl 2, 8012 <_start> + [0-9a-f]+: 4408 add r0, r1 + +0[0-9a-f]+ <branch>: + [0-9a-f]+: f000 b800 b.w 8012 <_start> + +0[0-9a-f]+ <_start>: + [0-9a-f]+: 4408 add r0, r1 |