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| author | Nelson Chu <nelson.chu@sifive.com> | 2020-12-09 13:53:22 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson.chu@sifive.com> | 2020-12-10 10:50:44 +0800 |
| commit | c2137f55ad04e451d834048d4bfec1de2daea20e (patch) | |
| tree | 71848a36ae6d0a7e129af78179952d016007340a /include | |
| parent | 8152e0407c25612c6a8079cc8e1a5c1fe14afdbf (diff) | |
| download | gdb-c2137f55ad04e451d834048d4bfec1de2daea20e.zip gdb-c2137f55ad04e451d834048d4bfec1de2daea20e.tar.gz gdb-c2137f55ad04e451d834048d4bfec1de2daea20e.tar.bz2 | |
RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions.
https://github.com/riscv/riscv-asm-manual/pull/61
We aleady have sext.w, so just add sext.b, sext.h, zext.b, zext.h
and zext.w. In a certain sense, zext.b is not a pseudo - It is an
alias of andi. Similarly, sext.b and sext.h are aliases of other
rvb instructions, when we enable b extension; But they are pseudos
when we just enable rvi. However, this patch does not consider the
rvb cases. Besides, zext.w is only valid in rv64.
gas/
* config/tc-riscv.c (riscv_ext): New function. Use md_assemblef
to expand the zext and sext pseudos, to give them a chance to be
expanded into c-ext instructions.
(macro): Handle M_ZEXTH, M_ZEXTW, M_SEXTB and M_SEXTH.
* testsuite/gas/riscv/ext.s: New testcase.
* testsuite/gas/riscv/ext-32.d: Likewise.
* testsuite/gas/riscv/ext-64.d: Likewise.
include/
* opcode/riscv.h (M_ZEXTH, M_ZEXTW, M_SEXTB, M_SEXTH.): Added.
opcodes/
* riscv-opc.c (riscv_opcodes): Add sext.[bh] and zext.[bhw].
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 6f4614f..cc235e0 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,9 @@ 2020-12-10 Nelson Chu <nelson.chu@sifive.com> + * opcode/riscv.h (M_ZEXTH, M_ZEXTW, M_SEXTB, M_SEXTH.): Added. + +2020-12-10 Nelson Chu <nelson.chu@sifive.com> + * opcode/riscv.h: Add INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI. 2020-12-07 Nick Clifton <nickc@redhat.com> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 6a9fd4a..1949072 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -480,6 +480,10 @@ enum M_CALL, M_J, M_LI, + M_ZEXTH, + M_ZEXTW, + M_SEXTB, + M_SEXTH, M_NUM_MACROS }; |