From c2137f55ad04e451d834048d4bfec1de2daea20e Mon Sep 17 00:00:00 2001 From: Nelson Chu Date: Wed, 9 Dec 2020 13:53:22 +0800 Subject: RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions. https://github.com/riscv/riscv-asm-manual/pull/61 We aleady have sext.w, so just add sext.b, sext.h, zext.b, zext.h and zext.w. In a certain sense, zext.b is not a pseudo - It is an alias of andi. Similarly, sext.b and sext.h are aliases of other rvb instructions, when we enable b extension; But they are pseudos when we just enable rvi. However, this patch does not consider the rvb cases. Besides, zext.w is only valid in rv64. gas/ * config/tc-riscv.c (riscv_ext): New function. Use md_assemblef to expand the zext and sext pseudos, to give them a chance to be expanded into c-ext instructions. (macro): Handle M_ZEXTH, M_ZEXTW, M_SEXTB and M_SEXTH. * testsuite/gas/riscv/ext.s: New testcase. * testsuite/gas/riscv/ext-32.d: Likewise. * testsuite/gas/riscv/ext-64.d: Likewise. include/ * opcode/riscv.h (M_ZEXTH, M_ZEXTW, M_SEXTB, M_SEXTH.): Added. opcodes/ * riscv-opc.c (riscv_opcodes): Add sext.[bh] and zext.[bhw]. --- include/ChangeLog | 4 ++++ include/opcode/riscv.h | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'include') diff --git a/include/ChangeLog b/include/ChangeLog index 6f4614f..cc235e0 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,9 @@ 2020-12-10 Nelson Chu + * opcode/riscv.h (M_ZEXTH, M_ZEXTW, M_SEXTB, M_SEXTH.): Added. + +2020-12-10 Nelson Chu + * opcode/riscv.h: Add INSN_CLASS_ZICSR and INSN_CLASS_ZIFENCEI. 2020-12-07 Nick Clifton diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 6a9fd4a..1949072 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -480,6 +480,10 @@ enum M_CALL, M_J, M_LI, + M_ZEXTH, + M_ZEXTW, + M_SEXTB, + M_SEXTH, M_NUM_MACROS }; -- cgit v1.1