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| author | Maciej W. Rozycki <macro@codesourcery.com> | 2014-08-26 13:44:34 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@codesourcery.com> | 2014-08-26 13:44:34 +0100 |
| commit | 5575639b8dbb2a04087c3bef0b10f182da48ad35 (patch) | |
| tree | 78b3908ad5220a6b8cb90396ab42ca8e6412c1d6 /include | |
| parent | 0db377d09c19fc0f9267ead1f75998b9f1eb38d1 (diff) | |
| download | gdb-5575639b8dbb2a04087c3bef0b10f182da48ad35.zip gdb-5575639b8dbb2a04087c3bef0b10f182da48ad35.tar.gz gdb-5575639b8dbb2a04087c3bef0b10f182da48ad35.tar.bz2 | |
MIPS: Make the CODE10 operand code consistent between ISAs
This change moves the microMIPS 10-bit uninterpreted immediate code
embedded at bits 25..16 in the SYSCALL, WAIT, SDBBP and HYPCALL
instructions from `B' over to `+J' which is the operand code used in
the standard MIPS instruction set for a similar code embedded at bits
20..11, currently used by HYPCALL only in that set.
opcodes/
* micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
(micromips_opcodes): Use "+J" in place of "B" for "hypcall",
"sdbbp", "syscall" and "wait".
include/opcode/
* mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
over to `+J'.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/mips.h | 7 |
2 files changed, 9 insertions, 3 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 95532b1..955706c 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,8 @@ +2014-08-26 Maciej W. Rozycki <macro@codesourcery.com> + + * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B' + over to `+J'. + 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> * mips.h (INSN_LOAD_COPROC_DELAY): Rename to... diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 846cc0f..aa1528f 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -2056,7 +2056,6 @@ extern const int bfd_mips16_num_opcodes; "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) "z" must be zero register "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) - "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10) "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes @@ -2081,6 +2080,8 @@ extern const int bfd_mips16_num_opcodes; "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). Requires that "+A" or "+E" occur first to set position. Enforces: 32 < (pos+size) <= 64. + "+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code + (MICROMIPSOP_*_CODE10) PC-relative addition (ADDIUPC) instruction: "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ) @@ -2160,14 +2161,14 @@ extern const int bfd_mips16_num_opcodes; Characters used so far, for quick reference when adding more: "12345678 0" "<>(),+.@\^|~" - "ABCDEFGHI KLMN RST V " + "A CDEFGHI KLMN RST V " "abcd f hijklmnopqrstuvw yz" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "" "~!@#$%^&*|" - "ABCEFGHTUVW" + "ABCEFGHJTUVW" "dehijklnouvwx" Extension character sequences used so far ("m" followed by the |