MIPS: Make the CODE10 operand code consistent between ISAs

This change moves the microMIPS 10-bit uninterpreted immediate code
embedded at bits 25..16 in the SYSCALL, WAIT, SDBBP and HYPCALL
instructions from `B' over to `+J' which is the operand code used in
the standard MIPS instruction set for a similar code embedded at bits
20..11, currently used by HYPCALL only in that set.

	opcodes/
	* micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
	(micromips_opcodes): Use "+J" in place of "B" for "hypcall",
	"sdbbp", "syscall" and "wait".

	include/opcode/
	* mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
	over to `+J'.

4 files changed, 20 insertions, 8 deletions

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 95532b1..955706c 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
+	over to `+J'.
+
 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 
 	* mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 846cc0f..aa1528f 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -2056,7 +2056,6 @@ extern const int bfd_mips16_num_opcodes;
    "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
    "z" must be zero register
    "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
-   "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
    "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
 
    "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
@@ -2081,6 +2080,8 @@ extern const int bfd_mips16_num_opcodes;
    "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
 	Requires that "+A" or "+E" occur first to set position.
 	Enforces: 32 < (pos+size) <= 64.
+   "+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code
+        (MICROMIPSOP_*_CODE10)
 
    PC-relative addition (ADDIUPC) instruction:
    "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
@@ -2160,14 +2161,14 @@ extern const int bfd_mips16_num_opcodes;
    Characters used so far, for quick reference when adding more:
    "12345678 0"
    "<>(),+.@\^|~"
-   "ABCDEFGHI KLMN   RST V    "
+   "A CDEFGHI KLMN   RST V    "
    "abcd f hijklmnopqrstuvw yz"
 
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:
    ""
    "~!@#$%^&*|"
-   "ABCEFGHTUVW"
+   "ABCEFGHJTUVW"
    "dehijklnouvwx"
 
    Extension character sequences used so far ("m" followed by the
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a9581ae..ca42dc9 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2014-08-26  Maciej W. Rozycki  <macro@codesourcery.com>
+
+	* micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
+	(micromips_opcodes): Use "+J" in place of "B" for "hypcall",
+	"sdbbp", "syscall" and "wait".
+
 2014-08-21  Nathan Sidwell  <nathan@codesourcery.com>
 	    Maciej W. Rozycki  <macro@codesourcery.com>
 
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 4bf8241..71b2dfe 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -107,6 +107,7 @@ decode_micromips_operand (const char *p)
 	case 'F': MSB (5, 11, 33, TRUE, 64);	 /* (33 .. 64), 64-bit op */
 	case 'G': MSB (5, 11, 33, FALSE, 64);	 /* (33 .. 64), 64-bit op */
 	case 'H': MSB (5, 11, 1, FALSE, 64);	 /* (1 .. 32), 64-bit op */
+	case 'J': HINT (10, 16);
 	case 'T': INT_ADJ (10, 16, 511, 0, FALSE);	/* (-512 .. 511) << 0 */
 	case 'U': INT_ADJ (10, 16, 511, 1, FALSE);	/* (-512 .. 511) << 1 */
 	case 'V': INT_ADJ (10, 16, 511, 2, FALSE);	/* (-512 .. 511) << 2 */
@@ -158,7 +159,6 @@ decode_micromips_operand (const char *p)
     case '7': REG (2, 14, ACC);
     case '8': HINT (6, 14);
 
-    case 'B': HINT (10, 16);
     case 'C': HINT (23, 3);
     case 'D': REG (5, 11, FP);
     case 'E': REG (5, 21, COPRO);
@@ -688,7 +688,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"floor.w.d",		"T,V",		0x54004b3b, 0xfc00ffff,	WR_1|RD_2|FP_S|FP_D,	0,		I1,		0,	0 },
 {"floor.w.s",		"T,V",		0x54000b3b, 0xfc00ffff,	WR_1|RD_2|FP_S,		0,		I1,		0,	0 },
 {"hypcall",		"",		0x0000c37c, 0xffffffff,	TRAP,			0,		0,		IVIRT,	0 },
-{"hypcall",		"B",		0x0000c37c, 0xfc00ffff,	TRAP,			0,		0,		IVIRT,	0 },
+{"hypcall",		"+J",		0x0000c37c, 0xfc00ffff,	TRAP,			0,		0,		IVIRT,	0 },
 {"ins",			"t,r,+A,+B",	0x0000000c, 0xfc00003f, WR_1|RD_2,		0,		I1,		0,	0 },
 {"iret",		"",		0x0000d37c, 0xffffffff,	NODS,			0,		0,		MC,	0 },
 {"jr",			"mj",		    0x4580,     0xffe0,	RD_1|UBD,		0,		I1,		0,	0 },
@@ -963,7 +963,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"sdbbp",		"",		    0x46c0,     0xffff,	TRAP,			0,		I1,		0,	0 },
 {"sdbbp",		"",		0x0000db7c, 0xffffffff,	TRAP,			0,		I1,		0,	0 },
 {"sdbbp",		"mO",		    0x46c0,     0xfff0,	TRAP,			0,		I1,		0,	0 },
-{"sdbbp",		"B",		0x0000db7c, 0xfc00ffff,	TRAP,			0,		I1,		0,	0 },
+{"sdbbp",		"+J",		0x0000db7c, 0xfc00ffff,	TRAP,			0,		I1,		0,	0 },
 {"sdc1",		"T,o(b)",	0xb8000000, 0xfc000000,	RD_1|RD_3|SM|FP_D,	0,		I1,		0,	0 },
 {"sdc1",		"E,o(b)",	0xb8000000, 0xfc000000,	RD_1|RD_3|SM|FP_D,	0,		I1,		0,	0 },
 {"sdc1",		"T,A(b)",	0,    (int) M_SDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I1,		0,	0 },
@@ -1066,7 +1066,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"sync",		"1",		0x00006b7c, 0xffe0ffff,	NODS,			0,		I1,		0,	0 },
 {"synci",		"o(b)",		0x42000000, 0xffe00000,	RD_2|SM,		0,		I1,		0,	0 },
 {"syscall",		"",		0x00008b7c, 0xffffffff,	TRAP,			0,		I1,		0,	0 },
-{"syscall",		"B",		0x00008b7c, 0xfc00ffff,	TRAP,			0,		I1,		0,	0 },
+{"syscall",		"+J",		0x00008b7c, 0xfc00ffff,	TRAP,			0,		I1,		0,	0 },
 {"teqi",		"s,j",		0x41c00000, 0xffe00000,	RD_1|TRAP,		0,		I1,		0,	0 },
 {"teq",			"s,t",		0x0000003c, 0xfc00ffff,	RD_1|RD_2|TRAP,		0,		I1,		0,	0 },
 {"teq",			"s,t,|",	0x0000003c, 0xfc000fff,	RD_1|RD_2|TRAP,		0,		I1,		0,	0 },
@@ -1121,7 +1121,7 @@ const struct mips_opcode micromips_opcodes[] =
 {"ush",			"t,A(b)",	0,    (int) M_USH_AB,	INSN_MACRO,		0,		I1,		0,	0 },
 {"usw",			"t,A(b)",	0,    (int) M_USW_AB,	INSN_MACRO,		0,		I1,		0,	0 },
 {"wait",		"",		0x0000937c, 0xffffffff,	NODS,			0,		I1,		0,	0 },
-{"wait",		"B",		0x0000937c, 0xfc00ffff,	NODS,			0,		I1,		0,	0 },
+{"wait",		"+J",		0x0000937c, 0xfc00ffff,	NODS,			0,		I1,		0,	0 },
 {"wrpgpr",		"t,r",		0x0000f17c, 0xfc00ffff,	RD_2,			0,		I1,		0,	0 },
 {"wsbh",		"t,r",		0x00007b3c, 0xfc00ffff,	WR_1|RD_2,		0,		I1,		0,	0 },
 {"xor",			"mf,mt,mg",	    0x4440,     0xffc0,	MOD_1|RD_3,		0,		I1,		0,	0 },