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| author | Nelson Chu <nelson@rivosinc.com> | 2024-06-18 15:15:14 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-06-18 15:15:14 +0800 |
| commit | 7aabe8edca8aaafa099a3451ce97997278a5bcf2 (patch) | |
| tree | 130b14e1b7a38fa26f3d73fda5e4640d4465e3a4 | |
| parent | 7003edc383feaa72c13310d075d383c2a98a6a6e (diff) | |
| download | gdb-7aabe8edca8aaafa099a3451ce97997278a5bcf2.zip gdb-7aabe8edca8aaafa099a3451ce97997278a5bcf2.tar.gz gdb-7aabe8edca8aaafa099a3451ce97997278a5bcf2.tar.bz2 | |
RISC-V: Updated gas/NEWS and gas/doc/c-riscv.texi for vendor extensions.
gas/
* NEWS: Updated for XCvMem, XCvBi, XCvElw, XSfCease.
* doc/c-riscv.texi: Minor typo for XCv* extensions.
| -rw-r--r-- | gas/NEWS | 5 | ||||
| -rw-r--r-- | gas/doc/c-riscv.texi | 20 |
2 files changed, 15 insertions, 10 deletions
@@ -31,6 +31,11 @@ * Add support for RISC-V Smcsrind/Sscsrind extension with version 1.0. +* Add support for RISC-V CORE-V extensions (XCvMem, XCvBi, XCvElw) with + version 1.0. + +* Add support for RISC-V SiFive cease extension (XSfCease) with version 1.0. + * The base register operand in D(X,B) and D(L,B) may be explicitly omitted in assembly on s390. It can now be coded as D(X,) or D(L,) instead of D(X,0) D(X,%r0), D(L,0), and D(L,%r0). diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index e579eeb..ebff7a6 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -740,28 +740,28 @@ extensions supported and provides the location of their publicly-released documentation: @table @r -@item Xcvmac -The Xcvmac extension provides instructions for multiply-accumulate operations. +@item XCvMac +The XCvMac extension provides instructions for multiply-accumulate operations. It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html} -@item Xcvalu -The Xcvalu extension provides instructions for general ALU operations. +@item XCvAlu +The XCvAlu extension provides instructions for general ALU operations. It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html} -@item Xcvelw -The Xcvelw extension provides instructions for event load word operations. +@item XCvElw +The XCvElw extension provides instructions for event load word operations. It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html} -@item Xcvbi -The Xcvbi extension provides instructions for branch immediate operations. +@item XCvBi +The XCvBi extension provides instructions for branch immediate operations. It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html} -@item Xcvmem -The Xcvmem extension provides instructions for post inc load/store operations. +@item XCvMem +The XCvMem extension provides instructions for post inc load/store operations. It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html} |