diff options
Diffstat (limited to 'gcc/testsuite')
277 files changed, 7128 insertions, 143 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 728f66f..ceb916f 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,897 @@ +2025-07-24 Nathaniel Shead <nathanieloshead@gmail.com> + + PR c++/117294 + PR c++/113854 + * g++.dg/cpp2a/concepts-traits3.C: Adjust diagnostics. + * g++.dg/cpp2a/concepts-traits4.C: New test. + * g++.dg/diagnostic/static_assert5.C: New test. + * g++.dg/ext/has_virtual_destructor2.C: New test. + * g++.dg/ext/is_assignable2.C: New test. + * g++.dg/ext/is_constructible9.C: New test. + * g++.dg/ext/is_convertible7.C: New test. + * g++.dg/ext/is_destructible3.C: New test. + * g++.dg/ext/is_invocable6.C: New test. + * g++.dg/ext/is_virtual_base_of_diagnostic2.C: New test. + +2025-07-24 Jason Merrill <jason@redhat.com> + + PR c++/114632 + PR c++/101233 + * g++.dg/cpp23/explicit-obj-lambda18.C: New test. + * g++.dg/cpp23/static-operator-call7.C: New test. + +2025-07-24 Robert Dubner <rdubner@symas.com> + + * cobol.dg/group2/_-static__compilation.cob: Modify for -static warning. + * cobol.dg/group2/_-static__compilation.out: Removed. + +2025-07-24 Robin Dapp <rdapp@ventanamicro.com> + + * lib/target-supports.exp: Fix misalignment check. + +2025-07-24 Spencer Abson <spencer.abson@arm.com> + + * g++.target/aarch64/sve/unpacked_cond_binary_bf16_1.C: New test. + * gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_fadd_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_fdiv_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_fmaxnm_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_fminnm_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_fmul_1.c: Likewise.. + * gcc.target/aarch64/sve/unpacked_cond_fsubr_1.c: Likewise. + +2025-07-24 Spencer Abson <spencer.abson@arm.com> + + * gcc.target/aarch64/sve/unpacked_fdiv_1.c: New test. + * gcc.target/aarch64/sve/unpacked_fdiv_2.c: Likewise. + * gcc.target/aarch64/sve/unpacked_fdiv_3.c: Likewise. + +2025-07-24 Spencer Abson <spencer.abson@arm.com> + + * g++.target/aarch64/sve/unpacked_binary_bf16_1.C: New test. + * g++.target/aarch64/sve/unpacked_binary_bf16_2.C: Likewise. + * gcc.target/aarch64/sve/unpacked_builtin_fmax_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_builtin_fmax_2.c: Likewise. + * gcc.target/aarch64/sve/unpacked_builtin_fmin_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_builtin_fmin_2.c: Likewise. + * gcc.target/aarch64/sve/unpacked_fadd_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_fadd_2.c: Likewise. + * gcc.target/aarch64/sve/unpacked_fmaxnm_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_fmaxnm_2.c: Likewise. + * gcc.target/aarch64/sve/unpacked_fminnm_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_fminnm_2.c: Likewise. + * gcc.target/aarch64/sve/unpacked_fmul_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_fmul_2.c: Likewise. + * gcc.target/aarch64/sve/unpacked_fsubr_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_fsubr_2.c: Likewise. + +2025-07-24 Jeevitha Palanisamy <jeevitha@linux.ibm.com> + + PR testsuite/119382 + * gcc.target/powerpc/vsx-builtin-7.c: Add '-fno-ipa-icf' to dg-options. + +2025-07-24 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u16.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u32.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u64.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u8.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm.h: New test. + +2025-07-24 Nathaniel Shead <nathanieloshead@gmail.com> + + PR c++/120412 + * g++.dg/modules/internal-14_a.C: New test. + * g++.dg/modules/internal-14_b.C: New test. + * g++.dg/modules/internal-14_c.C: New test. + +2025-07-23 Spencer Abson <spencer.abson@arm.com> + + * gcc.target/aarch64/sve/unpacked_cond_fabs_1.c: New test. + * gcc.target/aarch64/sve/unpacked_cond_fneg_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_frinta_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_frinta_2.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_frinti_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_frintm_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_frintp_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_frintx_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_frintz_1.c: Likewise. + +2025-07-23 Spencer Abson <spencer.abson@arm.com> + + * gcc.target/aarch64/sve/unpacked_fabs_1.c: New test. + * gcc.target/aarch64/sve/unpacked_fneg_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_frinta_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_frinta_2.c: Likewise. + * gcc.target/aarch64/sve/unpacked_frinti_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_frinti_2.c: Likewise. + * gcc.target/aarch64/sve/unpacked_frintm_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_frintm_2.c: Likewise. + * gcc.target/aarch64/sve/unpacked_frintp_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_frintp_2.c: Likewise. + * gcc.target/aarch64/sve/unpacked_frintx_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_frintx_2.c: Likewise. + * gcc.target/aarch64/sve/unpacked_frintz_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_frintz_2.c: Likewise. + +2025-07-23 Spencer Abson <spencer.abson@arm.com> + + * gcc.target/aarch64/sve/unpacked_cond_cvtf_1.c: New test. + * gcc.target/aarch64/sve/unpacked_cond_fcvt_1.c: Likewise. + * gcc.target/aarch64/sve/unpacked_cond_fcvtz_1.c: Likewise. + +2025-07-23 Harald Anlauf <anlauf@gmx.de> + + PR fortran/121203 + * gfortran.dg/function_charlen_4.f90: New test. + +2025-07-23 Robin Dapp <rdapp@ventanamicro.com> + + PR target/121073 + * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c: Adjust test + expectation. + * gcc.target/riscv/rvv/base/scalar_move-5.c: Ditto. + * gcc.target/riscv/rvv/base/scalar_move-6.c: Ditto. + * gcc.target/riscv/rvv/base/scalar_move-7.c: Ditto. + * gcc.target/riscv/rvv/base/scalar_move-8.c: Ditto. + * gcc.target/riscv/rvv/base/scalar_move-9.c: Ditto. + * gcc.target/riscv/rvv/pr121073.c: New test. + +2025-07-23 Robin Dapp <rdapp@ventanamicro.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c: + Add zvfh requirements and options. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c: + Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c: + Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c: + Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c: + Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c: + Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c: + Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c: + Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c: + Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c: + Ditto. + * lib/target-supports.exp: Add zvfh options. + +2025-07-23 Andrew Pinski <quic_apinski@quicinc.com> + + PR target/120119 + * g++.dg/torture/pr120119-1.C: New test. + +2025-07-23 Patrick Palka <ppalka@redhat.com> + + PR c++/121179 + * g++.dg/lookup/operator-8.C: Strengthen test and remove one + XFAIL. + +2025-07-23 Patrick Palka <ppalka@redhat.com> + + PR c++/121055 + * g++.dg/ext/is_invocable5.C: New test. + +2025-07-23 Spencer Abson <spencer.abson@arm.com> + + * lib/gcc-defs.exp (aarch64-arg-dg-options): Split add_tune into + add_tune and add_override, so that specifying -moverride does not + change the baseline tuning from the testuite's default (generic). + +2025-07-23 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121220 + * gcc.dg/tree-ssa/ssa-sink-23.c: New testcase. + +2025-07-23 Martin Jambor <mjambor@suse.cz> + + PR tree-optimization/119085 + * gcc.dg/tree-ssa/pr119085.c: New test. + +2025-07-23 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/121164 + * gm2/switches/pedantic-params/fail/arrayofchar.def: New test. + * gm2/switches/pedantic-params/fail/arrayofchar.mod: New test. + +2025-07-23 Richard Biener <rguenther@suse.de> + + PR middle-end/121216 + * gcc.dg/pr121216.c: New testcase. + +2025-07-23 Andrew Pinski <quic_apinski@quicinc.com> + + PR testsuite/120101 + * gcc.dg/tree-ssa/pr81627.c (fn1): Mark as noinline. + +2025-07-23 Siddhesh Poyarekar <siddhesh@gotplt.org> + + * gcc.dg/vect/pr116125.c (mem_overlap): Expand A to 10 members. + +2025-07-22 Jason Merrill <jason@redhat.com> + + PR c++/121068 + * g++.dg/cpp2a/constexpr-union6.C: Expect x5 to work. + * g++.dg/cpp26/constexpr-new4.C: New test. + +2025-07-22 Jason Merrill <jason@redhat.com> + + * g++.dg/warn/Wmismatched-new-delete-5.C: Fix allocation. + +2025-07-22 Andrew Pinski <quic_apinski@quicinc.com> + + PR middle-end/109267 + * lib/target-supports.exp (check_effective_target_trap): New proc. + * g++.dg/missing-return.C: Update testcase for the !trap case. + * gcc.dg/pr109267-1.c: New test. + * gcc.dg/pr109267-2.c: New test. + +2025-07-22 Karl Meakin <karl.meakin@arm.com> + + * gcc.target/aarch64/sve/mask_load_2.c: Update tests. + +2025-07-22 Karl Meakin <karl.meakin@arm.com> + + * gcc.target/aarch64/sve/mask_load_2.c: New test. + +2025-07-22 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121202 + * gcc.dg/pr121202.c: New testcase. + +2025-07-22 Richard Biener <rguenther@suse.de> + + * gcc.dg/vect/slp-28.c: Adjust. + +2025-07-21 Andrew Pinski <quic_apinski@quicinc.com> + + PR tree-optimization/110949 + PR tree-optimization/95906 + * gcc.dg/tree-ssa/cmp-2.c: New test. + * gcc.dg/tree-ssa/max-bitcmp-1.c: New test. + +2025-07-21 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Add asm check. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u64.c: New test. + +2025-07-21 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c: Add asm check. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c: Ditto. + +2025-07-21 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test + helper macros. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test + data for run test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u16.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u32.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u8.c: New test. + +2025-07-21 Kyrylo Tkachov <ktkachov@nvidia.com> + + * gcc.target/aarch64/simd/mf8_data_1.c (test_set_lane4, + test_setq_lane4): Relax allowed assembly. + * gcc.target/aarch64/vec-set-zero.c: Use -Os in flags. + * gcc.target/aarch64/inszero_split_1.c: New test. + +2025-07-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121194 + * gcc.dg/torture/pr121194.c: New testcase. + +2025-07-21 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + * gcc.dg/pr87600-2.c: Split test into two files since errors for + functions test{0,1} are thrown during expand, and for + test{2,3} during gimplification. + * lib/scanasm.exp: On s390, skip lines beginning with #. + * gcc.dg/asm-hard-reg-error-1.c: New test. + * gcc.dg/asm-hard-reg-error-2.c: New test. + * gcc.dg/asm-hard-reg-error-3.c: New test. + * gcc.dg/asm-hard-reg-error-4.c: New test. + * gcc.dg/asm-hard-reg-error-5.c: New test. + * gcc.dg/pr87600-3.c: New test. + * gcc.target/aarch64/asm-hard-reg-2.c: New test. + * gcc.target/s390/asm-hard-reg-7.c: New test. + +2025-07-21 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + * gcc.dg/asm-hard-reg-1.c: New test. + * gcc.dg/asm-hard-reg-2.c: New test. + * gcc.dg/asm-hard-reg-3.c: New test. + * gcc.dg/asm-hard-reg-4.c: New test. + * gcc.dg/asm-hard-reg-5.c: New test. + * gcc.dg/asm-hard-reg-6.c: New test. + * gcc.dg/asm-hard-reg-7.c: New test. + * gcc.dg/asm-hard-reg-8.c: New test. + * gcc.target/aarch64/asm-hard-reg-1.c: New test. + * gcc.target/i386/asm-hard-reg-1.c: New test. + * gcc.target/i386/asm-hard-reg-2.c: New test. + * gcc.target/s390/asm-hard-reg-1.c: New test. + * gcc.target/s390/asm-hard-reg-2.c: New test. + * gcc.target/s390/asm-hard-reg-3.c: New test. + * gcc.target/s390/asm-hard-reg-4.c: New test. + * gcc.target/s390/asm-hard-reg-5.c: New test. + * gcc.target/s390/asm-hard-reg-6.c: New test. + * gcc.target/s390/asm-hard-reg-longdouble.h: New test. + +2025-07-21 Richard Biener <rguenther@suse.de> + + * gcc.dg/vect/vect-127.c: New testcase. + +2025-07-21 Andre Vehreschild <vehre@gcc.gnu.org> + + PR fortran/119106 + * gfortran.dg/array_constructor_58.f90: New test. + +2025-07-21 panciyan <panciyan@eswincomputing.com> + + * gcc.target/riscv/sat/sat_arith.h: Unsigned testcase form8 form9. + * gcc.target/riscv/sat/sat_u_add-8-u16.c: New test. + * gcc.target/riscv/sat/sat_u_add-8-u32.c: New test. + * gcc.target/riscv/sat/sat_u_add-8-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-8-u8.c: New test. + * gcc.target/riscv/sat/sat_u_add-9-u16.c: New test. + * gcc.target/riscv/sat/sat_u_add-9-u32.c: New test. + * gcc.target/riscv/sat/sat_u_add-9-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-9-u8.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-8-u16.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-8-u32.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-8-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-8-u8.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-9-u16.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-9-u32.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-9-u64.c: New test. + * gcc.target/riscv/sat/sat_u_add-run-9-u8.c: New test. + +2025-07-20 Andrew Pinski <quic_apinski@quicinc.com> + + PR testsuite/120859 + * gcc.dg/tree-prof/afdo-crossmodule-1b.c: Add some dg-* + commands like what is in afdo-crossmodule-1.c + +2025-07-20 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c: + Leverage DEF_AVG_0_WRAP to generate the correct func name. + * gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c: Ditto. + +2025-07-19 Dimitar Dimitrov <dimitar@dinux.eu> + + PR target/121124 + * gcc.target/pru/pragma-ctable_entry-2.c: New test. + +2025-07-19 Paul-Antoine Arras <parras@baylibre.com> + + PR target/119100 + * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfwnmacc and + vfwnmsac. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise. + * gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c: New test. + * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c: New test. + +2025-07-18 Harald Anlauf <anlauf@gmx.de> + + PR fortran/121145 + * gfortran.dg/pointer_check_15.f90: New test. + +2025-07-18 Andrew Pinski <quic_apinski@quicinc.com> + + PR testsuite/121153 + * gcc.dg/vect/vect-reduc-cond-1.c: Require vect_condition. + * gcc.dg/vect/vect-reduc-cond-2.c: Likewise. + +2025-07-18 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/avg_data.h: Adjust the test data. + * gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c: New test. + * gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c: New test. + +2025-07-18 Martin Jambor <mjambor@suse.cz> + + PR tree-optimization/117423 + * gcc.dg/tree-ssa/pr117423.c: New test. + +2025-07-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121126 + * gcc.dg/vect/pr121126.c: New testcase. + +2025-07-18 Richard Biener <rguenther@suse.de> + + PR tree-optimization/120924 + * gcc.dg/uninit-pr120924.c: New testcase. + +2025-07-18 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/121131 + * gcc.dg/bitint-124.c: New test. + +2025-07-17 Jason Merrill <jason@redhat.com> + + PR c++/87097 + * g++.dg/cpp0x/constexpr-array29.C: New test. + +2025-07-17 Richard Sandiford <richard.sandiford@arm.com> + Yury Khrustalev <yury.khrustalev@arm.com> + + * lib/target-supports.exp (add_options_for_aarch64_sme) + (check_effective_target_aarch64_sme_hw): New procedures. + * g++.target/aarch64/sme/sme_throw_1.C: New test. + * g++.target/aarch64/sme/sme_throw_2.C: Likewise. + +2025-07-17 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + * gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c: Adapt + scan assembler directives. + * gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c: Ditto. + * gcc.target/s390/signbit-1.c: New test. + * gcc.target/s390/signbit-2.c: New test. + * gcc.target/s390/signbit-3.c: New test. + * gcc.target/s390/signbit-4.c: New test. + * gcc.target/s390/signbit-5.c: New test. + * gcc.target/s390/signbit.h: New test. + +2025-07-17 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + * gcc.target/s390/vector/vlgv-zero-extend-1.c: New test. + +2025-07-17 Xi Ruoyao <xry111@xry111.site> + + PR target/121064 + * gcc.target/loongarch/pr121064.c: New test. + +2025-07-17 Richard Biener <rguenther@suse.de> + + * gcc.dg/vect/bb-slp-39.c: Adjust. + +2025-07-17 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121035 + * gcc.dg/pr121035.c: New testcase. + +2025-07-16 Uros Bizjak <ubizjak@gmail.com> + + PR target/121062 + * gcc.target/i386/pr121062-1.c: New test. + * gcc.target/i386/pr121062-2.c: Likewise. + * gcc.target/i386/pr121062-3a.c: Likewise. + * gcc.target/i386/pr121062-3b.c: Likewise. + * gcc.target/i386/pr121062-3c.c: Likewise. + * gcc.target/i386/pr121062-4.c: Likewise. + * gcc.target/i386/pr121062-5.c: Likewise. + * gcc.target/i386/pr121062-6.c: Likewise. + * gcc.target/i386/pr121062-7.c: Likewise. + +2025-07-16 H.J. Lu <hjl.tools@gmail.com> + + PR target/120881 + PR testsuite/121078 + * gcc.dg/20021014-1.c (dg-additional-options): Add -mfentry + -fno-pic only on gnu/x86 targets. + * gcc.dg/aru-2.c (dg-additional-options): Likewise. + * gcc.dg/nest.c (dg-additional-options): Likewise. + * gcc.dg/pr32450.c (dg-additional-options): Likewise. + * gcc.dg/pr43643.c (dg-additional-options): Likewise. + * gcc.target/i386/pr104447.c (dg-additional-options): Likewise. + * gcc.target/i386/pr113122-3.c(dg-additional-options): Likewise. + * gcc.target/i386/pr119386-1.c (dg-additional-options): Add + -mfentry only on gnu targets. + * gcc.target/i386/pr119386-2.c (dg-additional-options): Likewise. + +2025-07-16 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121049 + * gcc.dg/vect/pr121049.c: New testcase. + +2025-07-16 Andrew Pinski <quic_apinski@quicinc.com> + + PR tree-optimization/119920 + PR tree-optimization/112324 + PR tree-optimization/110015 + * gcc.dg/vect/vect-reduc-cond-1.c: New test. + * gcc.dg/vect/vect-reduc-cond-2.c: New test. + * gcc.dg/vect/vect-reduc-cond-3.c: New test. + +2025-07-16 Richard Biener <rguenther@suse.de> + + PR tree-optimization/121116 + * gcc.dg/torture/pr121116.c: New testcase. + +2025-07-16 Spencer Abson <spencer.abson@arm.com> + + PR target/117850 + * gcc.target/aarch64/simd/vabal_combine.c: Removed. This is + covered by fold_to_highpart_1.c + * gcc.target/aarch64/simd/fold_to_highpart_1.c: New test. + * gcc.target/aarch64/simd/fold_to_highpart_2.c: Likewise. + * gcc.target/aarch64/simd/fold_to_highpart_3.c: Likewise. + * gcc.target/aarch64/simd/fold_to_highpart_4.c: Likewise. + * gcc.target/aarch64/simd/fold_to_highpart_5.c: Likewise. + * gcc.target/aarch64/simd/fold_to_highpart_6.c: Likewise. + +2025-07-16 Alfie Richards <alfie.richards@arm.com> + + * g++.dg/warn/Wformat-gcc_diag-1.C: Add string_slice "%B" format tests. + +2025-07-16 Robin Dapp <rdapp@ventanamicro.com> + + PR middle-end/121065 + * gcc.target/arm/pr121065.c: New test. + +2025-07-16 Robin Dapp <rdapp@ventanamicro.com> + + PR target/120297 + * gcc.target/riscv/rvv/pr120297.c: New test. + +2025-07-16 Kyrylo Tkachov <ktkachov@nvidia.com> + + * gcc.target/aarch64/sve2/eon_bsl2n.c: New test. + +2025-07-16 Kyrylo Tkachov <ktkachov@nvidia.com> + + * gcc.target/aarch64/sve2/nbsl_nor_nand_neon.c: New test. + +2025-07-16 Paul Thomas <pault@gcc.gnu.org> + + PR fortran/121060 + * gfortran.dg/associate_75.f90: New test. + +2025-07-16 Steve Kargl <sgk@troutmask.apl.washington.edu> + + * gfortran.dg/import13.f90: New test. + +2025-07-16 Jeremy Rifkin <jeremy@rifkin.dev> + + PR c/82134 + * c-c++-common/attr-warn-unused-result-2.c: New test. + +2025-07-16 Haochen Jiang <haochen.jiang@intel.com> + + * gcc.target/i386/amxavx512-cvtrowd2ps-2.c: Add -mavx512fp16 to + use FP16 related intrins for convert. + * gcc.target/i386/amxavx512-cvtrowps2bf16-2.c: Ditto. + * gcc.target/i386/amxavx512-cvtrowps2ph-2.c: Ditto. + * gcc.target/i386/amxavx512-movrow-2.c: Ditto. + +2025-07-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/sat/sat_s_add-1-i16.c: Remove function-body + check and add no jmp label asm check. + * gcc.target/riscv/sat/sat_s_add-1-i32.c: + * gcc.target/riscv/sat/sat_s_add-1-i64.c: Ditto. + * gcc.target/riscv/sat/sat_s_add-1-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_add-2-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_add-2-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_add-2-i64.c: Ditto. + * gcc.target/riscv/sat/sat_s_add-2-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_add-3-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_add-3-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_add-3-i64.c: Ditto. + * gcc.target/riscv/sat/sat_s_add-3-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_add-4-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_add-4-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_add-4-i64.c: Ditto. + * gcc.target/riscv/sat/sat_s_add-4-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_add_imm-1-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_add_imm-1-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_add_imm-1-i64.c: Ditto. + * gcc.target/riscv/sat/sat_s_add_imm-1-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_add_imm-2-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_add_imm-2-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_add_imm-2-i64.c: Ditto. + * gcc.target/riscv/sat/sat_s_add_imm-2-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-1-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-1-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-1-i64.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-1-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-2-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-2-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-2-i64.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-2-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-3-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-3-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-3-i64.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-3-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-4-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-4-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-4-i64.c: Ditto. + * gcc.target/riscv/sat/sat_s_sub-4-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c: Ditto. + * gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-1-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-1-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-1-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-1-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-2-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-2-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-2-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-2-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-3-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-3-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-3-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-3-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-4-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-4-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-4-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-4-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-5-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-5-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-5-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-5-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-6-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-6-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-6-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-6-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-1-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-1-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-1-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-1-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-2-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-2-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-2-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-2-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-3-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-3-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-3-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-3-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-4-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-4-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-4-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_add_imm-4-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_mul-1-u16-from-u128.c: Ditto. + * gcc.target/riscv/sat/sat_u_mul-1-u32-from-u128.c: Ditto. + * gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c: Ditto. + * gcc.target/riscv/sat/sat_u_mul-1-u8-from-u128.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-1-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-1-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-1-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-1-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-10-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-10-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-10-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-10-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-11-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-11-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-11-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-11-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-12-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-12-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-12-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-12-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-2-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-2-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-2-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-2-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-3-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-3-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-3-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-3-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-4-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-4-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-4-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-4-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-5-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-5-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-5-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-5-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-6-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-6-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-6-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-6-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-7-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-7-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-7-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-7-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-8-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-8-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-8-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-8-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-9-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-9-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-9-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub-9-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u16-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u16-2.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u16-3.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u16-4.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u32-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u32-2.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u32-3.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u32-4.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u64-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u64-2.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u8-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u8-2.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c: Ditto. + * gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-1-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-1-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-1-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-1-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-2-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-2-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-2-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-2-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-3-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-3-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-3-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-3-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-4-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-4-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-4-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-4-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-5-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-5-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-5-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-5-u8.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-6-u16.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-6-u32.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-6-u64.c: Ditto. + * gcc.target/riscv/sat/sat_u_trunc-6-u8.c: Ditto. + +2025-07-16 Pan Li <pan2.li@intel.com> + + * gcc.target/riscv/rvv/autovec/avg.h: Add int128 type when + xlen == 64. + * gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c: + Suppress __int128 warning for run test. + * gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_data.h: Fix one incorrect + test data. + * gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_floor-run-1-i32-from-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i16.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i32.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i64.c: Ditto. + * gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c: New test. + * gcc.target/riscv/rvv/autovec/avg_floor-run-1-i64-from-i128.c: New test. + 2025-07-15 David Malcolm <dmalcolm@redhat.com> PR sarif-replay/120792 diff --git a/gcc/testsuite/cobol.dg/group2/_-static__compilation.cob b/gcc/testsuite/cobol.dg/group2/_-static__compilation.cob index 7843d3d..f344a84 100644 --- a/gcc/testsuite/cobol.dg/group2/_-static__compilation.cob +++ b/gcc/testsuite/cobol.dg/group2/_-static__compilation.cob @@ -1,7 +1,7 @@ *> { dg-do run } *> { dg-options "-static" } - *> { dg-output-file "group2/_-static__compilation.out" } - + *> { dg-prune-output {warning} } + *> { dg-output {hello, world} } IDENTIFICATION DIVISION. PROGRAM-ID. prog. PROCEDURE DIVISION. diff --git a/gcc/testsuite/cobol.dg/group2/_-static__compilation.out b/gcc/testsuite/cobol.dg/group2/_-static__compilation.out deleted file mode 100644 index ae0e511..0000000 --- a/gcc/testsuite/cobol.dg/group2/_-static__compilation.out +++ /dev/null @@ -1,2 +0,0 @@ -hello, world - diff --git a/gcc/testsuite/g++.dg/coroutines/torture/pr121219.C b/gcc/testsuite/g++.dg/coroutines/torture/pr121219.C new file mode 100644 index 0000000..d1e7cb1 --- /dev/null +++ b/gcc/testsuite/g++.dg/coroutines/torture/pr121219.C @@ -0,0 +1,149 @@ +// PR c++/121219 +// { dg-do run } + +#include <coroutine> +#ifdef OUTPUT +#include <iostream> +#endif +#include <stdexcept> + +struct Task { + struct promise_type; + using handle_type = std::coroutine_handle<promise_type>; + + struct promise_type { + Task* task_; + int result_; + + static void* operator new(std::size_t size) noexcept { + void* p = ::operator new(size, std::nothrow); +#ifdef OUTPUT + std::cerr << "operator new (no arg) " << size << " -> " << p << std::endl; +#endif + return p; + } + static void operator delete(void* ptr) noexcept { + return ::operator delete(ptr, std::nothrow); + } +#if 1 // change to 0 to fix crash + static Task get_return_object_on_allocation_failure() noexcept { +#ifdef OUTPUT + std::cerr << "get_return_object_on_allocation_failure" << std::endl; +#endif + return Task(nullptr); + } +#endif + + auto get_return_object() { +#ifdef OUTPUT + std::cerr << "get_return_object" << std::endl; +#endif + return Task{handle_type::from_promise(*this)}; + } + + auto initial_suspend() { +#ifdef OUTPUT + std::cerr << "initial_suspend" << std::endl; +#endif + return std::suspend_always{}; + } + + auto final_suspend() noexcept { +#ifdef OUTPUT + std::cerr << "final_suspend" << std::endl; +#endif + return std::suspend_never{}; // Coroutine auto-destructs + } + + ~promise_type() { + if (task_) { +#ifdef OUTPUT + std::cerr << "promise_type destructor: Clearing Task handle" << std::endl; +#endif + task_->h_ = nullptr; + } + } + + void unhandled_exception() { +#ifdef OUTPUT + std::cerr << "unhandled_exception" << std::endl; +#endif + std::terminate(); + } + + void return_value(int value) { +#ifdef OUTPUT + std::cerr << "return_value: " << value << std::endl; +#endif + result_ = value; + if (task_) { + task_->result_ = value; + task_->completed_ = true; + } + } + }; + + handle_type h_; + int result_; + bool completed_ = false; + + Task(handle_type h) : h_(h) { +#ifdef OUTPUT + std::cerr << "Task constructor" << std::endl; +#endif + if (h_) { + h_.promise().task_ = this; // Link promise to Task + } + } + + ~Task() { +#ifdef OUTPUT + std::cerr << "~Task destructor" << std::endl; +#endif + // Only destroy handle if still valid (coroutine not completed) + if (h_) { +#ifdef OUTPUT + std::cerr << "Destroying coroutine handle" << std::endl; +#endif + h_.destroy(); + } + } + + bool done() const { + return completed_ || !h_ || h_.done(); + } + + void resume() { +#ifdef OUTPUT + std::cerr << "Resuming task" << std::endl; +#endif + if (h_) h_.resume(); + } + + int result() const { + if (!done()) throw std::runtime_error("Result not available"); + return result_; + } +}; + +Task my_coroutine() { +#ifdef OUTPUT + std::cerr << "Inside my_coroutine" << std::endl; +#endif + co_return 42; +} + +int main() { + auto task = my_coroutine(); + while (!task.done()) { +#ifdef OUTPUT + std::cerr << "Resuming task in main" << std::endl; +#endif + task.resume(); + } +#ifdef OUTPUT + std::cerr << "Task completed in main, printing result" << std::endl; +#endif + if (task.result() != 42) + __builtin_abort (); +} diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-array29.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-array29.C new file mode 100644 index 0000000..714d050 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-array29.C @@ -0,0 +1,13 @@ +// PR c++/87097 +// { dg-do compile { target c++11 } } + +struct A { + constexpr A() : data() {} + struct X { int n; }; + X data[2]; +}; + +static_assert((A(), true), ""); +static_assert(A().data[0].n == 0, ""); +static_assert(A().data[1].n == 0, ""); +constexpr A x; diff --git a/gcc/testsuite/g++.dg/cpp23/explicit-obj-lambda18.C b/gcc/testsuite/g++.dg/cpp23/explicit-obj-lambda18.C new file mode 100644 index 0000000..d54a93d --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp23/explicit-obj-lambda18.C @@ -0,0 +1,12 @@ +// PR c++/114632 +// { dg-do compile { target c++23 } } + +struct S {}; + +auto lambda = [](this auto& self, const int x) /* -> void */ {}; + +int main() +{ + void (*func)(S&, int) = lambda; // { dg-error "" } + return 0; +} diff --git a/gcc/testsuite/g++.dg/cpp23/static-operator-call7.C b/gcc/testsuite/g++.dg/cpp23/static-operator-call7.C new file mode 100644 index 0000000..7c381e6 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp23/static-operator-call7.C @@ -0,0 +1,12 @@ +// PR c++/114632 +// { dg-do compile { target c++23 } } + +struct S {}; + +auto lambda = [](auto, const int x) static /* -> void */ {}; + +int main() +{ + void (*func)(int, int) = lambda; + return 0; +} diff --git a/gcc/testsuite/g++.dg/cpp26/constexpr-new4.C b/gcc/testsuite/g++.dg/cpp26/constexpr-new4.C new file mode 100644 index 0000000..12d8a46 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp26/constexpr-new4.C @@ -0,0 +1,21 @@ +// PR c++/121068 +// { dg-do compile { target c++26 } } + +constexpr void *operator new (__SIZE_TYPE__, void *p) { return p; } +constexpr void *operator new[] (__SIZE_TYPE__, void *p) { return p; } + +consteval int +foo() +{ + using T = int; + union { T arr[3]; }; + new(arr) T[3]; // makes arr active + for (int i = 0; i < 3; ++i) + arr[i].~T(); + + new (arr + 2) T{10}; // A + + return 1; +}; + +constexpr int g = foo(); diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-traits3.C b/gcc/testsuite/g++.dg/cpp2a/concepts-traits3.C index 3e87da4..90d859a 100644 --- a/gcc/testsuite/g++.dg/cpp2a/concepts-traits3.C +++ b/gcc/testsuite/g++.dg/cpp2a/concepts-traits3.C @@ -1,49 +1,58 @@ // PR c++/100474 // { dg-do compile { target c++20 } } -struct S { S() = delete; S(const S&); }; +struct S { S() = delete; S(const S&); }; // { dg-line S } template<class T> concept Aggregate = __is_aggregate(T); -// { dg-message "'S' is not an aggregate" "" { target *-*-* } .-1 } +// { dg-message "'S' is not an aggregate" "" { target *-*-* } S } template<class T> concept TriviallyCopyable = __is_trivially_copyable(T); -// { dg-message "'S' is not trivially copyable" "" { target *-*-* } .-1 } +// { dg-message "'S' is not trivially copyable" "" { target *-*-* } S } template<class T, class U> concept Assignable = __is_assignable(T, U); -// { dg-message "'S' is not assignable from 'int'" "" { target *-*-* } .-1 } +// { dg-message "'S' is not assignable from 'int', because" "" { target *-*-* } .-1 } +// { dg-error "no match for 'operator='" "" { target *-*-* } .-2 } template<class T, class U> concept TriviallyAssignable = __is_trivially_assignable(T, U); // { dg-message "'S' is not trivially assignable from 'int'" "" { target *-*-* } .-1 } +// { dg-error "no match for 'operator='" "" { target *-*-* } .-2 } template<class T, class U> concept NothrowAssignable = __is_nothrow_assignable(T, U); // { dg-message "'S' is not nothrow assignable from 'int'" "" { target *-*-* } .-1 } +// { dg-error "no match for 'operator='" "" { target *-*-* } .-2 } template<class T, class... Args> concept Constructible = __is_constructible(T, Args...); // { dg-message "'S' is not default constructible" "" { target *-*-* } .-1 } -// { dg-message "'S' is not constructible from 'int'" "" { target *-*-* } .-2 } -// { dg-message "'S' is not constructible from 'int, char'" "" { target *-*-* } .-3 } +// { dg-error "use of deleted function 'S::S\\(\\)'" "" { target *-*-* } .-2 } +// { dg-message "'S' is not constructible from 'int'" "" { target *-*-* } .-3 } +// { dg-message "'S' is not constructible from 'int, char'" "" { target *-*-* } .-4 } +// { dg-error "no matching function for call to 'S::S" "" { target *-*-* } .-5 } template<class T, class... Args> concept TriviallyConstructible = __is_trivially_constructible(T, Args...); // { dg-message "'S' is not trivially default constructible" "" { target *-*-* } .-1 } -// { dg-message "'S' is not trivially constructible from 'int'" "" { target *-*-* } .-2 } -// { dg-message "'S' is not trivially constructible from 'int, char'" "" { target *-*-* } .-3 } +// { dg-error "use of deleted function 'S::S\\(\\)'" "" { target *-*-* } .-2 } +// { dg-message "'S' is not trivially constructible from 'int'" "" { target *-*-* } .-3 } +// { dg-message "'S' is not trivially constructible from 'int, char'" "" { target *-*-* } .-4 } +// { dg-error "no matching function for call to 'S::S" "" { target *-*-* } .-5 } template<class T, class... Args> concept NothrowConstructible = __is_nothrow_constructible(T, Args...); // { dg-message "'S' is not nothrow default constructible" "" { target *-*-* } .-1 } -// { dg-message "'S' is not nothrow constructible from 'int'" "" { target *-*-* } .-2 } -// { dg-message "'S' is not nothrow constructible from 'int, char'" "" { target *-*-* } .-3 } +// { dg-error "use of deleted function 'S::S\\(\\)'" "" { target *-*-* } .-2 } +// { dg-message "'S' is not nothrow constructible from 'int'" "" { target *-*-* } .-3 } +// { dg-message "'S' is not nothrow constructible from 'int, char'" "" { target *-*-* } .-4 } +// { dg-error "no matching function for call to 'S::S" "" { target *-*-* } .-5 } template<class T> concept UniqueObjReps = __has_unique_object_representations(T); -// { dg-message "'S' does not have unique object representations" "" { target *-*-* } .-1 } +// { dg-message "'S' does not have unique object representations" "" { target *-*-* } S } static_assert(Aggregate<S>); // { dg-error "assert" } static_assert(TriviallyCopyable<S>); // { dg-error "assert" } diff --git a/gcc/testsuite/g++.dg/cpp2a/concepts-traits4.C b/gcc/testsuite/g++.dg/cpp2a/concepts-traits4.C new file mode 100644 index 0000000..caad816 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp2a/concepts-traits4.C @@ -0,0 +1,77 @@ +// PR c++/117294 +// { dg-do compile { target c++20 } } +// { dg-additional-options "-fconcepts-diagnostics-depth=2" } + +template <typename T> struct norm + { static constexpr bool value = __is_constructible(T); }; +template <typename T> constexpr bool norm_v = __is_constructible(T); + +template <typename T> struct part + { static constexpr bool value = __is_constructible(T); }; +template <typename T> struct part<T*> + { static constexpr bool value = false; }; +template <typename T> struct part<const T> + { static constexpr bool value = __is_same(T, void); }; +template <typename T> constexpr bool part_v = __is_constructible(T); +template <typename T> constexpr bool part_v<T*> = false; +template <typename T> constexpr bool part_v<const T> = __is_same(T, void); + +template <typename T> struct expl + { static constexpr bool value = __is_constructible(T); }; +template <> struct expl<int*> + { static constexpr bool value = false; }; +template <> struct expl<const int> + { static constexpr bool value = __is_same(int, void); }; +template <typename T> constexpr bool expl_v = __is_constructible(T); +template <> constexpr bool expl_v<int*> = false; +template <> constexpr bool expl_v<const int> = __is_same(int, void); + +template <typename T> concept test_norm = norm<T>::value; // { dg-line norm } +template <typename T> concept test_part = part<T>::value; // { dg-line part } +template <typename T> concept test_expl = expl<T>::value; // { dg-line expl } +template <typename T> concept test_norm_v = norm_v<T>; // { dg-line norm_v } +template <typename T> concept test_part_v = part_v<T>; // { dg-line part_v } +template <typename T> concept test_expl_v = expl_v<T>; // { dg-line expl_v } + +static_assert(test_norm<void>); // { dg-error "assert" } +static_assert(test_part<void>); // { dg-error "assert" } +static_assert(test_expl<void>); // { dg-error "assert" } +static_assert(test_norm_v<void>); // { dg-error "assert" } +static_assert(test_part_v<void>); // { dg-error "assert" } +static_assert(test_expl_v<void>); // { dg-error "assert" } +// { dg-message "'void' is not default constructible" "" { target *-*-* } norm } +// { dg-message "'void' is not default constructible" "" { target *-*-* } part } +// { dg-message "'void' is not default constructible" "" { target *-*-* } expl } +// { dg-message "'void' is not default constructible" "" { target *-*-* } norm_v } +// { dg-message "'void' is not default constructible" "" { target *-*-* } part_v } +// { dg-message "'void' is not default constructible" "" { target *-*-* } expl_v } +// { dg-prune-output "'void' is incomplete" } + +static_assert(test_part<int*>); // { dg-error "assert" } +static_assert(test_expl<int*>); // { dg-error "assert" } +static_assert(test_part_v<int*>); // { dg-error "assert" } +static_assert(test_expl_v<int*>); // { dg-error "assert" } +// { dg-message ".with T = int\\*.. evaluated to .false." "" { target *-*-* } part } +// { dg-message ".with T = int\\*.. evaluated to .false." "" { target *-*-* } expl } +// { dg-message ".with T = int\\*.. evaluated to .false." "" { target *-*-* } part_v } +// { dg-message ".with T = int\\*.. evaluated to .false." "" { target *-*-* } expl_v } + +static_assert(test_part<const int>); // { dg-error "assert" } +static_assert(test_part_v<const int>); // { dg-error "assert" } +// { dg-message "'int' is not the same as 'void'" "" { target *-*-* } part } +// { dg-message "'int' is not the same as 'void'" "" { target *-*-* } part_v } + +struct S { S(int); }; +static_assert(requires { requires test_norm<S>; }); // { dg-error "assert" } +static_assert(requires { requires test_part<S>; }); // { dg-error "assert" } +static_assert(requires { requires test_expl<S>; }); // { dg-error "assert" } +static_assert(requires { requires test_norm_v<S>; }); // { dg-error "assert" } +static_assert(requires { requires test_part_v<S>; }); // { dg-error "assert" } +static_assert(requires { requires test_expl_v<S>; }); // { dg-error "assert" } +// { dg-message "'S' is not default constructible" "" { target *-*-* } norm } +// { dg-message "'S' is not default constructible" "" { target *-*-* } part } +// { dg-message "'S' is not default constructible" "" { target *-*-* } expl } +// { dg-message "'S' is not default constructible" "" { target *-*-* } norm_v } +// { dg-message "'S' is not default constructible" "" { target *-*-* } part_v } +// { dg-message "'S' is not default constructible" "" { target *-*-* } expl_v } +// { dg-prune-output "no matching function for call" } diff --git a/gcc/testsuite/g++.dg/cpp2a/constexpr-union6.C b/gcc/testsuite/g++.dg/cpp2a/constexpr-union6.C index 00bda53..ab8c979 100644 --- a/gcc/testsuite/g++.dg/cpp2a/constexpr-union6.C +++ b/gcc/testsuite/g++.dg/cpp2a/constexpr-union6.C @@ -45,9 +45,9 @@ constexpr int test5() { union { int data[1]; } u; - std::construct_at(u.data, 0); // { dg-message "in .constexpr. expansion" } + std::construct_at(u.data, 0); // { dg-bogus "in .constexpr. expansion" } return 0; } -constexpr int x5 = test5(); // { dg-message "in .constexpr. expansion" } +constexpr int x5 = test5(); // { dg-bogus "in .constexpr. expansion" } // { dg-error "accessing (uninitialized member|.* member instead of)" "" { target *-*-* } 0 } diff --git a/gcc/testsuite/g++.dg/diagnostic/static_assert5.C b/gcc/testsuite/g++.dg/diagnostic/static_assert5.C new file mode 100644 index 0000000..16681b2 --- /dev/null +++ b/gcc/testsuite/g++.dg/diagnostic/static_assert5.C @@ -0,0 +1,70 @@ +// PR c++/117294 +// { dg-do compile { target c++14 } } + +template <typename T> struct norm + { static constexpr bool value = __is_constructible(T); }; +template <typename T> constexpr bool norm_v = __is_constructible(T); + +template <typename T> struct part + { static constexpr bool value = __is_constructible(T); }; +template <typename T> struct part<T*> + { static constexpr bool value = false; }; +template <typename T> struct part<const T> + { static constexpr bool value = __is_same(T, void); }; +template <typename T> constexpr bool part_v = __is_constructible(T); +template <typename T> constexpr bool part_v<T*> = false; +template <typename T> constexpr bool part_v<const T> = __is_same(T, void); + +template <typename T> struct expl + { static constexpr bool value = __is_constructible(T); }; +template <> struct expl<int*> + { static constexpr bool value = false; }; +template <> struct expl<const int> + { static constexpr bool value = __is_same(int, void); }; +template <typename T> constexpr bool expl_v = __is_constructible(T); +template <> constexpr bool expl_v<int*> = false; +template <> constexpr bool expl_v<const int> = __is_same(int, void); + +// === Primary template can give customised diagnostics when using traits +static_assert(norm<void>::value); // { dg-error "assert" } +// { dg-message "'void' is not default constructible" "" { target *-*-* } .-1 } +static_assert(part<void>::value); // { dg-error "assert" } +// { dg-message "'void' is not default constructible" "" { target *-*-* } .-1 } +static_assert(expl<void>::value); // { dg-error "assert" } +// { dg-message "'void' is not default constructible" "" { target *-*-* } .-1 } +static_assert(norm_v<void>); // { dg-error "assert" } +// { dg-message "'void' is not default constructible" "" { target *-*-* } .-1 } +static_assert(part_v<void>); // { dg-error "assert" } +// { dg-message "'void' is not default constructible" "" { target *-*-* } .-1 } +static_assert(expl_v<void>); // { dg-error "assert" } +// { dg-message "'void' is not default constructible" "" { target *-*-* } .-1 } + +// { dg-prune-output "'void' is incomplete" } + + +// === Specialisations don't customise just because primary template had trait +static_assert(part<int*>::value); // { dg-error "assert" } +// { dg-bogus "default constructible" "" { target *-*-* } .-1 } +static_assert(expl<int*>::value); // { dg-error "assert" } +// { dg-bogus "default constructible" "" { target *-*-* } .-1 } +static_assert(part_v<int*>); // { dg-error "assert" } +// { dg-bogus "default constructible" "" { target *-*-* } .-1 } +static_assert(expl_v<int*>); // { dg-error "assert" } +// { dg-bogus "default constructible" "" { target *-*-* } .-1 } + + +// === But partial specialisations actually using a trait can customise +static_assert(part<const int>::value); // { dg-error "assert" } +// { dg-message "'int' is not the same as 'void'" "" { target *-*-* } .-1 } +static_assert(part_v<const int>); // { dg-error "assert" } +// { dg-message "'int' is not the same as 'void'" "" { target *-*-* } .-1 } + + +// === For these cases, we no longer know that the error was caused by the trait +// === because it's been folded away before we process the failure. +static_assert(expl<const int>::value); // { dg-error "assert" } +// { dg-bogus "because" "" { target *-*-* } .-1 } +static_assert(expl_v<const int>); // { dg-error "assert" } +// { dg-bogus "because" "" { target *-*-* } .-1 } +static_assert(__is_constructible(void)); // { dg-error "assert" } +// { dg-bogus "because" "" { target *-*-* } .-1 } diff --git a/gcc/testsuite/g++.dg/ext/has_virtual_destructor2.C b/gcc/testsuite/g++.dg/ext/has_virtual_destructor2.C new file mode 100644 index 0000000..14eea80 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/has_virtual_destructor2.C @@ -0,0 +1,27 @@ +// { dg-do compile { target c++11 } } + +template <typename T> struct has_virtual_destructor { + static constexpr bool value = __has_virtual_destructor(T); +}; + +static_assert(has_virtual_destructor<int>::value, ""); // { dg-error "assert" } +// { dg-message "'int' does not have a virtual destructor" "" { target *-*-* } .-1 } + +struct A {}; // { dg-message "'A' does not have a virtual destructor" } +static_assert(has_virtual_destructor<A>::value, ""); // { dg-error "assert" } + +struct B { + ~B(); // { dg-message "'B' does not have a virtual destructor" } +}; +static_assert(has_virtual_destructor<B>::value, ""); // { dg-error "assert" } + +struct C { // { dg-bogus "" } + virtual ~C(); // { dg-bogus "" } +}; +static_assert(has_virtual_destructor<C[5]>::value, ""); // { dg-error "assert" } +// { dg-message "'C \\\[5\\\]' does not have a virtual destructor" "" { target *-*-* } .-1 } + +union U { // { dg-message "'U' does not have a virtual destructor" } + ~U(); +}; +static_assert(has_virtual_destructor<U>::value, ""); // { dg-error "assert" } diff --git a/gcc/testsuite/g++.dg/ext/is_assignable2.C b/gcc/testsuite/g++.dg/ext/is_assignable2.C new file mode 100644 index 0000000..b346d7b --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/is_assignable2.C @@ -0,0 +1,36 @@ +// { dg-do compile { target c++11 } } + +template <typename T> +struct is_copy_assignable { + static constexpr bool value = __is_assignable(T&, const T&); +}; + +static_assert(is_copy_assignable<const int>::value, ""); // { dg-error "assert" } +// { dg-error "assignment to read-only type 'const int'" "" { target *-*-* } .-1 } + +struct A { + void operator=(A) = delete; // { dg-message "declared here" } +}; +static_assert(is_copy_assignable<A>::value, ""); // { dg-error "assert" } +// { dg-message "is not assignable" "" { target *-*-* } .-1 } +// { dg-error "use of deleted function" "" { target *-*-* } .-2 } + +template <typename T> +struct is_nothrow_copy_assignable { + static constexpr bool value = __is_nothrow_assignable(T&, const T&); +}; +struct B { + void operator=(const B&); // { dg-message "noexcept" } +}; +static_assert(is_nothrow_copy_assignable<B>::value, ""); // { dg-error "assert" } +// { dg-message "is not nothrow assignable" "" { target *-*-* } .-1 } + +template <typename T> +struct is_trivially_copy_assignable { + static constexpr bool value = __is_trivially_assignable(T&, const T&); +}; +struct C { + void operator=(const C&); // { dg-message "non-trivial" } +}; +static_assert(is_trivially_copy_assignable<C>::value, ""); // { dg-error "assert" } +// { dg-message "is not trivially assignable" "" { target *-*-* } .-1 } diff --git a/gcc/testsuite/g++.dg/ext/is_constructible9.C b/gcc/testsuite/g++.dg/ext/is_constructible9.C new file mode 100644 index 0000000..5448878 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/is_constructible9.C @@ -0,0 +1,60 @@ +// { dg-do compile { target c++11 } } + +template <typename T, typename... Args> +struct is_constructible { + static constexpr bool value = __is_constructible(T, Args...); +}; + +static_assert(is_constructible<void>::value, ""); // { dg-error "assert" } +// { dg-message "'void' is not default constructible, because" "" { target *-*-* } .-1 } +// { dg-error "'void' is incomplete" "" { target *-*-* } .-2 } + +static_assert(is_constructible<int&, const int&>::value, ""); // { dg-error "assert" } +// { dg-message "'int&' is not constructible from 'const int&', because" "" { target *-*-* } .-1 } +// { dg-error "discards qualifiers" "" { target *-*-* } .-2 } + +static_assert(is_constructible<int, int, int>::value, ""); // { dg-error "assert" } +// { dg-message "'int' is not constructible from 'int, int', because" "" { target *-*-* } .-1 } +// { dg-error "too many initializers for non-class type 'int'" "" { target *-*-* } .-2 } + +struct A { + A(int); // { dg-message "candidate" } +}; +static_assert(is_constructible<A, int, int>::value, ""); // { dg-error "assert" } +// { dg-message "'A' is not constructible from 'int, int', because" "" { target *-*-* } .-1 } +// { dg-error "no matching function for call to" "" { target *-*-* } .-2 } + +template <typename T, typename... Args> +struct is_nothrow_constructible { + static constexpr bool value = __is_nothrow_constructible(T, Args...); +}; + +struct B { + B(int); // { dg-message "candidate" } +}; +static_assert(is_nothrow_constructible<B>::value, ""); // { dg-error "assert" } +// { dg-message "'B' is not nothrow default constructible, because" "" { target *-*-* } .-1 } +// { dg-error "no matching function for call to" "" { target *-*-* } .-2 } + +struct C { + C(int); // { dg-message "noexcept" } +}; +static_assert(is_nothrow_constructible<C, int>::value, ""); // { dg-error "assert" } +// { dg-message "'C' is not nothrow constructible from 'int', because" "" { target *-*-* } .-1 } + +template <typename T, typename... Args> +struct is_trivially_constructible { + static constexpr bool value = __is_trivially_constructible(T, Args...); +}; + +struct D { + D(); // { dg-message "non-trivial" } +}; +static_assert(is_trivially_constructible<D>::value, ""); // { dg-error "assert" } +// { dg-message "'D' is not trivially default constructible, because" "" { target *-*-* } .-1 } + +struct E { + operator int(); // { dg-message "non-trivial" } +}; +static_assert(is_trivially_constructible<int, E>::value, ""); // { dg-error "assert" } +// { dg-message "'int' is not trivially constructible from 'E', because" "" { target *-*-* } .-1 } diff --git a/gcc/testsuite/g++.dg/ext/is_convertible7.C b/gcc/testsuite/g++.dg/ext/is_convertible7.C new file mode 100644 index 0000000..b38fc04 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/is_convertible7.C @@ -0,0 +1,29 @@ +// { dg-do compile { target c++11 } } + +template <typename T, typename U> +struct is_convertible { + static constexpr bool value = __is_convertible(T, U); +}; + +static_assert(is_convertible<int*, int>::value, ""); // { dg-error "assert" } +// { dg-error "invalid conversion" "" { target *-*-* } .-1 } + +static_assert(is_convertible<int(), double (*)()>::value, ""); // { dg-error "assert" } +// { dg-error "invalid conversion" "" { target *-*-* } .-1 } + +struct A { + explicit A(int); +}; +static_assert(is_convertible<int, A>::value, ""); // { dg-error "assert" } +// { dg-error "could not convert 'int' to 'A'" "" { target *-*-* } .-1 } + +template <typename T, typename U> +struct is_nothrow_convertible { + static constexpr bool value = __is_nothrow_convertible(T, U); +}; + +struct B { + B(int); // { dg-message "noexcept" } +}; +static_assert(is_nothrow_convertible<int, B>::value, ""); // { dg-error "assert" } +// { dg-message "'int' is not nothrow convertible from 'B', because" "" { target *-*-* } .-1 } diff --git a/gcc/testsuite/g++.dg/ext/is_destructible3.C b/gcc/testsuite/g++.dg/ext/is_destructible3.C new file mode 100644 index 0000000..a8501d6 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/is_destructible3.C @@ -0,0 +1,65 @@ +// { dg-do compile { target c++11 } } + +template <typename T> +struct is_destructible { + static constexpr bool value = __is_destructible(T); +}; + +static_assert(is_destructible<void>::value, ""); // { dg-error "assert" } +// { dg-message "'void' is not destructible, because" "" { target *-*-* } .-1 } +// { dg-error "'void' is incomplete" "" { target *-*-* } .-2 } + +struct A { + ~A() = delete; // { dg-message "declared here" } +}; +static_assert(is_destructible<A>::value, ""); // { dg-error "assert" } +// { dg-message "'A' is not destructible, because" "" { target *-*-* } .-1 } +// { dg-error "use of deleted function" "" { target *-*-* } .-2 } + +struct B { +private: + ~B(); // { dg-message "declared private here" } +}; +static_assert(is_destructible<B>::value, ""); // { dg-error "assert" } +// { dg-message "'B' is not destructible, because" "" { target *-*-* } .-1 } +// { dg-error "private within this context" "" { target *-*-* } .-2 } + +template <typename T> +struct is_nothrow_destructible { + static constexpr bool value = __is_nothrow_destructible(T); +}; + +struct C { + ~C() noexcept(false); // { dg-message "noexcept" } +}; +static_assert(is_nothrow_destructible<C>::value, ""); // { dg-error "assert" } +// { dg-message "'C' is not nothrow destructible, because" "" { target *-*-* } .-1 } + +struct D { +private: + ~D() {} // { dg-message "declared private here" } +}; +static_assert(is_nothrow_destructible<D>::value, ""); // { dg-error "assert" } +// { dg-message "'D' is not nothrow destructible, because" "" { target *-*-* } .-1 } +// { dg-error "private within this context" "" { target *-*-* } .-2 } + +template <typename T> +struct is_trivially_destructible { + static constexpr bool value = __is_trivially_destructible(T); +}; + +struct E { + ~E(); +}; +struct F { E d; }; // { dg-message "non-trivial" } +static_assert(is_trivially_destructible<F>::value, ""); // { dg-error "assert" } +// { dg-message "'F' is not trivially destructible, because" "" { target *-*-* } .-1 } + +struct G { +private: + ~G(); // { dg-message "declared private here" } +}; +struct H { G g; }; // { dg-error "private within this context" } +static_assert(is_trivially_destructible<H>::value, ""); // { dg-error "assert" } +// { dg-message "'H' is not trivially destructible, because" "" { target *-*-* } .-1 } +// { dg-error "use of deleted function" "" { target *-*-* } .-2 } diff --git a/gcc/testsuite/g++.dg/ext/is_invocable5.C b/gcc/testsuite/g++.dg/ext/is_invocable5.C new file mode 100644 index 0000000..460eed5 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/is_invocable5.C @@ -0,0 +1,15 @@ +// PR c++/121055 +// { dg-do compile { target c++11 } } +// { dg-skip-if "requires hosted libstdc++ for functional function" { ! hostedlib } } + +#include <functional> + +#define SA(X) static_assert((X),#X) + +struct F; + +SA( __is_invocable(void (F::*)() &, std::reference_wrapper<F>) ); +SA( ! __is_invocable(void (F::*)() &&, std::reference_wrapper<F>) ); + +SA( __is_invocable(void (F::*)(int) &, std::reference_wrapper<F>, int) ); +SA( ! __is_invocable(void (F::*)(int) &&, std::reference_wrapper<F>, int) ); diff --git a/gcc/testsuite/g++.dg/ext/is_invocable6.C b/gcc/testsuite/g++.dg/ext/is_invocable6.C new file mode 100644 index 0000000..64c5c76 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/is_invocable6.C @@ -0,0 +1,45 @@ +// { dg-do compile { target c++11 } } + +template <typename F, typename... Args> +struct is_invocable { + static constexpr bool value = __is_invocable(F, Args...); +}; + +static_assert(is_invocable<int>::value, ""); // { dg-error "assert" } +// { dg-message "'int' is not invocable, because" "" { target *-*-* } .-1 } +// { dg-error "'int' cannot be used as a function" "" { target *-*-* } .-2 } + +static_assert(is_invocable<void(*)(), int>::value, ""); // { dg-error "assert" } +// { dg-message "'void \[^'\]*' is not invocable by 'int', because" "" { target *-*-* } .-1 } +// { dg-error "too many arguments" "" { target *-*-* } .-2 } + +static_assert(is_invocable<void(void*), void() const>::value, ""); // { dg-error "assert" } +// { dg-message "'void.void..' is not invocable by 'void.. const', because" "" { target *-*-* } .-1 } +// { dg-error "qualified function type" "" { target *-*-* } .-2 } + +struct A {}; +static_assert(is_invocable<const A&&, int, double>::value, ""); // { dg-error "assert" } +// { dg-message "'const A&&' is not invocable by 'int, double', because" "" { target *-*-* } .-1 } +// { dg-error "no match for call to " "" { target *-*-* } .-2 } + +struct B { + void operator()() = delete; // { dg-message "declared here" } +}; +static_assert(is_invocable<B>::value, ""); // { dg-error "assert" } +// { dg-message "'B' is not invocable, because" "" { target *-*-* } .-1 } +// { dg-error "use of deleted function" "" { target *-*-* } .-2 } + +template <typename F, typename... Args> +struct is_nothrow_invocable { + static constexpr bool value = __is_nothrow_invocable(F, Args...); +}; + +static_assert(is_nothrow_invocable<void(*)()>::value, ""); // { dg-error "assert" } +// { dg-message "'void \[^'\]*' is not nothrow invocable, because" "" { target *-*-* } .-1 } +// { dg-message "'void \[^'\]*' is not 'noexcept'" "" { target *-*-* } .-2 } + +struct C { + int operator()(int, double) const; // { dg-message "noexcept" } +}; +static_assert(is_nothrow_invocable<const C&, int, int>::value, ""); // { dg-error "assert" } +// { dg-message "'const C&' is not nothrow invocable by 'int, int', because" "" { target *-*-* } .-1 } diff --git a/gcc/testsuite/g++.dg/ext/is_virtual_base_of_diagnostic2.C b/gcc/testsuite/g++.dg/ext/is_virtual_base_of_diagnostic2.C new file mode 100644 index 0000000..ac28121 --- /dev/null +++ b/gcc/testsuite/g++.dg/ext/is_virtual_base_of_diagnostic2.C @@ -0,0 +1,13 @@ +// { dg-do compile { target c++11 } } + +template <typename T, typename U> +struct is_virtual_base_of { + static constexpr bool value = __builtin_is_virtual_base_of(T, U); +}; + +static_assert(is_virtual_base_of<int, int>::value, ""); // { dg-error "assert" } +// { dg-message "'int' is not a virtual base of 'int'" "" { target *-*-* } .-1 } + +struct A {}; // { dg-message "'A' is not a virtual base of 'B'" } +struct B : A {}; // { dg-message "declared here" } +static_assert(is_virtual_base_of<A, B>::value, ""); // { dg-error "assert" } diff --git a/gcc/testsuite/g++.dg/lookup/operator-8.C b/gcc/testsuite/g++.dg/lookup/operator-8.C index 64d8a97..7fe6a57 100644 --- a/gcc/testsuite/g++.dg/lookup/operator-8.C +++ b/gcc/testsuite/g++.dg/lookup/operator-8.C @@ -16,7 +16,8 @@ struct A { template<class T> void f() { A a; - (void)(a != 0, 0 != a); // { dg-bogus "deleted" "" { xfail *-*-* } } + (void)(a != 0); // We only handle this simple case, after PR121179 + (void)(0 != a); // { dg-bogus "deleted" "" { xfail *-*-* } } (void)(a < 0, 0 < a); // { dg-bogus "deleted" "" { xfail *-*-* } } (void)(a <= 0, 0 <= a); // { dg-bogus "deleted" "" { xfail *-*-* } } (void)(a > 0, 0 > a); // { dg-bogus "deleted" "" { xfail *-*-* } } @@ -31,4 +32,10 @@ bool operator<=(A, int) = delete; bool operator>(A, int) = delete; bool operator>=(A, int) = delete; +bool operator!=(int, A) = delete; +bool operator<(int, A) = delete; +bool operator<=(int, A) = delete; +bool operator>(int, A) = delete; +bool operator>=(int, A) = delete; + template void f<int>(); diff --git a/gcc/testsuite/g++.dg/missing-return.C b/gcc/testsuite/g++.dg/missing-return.C index 5f8e2cc..f6934b0 100644 --- a/gcc/testsuite/g++.dg/missing-return.C +++ b/gcc/testsuite/g++.dg/missing-return.C @@ -5,4 +5,6 @@ int foo(int a) { } /* { dg-warning "no return statement" } */ -/* { dg-final { scan-tree-dump "__builtin_unreachable" "optimized" } } */ +/* For targets without traps, it will be an infinite loop */ +/* { dg-final { scan-tree-dump "__builtin_unreachable" "optimized" { target trap } } } */ +/* { dg-final { scan-tree-dump "goto <" "optimized" { target { ! trap } } } } */ diff --git a/gcc/testsuite/g++.dg/modules/internal-14_a.C b/gcc/testsuite/g++.dg/modules/internal-14_a.C new file mode 100644 index 0000000..07eb965 --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/internal-14_a.C @@ -0,0 +1,17 @@ +// PR c++/120412 +// { dg-additional-options "-fmodules -std=c++20 -Wtemplate-names-tu-local" } +// { dg-module-cmi m:part } + +export module m:part; + +export template <typename F> +auto fun1(F) { + return true; +} + +using Dodgy = decltype([]{}); + +export template <typename T> +auto fun2(T&&) { // { dg-warning "TU-local" } + return fun1(Dodgy{}); +} diff --git a/gcc/testsuite/g++.dg/modules/internal-14_b.C b/gcc/testsuite/g++.dg/modules/internal-14_b.C new file mode 100644 index 0000000..ad3b09d --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/internal-14_b.C @@ -0,0 +1,6 @@ +// PR c++/120412 +// { dg-additional-options "-fmodules -std=c++20 -Wtemplate-names-tu-local" } +// { dg-module-cmi m } + +export module m; +export import :part; diff --git a/gcc/testsuite/g++.dg/modules/internal-14_c.C b/gcc/testsuite/g++.dg/modules/internal-14_c.C new file mode 100644 index 0000000..4f8e785c --- /dev/null +++ b/gcc/testsuite/g++.dg/modules/internal-14_c.C @@ -0,0 +1,9 @@ +// PR c++/120412 +// { dg-additional-options "-fmodules -std=c++20" } + +import m; + +int main() { + // { dg-error "instantiation exposes TU-local entity '(fun1|Dodgy)'" "" { target *-*-* } 0 } + fun2(123); // { dg-message "required from here" } +} diff --git a/gcc/testsuite/g++.dg/torture/pr120119-1.C b/gcc/testsuite/g++.dg/torture/pr120119-1.C new file mode 100644 index 0000000..1206feb --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/pr120119-1.C @@ -0,0 +1,15 @@ +// { dg-do compile } +// { dg-additional-options "-mcpu=cortex-a57" { target aarch64*-*-* } } + +// PR target/120119 + +struct a { + float operator()(int b, int c) { return d[c * 4 + b]; } + float *d; +}; +float e(float *); +auto f(a b) { + float g[]{b(1, 1), b(2, 1), b(3, 1), b(1, 2), b(2, 2), b(3, 2), b(1, 3), + b(2, 3), b(3, 3), b(3, 2), b(1, 3), b(2, 3), b(3, 3)}; + return b.d[0] * e(g); +} diff --git a/gcc/testsuite/g++.dg/warn/Wmismatched-new-delete-5.C b/gcc/testsuite/g++.dg/warn/Wmismatched-new-delete-5.C index bac2b68..a21e864 100644 --- a/gcc/testsuite/g++.dg/warn/Wmismatched-new-delete-5.C +++ b/gcc/testsuite/g++.dg/warn/Wmismatched-new-delete-5.C @@ -31,7 +31,7 @@ void warn_placement_new () void warn_placement_array_new () { - void *p = malloc (sizeof (int)); + void *p = malloc (sizeof (int) * 2); int *q = new (p) int[2]; delete q; // { dg-warning "-Wmismatched-new-delete" } } diff --git a/gcc/testsuite/g++.target/aarch64/sme/sme_throw_1.C b/gcc/testsuite/g++.target/aarch64/sme/sme_throw_1.C new file mode 100644 index 0000000..76f1e8b --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sme/sme_throw_1.C @@ -0,0 +1,55 @@ +/* { dg-do run { target { aarch64*-linux-gnu* && aarch64_sme_hw } } } */ + +#include <signal.h> +#include <arm_sme.h> + +static bool caught; + +[[gnu::noipa]] void thrower(int) +{ + throw 1; +} + +[[gnu::noipa]] void bar() +{ + *(volatile int *)0 = 0; +} + +[[gnu::noipa]] void foo() +{ + try + { + bar(); + } + catch (int) + { + caught = true; + } +} + +__arm_new("za") __arm_locally_streaming void sme_user() +{ + svbool_t all = svptrue_b8(); + for (unsigned int i = 0; i < svcntb(); ++i) + { + svint8_t expected = svindex_s8(i + 1, i); + svwrite_hor_za8_m(0, i, all, expected); + } + foo(); + for (unsigned int i = 0; i < svcntb(); ++i) + { + svint8_t expected = svindex_s8(i + 1, i); + svint8_t actual = svread_hor_za8_m(svdup_s8(0), all, 0, i); + if (svptest_any(all, svcmpne(all, expected, actual))) + __builtin_abort(); + } + if (!caught) + __builtin_abort(); +} + +int main() +{ + signal(SIGSEGV, thrower); + sme_user(); + return 0; +} diff --git a/gcc/testsuite/g++.target/aarch64/sme/sme_throw_2.C b/gcc/testsuite/g++.target/aarch64/sme/sme_throw_2.C new file mode 100644 index 0000000..db3197c --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sme/sme_throw_2.C @@ -0,0 +1,4 @@ +/* { dg-do run { target { aarch64*-linux-gnu* && aarch64_sme_hw } } } */ +/* { dg-options "-O2" } */ + +#include "sme_throw_1.C" diff --git a/gcc/testsuite/g++.target/aarch64/sve/unpacked_binary_bf16_1.C b/gcc/testsuite/g++.target/aarch64/sve/unpacked_binary_bf16_1.C new file mode 100644 index 0000000..9d6342b --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/unpacked_binary_bf16_1.C @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-signed-zeros -ffinite-math-only -msve-vector-bits=2048" } */ + +#pragma GCC target "arch=armv9-a+sve-b16b16" + +#define ADD(a, b) a + b +#define SUB(a, b) a - b +#define MUL(a, b) a * b +#define MAX(a, b) (a > b) ? a : b +#define MIN(a, b) (a > b) ? b : a + +#define TEST_OP(TYPE, OP) \ + TYPE test_##TYPE##_##OP (TYPE a, TYPE b) { return OP (a, b); } \ + +#define TEST_ALL(TYPE, SIZE) \ + typedef TYPE TYPE##SIZE __attribute__((vector_size(SIZE))); \ + TEST_OP (TYPE##SIZE, ADD) \ + TEST_OP (TYPE##SIZE, SUB) \ + TEST_OP (TYPE##SIZE, MUL) \ + TEST_OP (TYPE##SIZE, MIN) \ + TEST_OP (TYPE##SIZE, MAX) + +TEST_ALL (__bf16, 64) + +TEST_ALL (__bf16, 128) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 5 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 5 } } */ + +/* { dg-final { scan-assembler-times {\tbfadd\tz[0-9]+\.h, p[0-7]/m. z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tbfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tbfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tbfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tbfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/unpacked_binary_bf16_2.C b/gcc/testsuite/g++.target/aarch64/sve/unpacked_binary_bf16_2.C new file mode 100644 index 0000000..63de293 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/unpacked_binary_bf16_2.C @@ -0,0 +1,15 @@ +/* { dg-do compile }*/ +/* { dg-options "-O2 -ffinite-math-only -fno-signed-zeros -fno-trapping-math -msve-vector-bits=2048 " } */ + +#include "unpacked_binary_bf16_1.C" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 10 } } */ + +/* { dg-final { scan-assembler-times {\tbfadd\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tbfsub\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tbfmul\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tbfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tbfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/g++.target/aarch64/sve/unpacked_cond_binary_bf16_1.C b/gcc/testsuite/g++.target/aarch64/sve/unpacked_cond_binary_bf16_1.C new file mode 100644 index 0000000..560d874 --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/unpacked_cond_binary_bf16_1.C @@ -0,0 +1,46 @@ +/* { dg-do compile }*/ +/* { dg-options "-O -ffinite-math-only -fno-signed-zeros -fno-trapping-math -msve-vector-bits=2048 " } */ + +#include <stdint.h> +#pragma GCC target "arch=armv9-a+sve-b16b16" + +#define ADD(a, b) a + b +#define SUB(a, b) a - b +#define MUL(a, b) a * b +#define MAX(a, b) (a > b) ? a : b +#define MIN(a, b) (a > b) ? b : a + +#define COND_OP(OP, TYPE, PRED_TYPE, ARG2, MERGE) \ + TYPE test_##OP##_##TYPE##_##ARG2##_##MERGE (TYPE a, TYPE b, TYPE c, PRED_TYPE p) \ + {return p ? OP (a, ARG2) : MERGE; } + +#define TEST_OP(OP, TYPE, PRED_TYPE, T) \ + T (OP, TYPE, PRED_TYPE, b, a) \ + T (OP, TYPE, PRED_TYPE, b, b) \ + T (OP, TYPE, PRED_TYPE, b, c) + +#define TEST_ALL(TYPE, PRED_TYPE, T) \ + TEST_OP (ADD, TYPE, PRED_TYPE, T) \ + TEST_OP (SUB, TYPE, PRED_TYPE, T) \ + TEST_OP (MUL, TYPE, PRED_TYPE, T) \ + TEST_OP (MAX, TYPE, PRED_TYPE, T) \ + TEST_OP (MIN, TYPE, PRED_TYPE, T) + +#define TEST(TYPE, PTYPE, SIZE) \ + typedef TYPE TYPE##SIZE __attribute__ ((vector_size (SIZE))); \ + typedef PTYPE PTYPE##SIZE __attribute__ ((vector_size (SIZE))); \ + TEST_ALL (TYPE##SIZE, PTYPE##SIZE, COND_OP) + +TEST (__bf16, uint16_t, 128) + +TEST (__bf16, uint16_t, 64) + +/* { dg-final { scan-assembler-times {\tbfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tbfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tbfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ + +/* { dg-final { scan-assembler-times {\tbfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tbfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ + +// There's no BFSUBR. +/* { dg-final { scan-assembler-times {\tsel\t} 2 } } */ diff --git a/gcc/testsuite/gcc.dg/20021014-1.c b/gcc/testsuite/gcc.dg/20021014-1.c index f5f6fcf..ee5d459 100644 --- a/gcc/testsuite/gcc.dg/20021014-1.c +++ b/gcc/testsuite/gcc.dg/20021014-1.c @@ -2,7 +2,7 @@ /* { dg-require-profiling "-p" } */ /* { dg-options "-O2 -p" } */ /* { dg-options "-O2 -p -static" { target hppa*-*-hpux* } } */ -/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-* x86_64-*-* } } */ +/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-gnu* x86_64-*-gnu* } } */ /* { dg-error "profiler" "No profiler support" { target xstormy16-*-* } 0 } */ /* { dg-message "" "consider using `-pg' instead of `-p' with gprof(1)" { target *-*-freebsd* } 0 } */ diff --git a/gcc/testsuite/gcc.dg/aru-2.c b/gcc/testsuite/gcc.dg/aru-2.c index 102ece1..61898de 100644 --- a/gcc/testsuite/gcc.dg/aru-2.c +++ b/gcc/testsuite/gcc.dg/aru-2.c @@ -1,7 +1,7 @@ /* { dg-do run } */ /* { dg-require-profiling "-pg" } */ /* { dg-options "-O2 -pg" } */ -/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-* x86_64-*-* } } */ +/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-gnu* x86_64-*-gnu* } } */ static int __attribute__((noinline)) bar (int x) diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-1.c b/gcc/testsuite/gcc.dg/asm-hard-reg-1.c new file mode 100644 index 0000000..6a5a9ad --- /dev/null +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-1.c @@ -0,0 +1,85 @@ +/* { dg-do compile { target aarch64*-*-* arm*-*-* i?86-*-* powerpc*-*-* riscv*-*-* s390*-*-* x86_64-*-* } } */ + +#if defined (__aarch64__) +# define GPR "{x4}" +/* { dg-final { scan-assembler-times "foo\tx4" 8 { target { aarch64*-*-* } } } } */ +#elif defined (__arm__) +# define GPR "{r4}" +/* { dg-final { scan-assembler-times "foo\tr4" 8 { target { arm*-*-* } } } } */ +#elif defined (__i386__) +# define GPR "{ecx}" +/* { dg-final { scan-assembler-times "foo\t%cl" 2 { target { i?86-*-* } } } } */ +/* { dg-final { scan-assembler-times "foo\t%cx" 2 { target { i?86-*-* } } } } */ +/* { dg-final { scan-assembler-times "foo\t%ecx" 4 { target { i?86-*-* } } } } */ +#elif defined (__powerpc__) || defined (__POWERPC__) +# define GPR "{r5}" +/* { dg-final { scan-assembler-times "foo\t5" 8 { target { powerpc*-*-* } } } } */ +#elif defined (__riscv) +# define GPR "{t5}" +/* { dg-final { scan-assembler-times "foo\tt5" 8 { target { riscv*-*-* } } } } */ +#elif defined (__s390__) +# define GPR "{r4}" +/* { dg-final { scan-assembler-times "foo\t%r4" 8 { target { s390*-*-* } } } } */ +#elif defined (__x86_64__) +# define GPR "{rcx}" +/* { dg-final { scan-assembler-times "foo\t%cl" 2 { target { x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "foo\t%cx" 2 { target { x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "foo\t%ecx" 2 { target { x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "foo\t%rcx" 2 { target { x86_64-*-* } } } } */ +#endif + +char +test_char (char x) +{ + __asm__ ("foo\t%0" : "+"GPR (x)); + return x; +} + +char +test_char_from_mem (char *x) +{ + __asm__ ("foo\t%0" : "+"GPR (*x)); + return *x; +} + +short +test_short (short x) +{ + __asm__ ("foo\t%0" : "+"GPR (x)); + return x; +} + +short +test_short_from_mem (short *x) +{ + __asm__ ("foo\t%0" : "+"GPR (*x)); + return *x; +} + +int +test_int (int x) +{ + __asm__ ("foo\t%0" : "+"GPR (x)); + return x; +} + +int +test_int_from_mem (int *x) +{ + __asm__ ("foo\t%0" : "+"GPR (*x)); + return *x; +} + +long +test_long (long x) +{ + __asm__ ("foo\t%0" : "+"GPR (x)); + return x; +} + +long +test_long_from_mem (long *x) +{ + __asm__ ("foo\t%0" : "+"GPR (*x)); + return *x; +} diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-2.c b/gcc/testsuite/gcc.dg/asm-hard-reg-2.c new file mode 100644 index 0000000..7dabf96 --- /dev/null +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-2.c @@ -0,0 +1,33 @@ +/* { dg-do compile { target aarch64*-*-* powerpc64*-*-* riscv64-*-* s390*-*-* x86_64-*-* } } */ +/* { dg-options "-std=c99" } we need long long */ + +#if defined (__aarch64__) +# define GPR "{x4}" +/* { dg-final { scan-assembler-times "foo\tx4" 2 { target { aarch64*-*-* } } } } */ +#elif defined (__powerpc__) || defined (__POWERPC__) +# define GPR "{r5}" +/* { dg-final { scan-assembler-times "foo\t5" 2 { target { powerpc64*-*-* } } } } */ +#elif defined (__riscv) +# define GPR "{t5}" +/* { dg-final { scan-assembler-times "foo\tt5" 2 { target { riscv64-*-* } } } } */ +#elif defined (__s390__) +# define GPR "{r4}" +/* { dg-final { scan-assembler-times "foo\t%r4" 2 { target { s390*-*-* } } } } */ +#elif defined (__x86_64__) +# define GPR "{rcx}" +/* { dg-final { scan-assembler-times "foo\t%rcx" 2 { target { x86_64-*-* } } } } */ +#endif + +long long +test_longlong (long long x) +{ + __asm__ ("foo\t%0" : "+"GPR (x)); + return x; +} + +long long +test_longlong_from_mem (long long *x) +{ + __asm__ ("foo\t%0" : "+"GPR (*x)); + return *x; +} diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-3.c b/gcc/testsuite/gcc.dg/asm-hard-reg-3.c new file mode 100644 index 0000000..fa4472a --- /dev/null +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-3.c @@ -0,0 +1,25 @@ +/* { dg-do compile { target { { aarch64*-*-* powerpc64*-*-* riscv64-*-* s390*-*-* x86_64-*-* } && int128 } } } */ +/* { dg-options "-O2" } get rid of -ansi since we use __int128 */ + +#if defined (__aarch64__) +# define REG "{x4}" +/* { dg-final { scan-assembler-times "foo\tx4" 1 { target { aarch64*-*-* } } } } */ +#elif defined (__powerpc__) || defined (__POWERPC__) +# define REG "{r5}" +/* { dg-final { scan-assembler-times "foo\t5" 1 { target { powerpc*-*-* } } } } */ +#elif defined (__riscv) +# define REG "{t5}" +/* { dg-final { scan-assembler-times "foo\tt5" 1 { target { riscv*-*-* } } } } */ +#elif defined (__s390__) +# define REG "{r4}" +/* { dg-final { scan-assembler-times "foo\t%r4" 1 { target { s390*-*-* } } } } */ +#elif defined (__x86_64__) +# define REG "{xmm0}" +/* { dg-final { scan-assembler-times "foo\t%xmm0" 1 { target { x86_64-*-* } } } } */ +#endif + +void +test (void) +{ + __asm__ ("foo\t%0" :: REG ((__int128) 42)); +} diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-4.c b/gcc/testsuite/gcc.dg/asm-hard-reg-4.c new file mode 100644 index 0000000..0134bf0 --- /dev/null +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-4.c @@ -0,0 +1,50 @@ +/* { dg-do compile { target aarch64*-*-* arm*-*-* powerpc*-*-* riscv*-*-* s390*-*-* x86_64-*-* } } */ + +#if defined (__aarch64__) +# define FPR "{d5}" +/* { dg-final { scan-assembler-times "foo\tv5" 4 { target { aarch64*-*-* } } } } */ +#elif defined (__arm__) +# define FPR "{d5}" +/* { dg-additional-options "-march=armv7-a+fp -mfloat-abi=hard" { target arm*-*-* } } */ +/* { dg-final { scan-assembler-times "foo\ts10" 4 { target { arm*-*-* } } } } */ +#elif defined (__powerpc__) || defined (__POWERPC__) +# define FPR "{5}" +/* { dg-final { scan-assembler-times "foo\t5" 4 { target { powerpc*-*-* } } } } */ +#elif defined (__riscv) +# define FPR "{fa5}" +/* { dg-final { scan-assembler-times "foo\tfa5" 4 { target { rsicv*-*-* } } } } */ +#elif defined (__s390__) +# define FPR "{f5}" +/* { dg-final { scan-assembler-times "foo\t%f5" 4 { target { s390*-*-* } } } } */ +#elif defined (__x86_64__) +# define FPR "{xmm5}" +/* { dg-final { scan-assembler-times "foo\t%xmm5" 4 { target { x86_64-*-* } } } } */ +#endif + +float +test_float (float x) +{ + __asm__ ("foo\t%0" : "+"FPR (x)); + return x; +} + +float +test_float_from_mem (float *x) +{ + __asm__ ("foo\t%0" : "+"FPR (*x)); + return *x; +} + +double +test_double (double x) +{ + __asm__ ("foo\t%0" : "+"FPR (x)); + return x; +} + +double +test_double_from_mem (double *x) +{ + __asm__ ("foo\t%0" : "+"FPR (*x)); + return *x; +} diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-5.c b/gcc/testsuite/gcc.dg/asm-hard-reg-5.c new file mode 100644 index 0000000..a9e25ce --- /dev/null +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-5.c @@ -0,0 +1,36 @@ +/* { dg-do compile { target aarch64*-*-* powerpc64*-*-* riscv64-*-* s390*-*-* x86_64-*-* } } */ + +typedef int V __attribute__ ((vector_size (4 * sizeof (int)))); + +#if defined (__aarch64__) +# define VR "{v20}" +/* { dg-final { scan-assembler-times "foo\tv20" 2 { target { aarch64*-*-* } } } } */ +#elif defined (__powerpc__) || defined (__POWERPC__) +# define VR "{v5}" +/* { dg-final { scan-assembler-times "foo\t5" 2 { target { powerpc64*-*-* } } } } */ +#elif defined (__riscv) +# define VR "{v5}" +/* { dg-additional-options "-march=rv64imv" { target riscv64-*-* } } */ +/* { dg-final { scan-assembler-times "foo\tv5" 2 { target { riscv*-*-* } } } } */ +#elif defined (__s390__) +# define VR "{v5}" +/* { dg-require-effective-target s390_mvx { target s390*-*-* } } */ +/* { dg-final { scan-assembler-times "foo\t%v5" 2 { target s390*-*-* } } } */ +#elif defined (__x86_64__) +# define VR "{xmm9}" +/* { dg-final { scan-assembler-times "foo\t%xmm9" 2 { target { x86_64-*-* } } } } */ +#endif + +V +test (V x) +{ + __asm__ ("foo\t%0" : "+"VR (x)); + return x; +} + +V +test_from_mem (V *x) +{ + __asm__ ("foo\t%0" : "+"VR (*x)); + return *x; +} diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-6.c b/gcc/testsuite/gcc.dg/asm-hard-reg-6.c new file mode 100644 index 0000000..d9b7fae --- /dev/null +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-6.c @@ -0,0 +1,60 @@ +/* { dg-do compile { target aarch64*-*-* arm*-*-* i?86-*-* powerpc*-*-* riscv*-*-* s390*-*-* x86_64-*-* } } */ +/* { dg-options "-O2" } */ + +/* Test multiple alternatives. */ + +#if defined (__aarch64__) +# define GPR1 "{x1}" +# define GPR2 "{x2}" +# define GPR3 "{x3}" +/* { dg-final { scan-assembler-times "foo\tx1,x3" 1 { target { aarch64*-*-* } } } } */ +/* { dg-final { scan-assembler-times "bar\tx2,\\\[x1\\\]" 1 { target { aarch64*-*-* } } } } */ +#elif defined (__arm__) +# define GPR1 "{r1}" +# define GPR2 "{r2}" +# define GPR3 "{r3}" +/* { dg-final { scan-assembler-times "foo\tr1,r3" 1 { target { arm*-*-* } } } } */ +/* { dg-final { scan-assembler-times "bar\tr2,\\\[r1\\\]" 1 { target { arm*-*-* } } } } */ +#elif defined (__i386__) +# define GPR1 "{eax}" +# define GPR2 "{ebx}" +# define GPR3 "{ecx}" +/* { dg-final { scan-assembler-times "foo\t4\\(%esp\\),%ecx" 1 { target { i?86-*-* } } } } */ +/* { dg-final { scan-assembler-times "bar\t%ebx,\\(%eax\\)" 1 { target { i?86-*-* } } } } */ +#elif defined (__powerpc__) || defined (__POWERPC__) +# define GPR1 "{r4}" +# define GPR2 "{r5}" +# define GPR3 "{r6}" +/* { dg-final { scan-assembler-times "foo\t4,6" 1 { target { powerpc*-*-* } } } } */ +/* { dg-final { scan-assembler-times "bar\t5,0\\(4\\)" 1 { target { powerpc*-*-* } } } } */ +#elif defined (__riscv) +# define GPR1 "{t1}" +# define GPR2 "{t2}" +# define GPR3 "{t3}" +/* { dg-final { scan-assembler-times "foo\tt1,t3" 1 { target { riscv*-*-* } } } } */ +/* { dg-final { scan-assembler-times "bar\tt2,0\\(a1\\)" 1 { target { riscv*-*-* } } } } */ +#elif defined (__s390__) +# define GPR1 "{r0}" +# define GPR2 "{r1}" +# define GPR3 "{r2}" +/* { dg-final { scan-assembler-times "foo\t%r0,%r2" 1 { target { s390*-*-* } } } } */ +/* { dg-final { scan-assembler-times "bar\t%r1,0\\(%r3\\)" 1 { target { s390*-*-* } } } } */ +#elif defined (__x86_64__) +# define GPR1 "{eax}" +# define GPR2 "{ebx}" +# define GPR3 "{rcx}" +/* { dg-final { scan-assembler-times "foo\t%eax,%rcx" 1 { target { x86_64-*-* } } } } */ +/* { dg-final { scan-assembler-times "bar\t%ebx,\\(%rsi\\)" 1 { target { x86_64-*-* } } } } */ +#endif + +void +test_reg_reg (int x, long long *y) +{ + __asm__ ("foo\t%0,%1" :: GPR1"m,"GPR2 (x), GPR3",m" (y)); +} + +void +test_reg_mem (int x, long long *y) +{ + __asm__ ("bar\t%0,%1" :: GPR1"m,"GPR2 (x), GPR3",m" (*y)); +} diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-7.c b/gcc/testsuite/gcc.dg/asm-hard-reg-7.c new file mode 100644 index 0000000..761a6b7 --- /dev/null +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-7.c @@ -0,0 +1,41 @@ +/* { dg-do compile { target aarch64*-*-* arm*-*-* i?86-*-* powerpc*-*-* riscv*-*-* s390*-*-* x86_64-*-* } } */ +/* { dg-options "-O2" } */ + +/* Test multiple alternatives. */ + +#if defined (__aarch64__) +# define GPR "{x1}" +/* { dg-final { scan-assembler-times "foo\tx1,x1" 2 { target { aarch64*-*-* } } } } */ +#elif defined (__arm__) +# define GPR "{r1}" +/* { dg-final { scan-assembler-times "foo\tr1,r1" 2 { target { arm*-*-* } } } } */ +#elif defined (__i386__) +# define GPR "{eax}" +/* { dg-final { scan-assembler-times "foo\t%eax,%eax" 2 { target { i?86-*-* } } } } */ +#elif defined (__powerpc__) || defined (__POWERPC__) +# define GPR "{r4}" +/* { dg-final { scan-assembler-times "foo\t4,4" 2 { target { powerpc*-*-* } } } } */ +#elif defined (__riscv) +# define GPR "{t1}" +/* { dg-final { scan-assembler-times "foo\tt1,t1" 2 { target { riscv*-*-* } } } } */ +#elif defined (__s390__) +# define GPR "{r0}" +/* { dg-final { scan-assembler-times "foo\t%r0,%r0" 2 { target { s390*-*-* } } } } */ +#elif defined (__x86_64__) +# define GPR "{eax}" +/* { dg-final { scan-assembler-times "foo\t%eax,%eax" 2 { target { x86_64-*-* } } } } */ +#endif + +int +test_1 (int x) +{ + __asm__ ("foo\t%0,%0" : "+"GPR (x)); + return x; +} + +int +test_2 (int x, int y) +{ + __asm__ ("foo\t%0,%1" : "="GPR (x) : GPR (y)); + return x; +} diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-8.c b/gcc/testsuite/gcc.dg/asm-hard-reg-8.c new file mode 100644 index 0000000..cda5e3e --- /dev/null +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-8.c @@ -0,0 +1,49 @@ +/* { dg-do compile { target aarch64*-*-* arm*-*-* i?86-*-* powerpc*-*-* riscv*-*-* s390*-*-* x86_64-*-* } } */ + +/* Due to hard register constraints, X must be copied. */ + +#if defined (__aarch64__) +# define GPR1 "{x1}" +# define GPR2 "{x2}" +#elif defined (__arm__) +# define GPR1 "{r1}" +# define GPR2 "{r2}" +#elif defined (__i386__) +# define GPR1 "{eax}" +# define GPR2 "{ebx}" +#elif defined (__powerpc__) || defined (__POWERPC__) +# define GPR1 "{r4}" +# define GPR2 "{r5}" +#elif defined (__riscv) +# define GPR1 "{t1}" +# define GPR2 "{t2}" +#elif defined (__s390__) +# define GPR1 "{r0}" +# define GPR2 "{r1}" +#elif defined (__x86_64__) +# define GPR1 "{eax}" +# define GPR2 "{ebx}" +#endif + +#define TEST(T) \ +int \ +test_##T (T x) \ +{ \ + int out; \ + __asm__ ("foo" : "=r" (out) : GPR1 (x), GPR2 (x)); \ + return out; \ +} + +TEST(char) +TEST(short) +TEST(int) +TEST(long) + +int +test_subreg (long x) +{ + int out; + short subreg_x = x; + __asm__ ("foo" : "=r" (out) : GPR1 (x), GPR2 (subreg_x)); + return out; +} diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-error-1.c b/gcc/testsuite/gcc.dg/asm-hard-reg-error-1.c new file mode 100644 index 0000000..0d7c2f2 --- /dev/null +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-error-1.c @@ -0,0 +1,83 @@ +/* { dg-do compile { target aarch64*-*-* arm*-*-* i?86-*-* powerpc*-*-* riscv*-*-* s390*-*-* x86_64-*-* } } */ + +#if defined (__aarch64__) +# define GPR1_RAW "x0" +# define GPR2 "{x1}" +# define GPR3 "{x2}" +# define INVALID_GPR_A "{x31}" +#elif defined (__arm__) +# define GPR1_RAW "r0" +# define GPR2 "{r1}" +# define GPR3 "{r2}" +# define INVALID_GPR_A "{r16}" +#elif defined (__i386__) +# define GPR1_RAW "%eax" +# define GPR2 "{%ebx}" +# define GPR3 "{%edx}" +# define INVALID_GPR_A "{%eex}" +#elif defined (__powerpc__) || defined (__POWERPC__) +# define GPR1_RAW "r4" +# define GPR2 "{r5}" +# define GPR3 "{r6}" +# define INVALID_GPR_A "{r33}" +#elif defined (__riscv) +# define GPR1_RAW "t4" +# define GPR2 "{t5}" +# define GPR3 "{t6}" +# define INVALID_GPR_A "{t7}" +#elif defined (__s390__) +# define GPR1_RAW "r4" +# define GPR2 "{r5}" +# define GPR3 "{r6}" +# define INVALID_GPR_A "{r17}" +#elif defined (__x86_64__) +# define GPR1_RAW "rax" +# define GPR2 "{rbx}" +# define GPR3 "{rcx}" +# define INVALID_GPR_A "{rex}" +#endif + +#define GPR1 "{"GPR1_RAW"}" +#define INVALID_GPR_B "{"GPR1_RAW + +struct { int a[128]; } s = {0}; + +void +test (void) +{ + int x, y; + register int gpr1 __asm__ (GPR1_RAW) = 0; + + __asm__ ("" :: "{}" (42)); /* { dg-error "invalid input constraint: \{\}" } */ + __asm__ ("" :: INVALID_GPR_A (42)); /* { dg-error "invalid input constraint" } */ + __asm__ ("" :: INVALID_GPR_B (42)); /* { dg-error "invalid input constraint" } */ + + __asm__ ("" :: GPR1 (s)); /* { dg-error "data type isn't suitable for register .* of operand 0" } */ + + __asm__ ("" :: "r" (gpr1), GPR1 (42)); /* { dg-error "multiple inputs to hard register" } */ + __asm__ ("" :: GPR1 (42), "r" (gpr1)); /* { dg-error "multiple inputs to hard register" } */ + __asm__ ("" :: GPR1 (42), GPR1 (42)); /* { dg-error "multiple inputs to hard register" } */ + __asm__ ("" :: GPR1","GPR2 (42), GPR2","GPR3 (42)); + __asm__ ("" :: GPR1","GPR2 (42), GPR3","GPR2 (42)); /* { dg-error "multiple inputs to hard register" } */ + __asm__ ("" :: GPR1","GPR2 (42), GPR1","GPR3 (42)); /* { dg-error "multiple inputs to hard register" } */ + __asm__ ("" :: GPR1 GPR2 (42), GPR2 (42)); /* { dg-error "multiple inputs to hard register" } */ + __asm__ ("" : "+"GPR1 (x), "="GPR1 (y)); /* { dg-error "multiple outputs to hard register" } */ + __asm__ ("" : "="GPR1 (y) : GPR1 (42), "0" (42)); /* { dg-error "multiple inputs to hard register" } */ + __asm__ ("" : "+"GPR1 (x) : GPR1 (42)); /* { dg-error "multiple inputs to hard register" } */ + + __asm__ ("" : "="GPR1 (gpr1)); + __asm__ ("" : "="GPR2 (gpr1)); /* { dg-error "constraint and register 'asm' for output operand 0 are unsatisfiable" } */ + __asm__ ("" :: GPR2 (gpr1)); /* { dg-error "constraint and register 'asm' for input operand 0 are unsatisfiable" } */ + __asm__ ("" : "="GPR1 (x) : "0" (gpr1)); + __asm__ ("" : "="GPR1 GPR2 (x) : "0" (gpr1)); /* { dg-error "constraint and register 'asm' for input operand 0 are unsatisfiable" } */ + + __asm__ ("" : "=&"GPR1 (x) : "0" (gpr1)); + __asm__ ("" : "=&"GPR1 (x) : "0" (42)); + __asm__ ("" : "=&"GPR2","GPR1 (x) : "r,"GPR1 (42)); + __asm__ ("" : "="GPR2",&"GPR1 (x) : "r,"GPR1 (42)); /* { dg-error "invalid hard register usage between earlyclobber operand and input operand" } */ + __asm__ ("" : "=&"GPR1 (x) : GPR1 (42)); /* { dg-error "invalid hard register usage between earlyclobber operand and input operand" } */ + __asm__ ("" : "=&"GPR2","GPR1 (x) : "r,r" (gpr1)); + __asm__ ("" : "="GPR2",&"GPR1 (x) : "r,r" (gpr1)); /* { dg-error "invalid hard register usage between earlyclobber operand and input operand" } */ + __asm__ ("" : "=&r" (gpr1) : GPR1 (42)); /* { dg-error "invalid hard register usage between earlyclobber operand and input operand" } */ + __asm__ ("" : "=&"GPR1 (x), "=r" (y) : "1" (gpr1)); /* { dg-error "invalid hard register usage between earlyclobber operand and input operand" } */ +} diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-error-2.c b/gcc/testsuite/gcc.dg/asm-hard-reg-error-2.c new file mode 100644 index 0000000..d0d5cfe --- /dev/null +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-error-2.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target { { aarch64*-*-* s390x-*-* } && int128 } } } */ +/* { dg-options "-O2" } get rid of -ansi since we use __int128 */ + +/* Test register pairs. */ + +#if defined (__aarch64__) +# define GPR1 "{x4}" +# define GPR2_RAW "x5" +#elif defined (__s390__) +# define GPR1 "{r4}" +# define GPR2_RAW "r5" +#endif + +#define GPR2 "{"GPR2_RAW"}" + +void +test (void) +{ + __asm__ ("" :: GPR1 ((__int128) 42)); + __asm__ ("" :: GPR2 ((__int128) 42)); /* { dg-error "register .* for operand 0 isn't suitable for data type" } */ + __asm__ ("" :: GPR1 ((__int128) 42), GPR2 (42)); /* { dg-error "multiple inputs to hard register" } */ + + __int128 x; + __asm__ ("" : "="GPR1 (x) :: GPR2_RAW); /* { dg-error "hard register constraint for output 0 conflicts with 'asm' clobber list" } */ + __asm__ ("" : "=r" (x) : GPR1 (x) : GPR2_RAW); /* { dg-error "hard register constraint for input 0 conflicts with 'asm' clobber list" } */ +} diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-error-3.c b/gcc/testsuite/gcc.dg/asm-hard-reg-error-3.c new file mode 100644 index 0000000..17b2317 --- /dev/null +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-error-3.c @@ -0,0 +1,27 @@ +/* { dg-do compile { target arm-*-* s390-*-* } } */ +/* { dg-options "-std=c99" } we need long long */ +/* { dg-additional-options "-march=armv7-a" { target arm-*-* } } */ + +/* Test register pairs. */ + +#if defined (__arm__) +# define GPR1 "{r4}" +# define GPR2_RAW "r5" +#elif defined (__s390__) +# define GPR1 "{r4}" +# define GPR2_RAW "r5" +#endif + +#define GPR2 "{"GPR2_RAW"}" + +void +test (void) +{ + __asm__ ("" :: GPR1 (42ll)); + __asm__ ("" :: GPR2 (42ll)); /* { dg-error "register .* for operand 0 isn't suitable for data type" } */ + __asm__ ("" :: GPR1 (42ll), GPR2 (42)); /* { dg-error "multiple inputs to hard register" } */ + + long long x; + __asm__ ("" : "="GPR1 (x) :: GPR2_RAW); /* { dg-error "hard register constraint for output 0 conflicts with 'asm' clobber list" } */ + __asm__ ("" : "=r" (x) : GPR1 (x) : GPR2_RAW); /* { dg-error "hard register constraint for input 0 conflicts with 'asm' clobber list" } */ +} diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-error-4.c b/gcc/testsuite/gcc.dg/asm-hard-reg-error-4.c new file mode 100644 index 0000000..465f24b --- /dev/null +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-error-4.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ + +/* Verify output operands. */ + +int +test (void) +{ + int x; + register int y __asm__ ("0"); + + /* Preserve status quo and don't error out. */ + __asm__ ("" : "=r" (x), "=r" (x)); + + /* Be more strict for hard register constraints and error out. */ + __asm__ ("" : "={0}" (x), "={1}" (x)); /* { dg-error "multiple outputs to lvalue 'x'" } */ + + /* Still error out in case of a mixture. */ + __asm__ ("" : "=r" (x), "={1}" (x)); /* { dg-error "multiple outputs to lvalue 'x'" } */ + + return x + y; +} diff --git a/gcc/testsuite/gcc.dg/asm-hard-reg-error-5.c b/gcc/testsuite/gcc.dg/asm-hard-reg-error-5.c new file mode 100644 index 0000000..85398f0 --- /dev/null +++ b/gcc/testsuite/gcc.dg/asm-hard-reg-error-5.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ + +/* Test clobbers. + See asm-hard-reg-error-{2,3}.c for tests involving register pairs. */ + +int +test (void) +{ + int x, y; + __asm__ ("" : "={0}" (x), "={1}" (y) : : "1"); /* { dg-error "hard register constraint for output 1 conflicts with 'asm' clobber list" } */ + __asm__ ("" : "={0}" (x) : "{0}" (y), "{1}" (y) : "1"); /* { dg-error "hard register constraint for input 1 conflicts with 'asm' clobber list" } */ + return x + y; +} diff --git a/gcc/testsuite/gcc.dg/bitint-124.c b/gcc/testsuite/gcc.dg/bitint-124.c new file mode 100644 index 0000000..160a1e3 --- /dev/null +++ b/gcc/testsuite/gcc.dg/bitint-124.c @@ -0,0 +1,30 @@ +/* PR tree-optimization/121131 */ +/* { dg-do run { target bitint } } */ +/* { dg-options "-O2" } */ + +#if __BITINT_MAXWIDTH__ >= 156 +struct A { _BitInt(156) b : 135; }; + +static inline _BitInt(156) +foo (struct A *x) +{ + return x[1].b; +} + +__attribute__((noipa)) _BitInt(156) +bar (void) +{ + struct A a[] = { 1, 1, -13055525270329736316393717310914023773847wb, + 1, 1, 1, 1, 1, 1, 1, 1, 1 }; + return foo (&a[1]); +} +#endif + +int +main () +{ +#if __BITINT_MAXWIDTH__ >= 156 + if (bar () != -13055525270329736316393717310914023773847wb) + __builtin_abort (); +#endif +} diff --git a/gcc/testsuite/gcc.dg/nest.c b/gcc/testsuite/gcc.dg/nest.c index 9221ed1..2dce65e 100644 --- a/gcc/testsuite/gcc.dg/nest.c +++ b/gcc/testsuite/gcc.dg/nest.c @@ -3,7 +3,7 @@ /* { dg-require-profiling "-pg" } */ /* { dg-options "-O2 -pg" } */ /* { dg-options "-O2 -pg -static" { target hppa*-*-hpux* } } */ -/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-* x86_64-*-* } } */ +/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-gnu* x86_64-*-gnu* } } */ /* { dg-error "profiler" "No profiler support" { target xstormy16-*-* } 0 } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/pr109267-1.c b/gcc/testsuite/gcc.dg/pr109267-1.c new file mode 100644 index 0000000..e762e59 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr109267-1.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ + +/* PR middle-end/109267 */ + +int f(void) +{ + __builtin_unreachable(); +} + +/* This unreachable should be changed to be a trap. */ + +/* { dg-final { scan-tree-dump-times "__builtin_unreachable trap \\\(" 1 "optimized" { target trap } } } */ +/* { dg-final { scan-tree-dump-times "goto <" 1 "optimized" { target { ! trap } } } } */ +/* { dg-final { scan-tree-dump-not "__builtin_unreachable \\\(" "optimized"} } */ diff --git a/gcc/testsuite/gcc.dg/pr109267-2.c b/gcc/testsuite/gcc.dg/pr109267-2.c new file mode 100644 index 0000000..6cd1419 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr109267-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ + +/* PR middle-end/109267 */ +void g(void); +int f(int *t) +{ + g(); + __builtin_unreachable(); +} + +/* The unreachable should stay a unreachable. */ +/* { dg-final { scan-tree-dump-not "__builtin_unreachable trap \\\(" "optimized"} } */ +/* { dg-final { scan-tree-dump-times "__builtin_unreachable \\\(" 1 "optimized"} } */ diff --git a/gcc/testsuite/gcc.dg/pr121035.c b/gcc/testsuite/gcc.dg/pr121035.c new file mode 100644 index 0000000..fc0edce --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr121035.c @@ -0,0 +1,94 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fgimple" } */ + +int printf(const char *, ...); +int a, b, d; +unsigned c; +int __GIMPLE (ssa,startwith("pre")) +main () +{ + unsigned int g; + int f; + unsigned int _1; + unsigned int _2; + int _3; + int _4; + int _5; + unsigned int _6; + unsigned int _7; + int _10; + unsigned int _11; + _Bool _19; + _Bool _20; + _Bool _22; + int _25; + + __BB(2): + _25 = a; + if (_25 != 0) + goto __BB11; + else + goto __BB10; + + __BB(11): + goto __BB3; + + __BB(3): + f_26 = __PHI (__BB12: f_18, __BB11: 0); + g_15 = c; + if (f_26 != 0) + goto __BB4; + else + goto __BB5; + + __BB(4): + __builtin_putchar (48); + goto __BB5; + + __BB(5): + _1 = c; + _2 = _1 << 1; + _3 = a; + _4 = d; + _5 = _3 * _4; + if (_5 != 0) + goto __BB7; + else + goto __BB6; + + __BB(6): + goto __BB7; + + __BB(7): + _11 = __PHI (__BB5: 0u, __BB6: 4294967295u); + _6 = g_15 * 4294967294u; + _7 = _6 | _11; + _20 = _3 != 0; + _19 = _7 != 0u; + _22 = _19 & _20; + if (_22 != _Literal (_Bool) 0) + goto __BB9; + else + goto __BB8; + + __BB(8): + goto __BB9; + + __BB(9): + _10 = __PHI (__BB7: 1, __BB8: 0); + b = _10; + f_18 = (int) _1; + if (_3 != 0) + goto __BB12; + else + goto __BB10; + + __BB(12): + goto __BB3; + + __BB(10): + return 0; + +} + + diff --git a/gcc/testsuite/gcc.dg/pr121202.c b/gcc/testsuite/gcc.dg/pr121202.c new file mode 100644 index 0000000..30ecf4a --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr121202.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -fno-tree-copy-prop" } */ + +int a, b, c; +int e(int f, int g) { return f >> g; } +int h(int f) { return a > 1 ? 0 : f << a; } +int main() { + while (c--) + b = e(h(1), a); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/pr121216.c b/gcc/testsuite/gcc.dg/pr121216.c new file mode 100644 index 0000000..a695b40 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr121216.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "" } */ + +int foo (void) +{ + const char *key = "obscurelevelofabstraction"; + const char reverse_key[__builtin_strlen(key)] = {'\0'}; /* { dg-error "variable-sized object may not be initialized except with an empty initializer" } */ + return __builtin_strlen(reverse_key); +} diff --git a/gcc/testsuite/gcc.dg/pr32450.c b/gcc/testsuite/gcc.dg/pr32450.c index 4aaeb7d..0af262f 100644 --- a/gcc/testsuite/gcc.dg/pr32450.c +++ b/gcc/testsuite/gcc.dg/pr32450.c @@ -3,7 +3,8 @@ /* { dg-do run } */ /* { dg-require-profiling "-pg" } */ /* { dg-options "-O2 -pg" } */ -/* { dg-options "-O2 -pg -mtune=core2 -mfentry -fno-pic" { target { i?86-*-* x86_64-*-* } } } */ +/* { dg-options "-O2 -pg -mtune=core2" { target { i?86-*-* x86_64-*-* } } } */ +/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-gnu* x86_64-*-gnu* } } */ /* { dg-options "-O2 -pg -static" { target hppa*-*-hpux* } } */ extern void abort (void); diff --git a/gcc/testsuite/gcc.dg/pr43643.c b/gcc/testsuite/gcc.dg/pr43643.c index a62586d..41c00c8 100644 --- a/gcc/testsuite/gcc.dg/pr43643.c +++ b/gcc/testsuite/gcc.dg/pr43643.c @@ -4,7 +4,7 @@ /* { dg-require-profiling "-pg" } */ /* { dg-options "-O2 -pg" } */ /* { dg-options "-O2 -pg -static" { target hppa*-*-hpux* } } */ -/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-* x86_64-*-* } } */ +/* { dg-additional-options "-mfentry -fno-pic" { target i?86-*-gnu* x86_64-*-gnu* } } */ extern char *strdup (const char *); diff --git a/gcc/testsuite/gcc.dg/pr87600-2.c b/gcc/testsuite/gcc.dg/pr87600-2.c index 808ebe1..822afe0 100644 --- a/gcc/testsuite/gcc.dg/pr87600-2.c +++ b/gcc/testsuite/gcc.dg/pr87600-2.c @@ -23,22 +23,3 @@ test1 (void) asm ("blah %0 %1" : "=r" (var1) : "0" (var2)); /* { dg-error "invalid hard register usage between output operand and matching constraint operand" } */ return var1; } - -long -test2 (void) -{ - register long var1 asm (REG1); - register long var2 asm (REG1); - asm ("blah %0 %1" : "=&r" (var1) : "r" (var2)); /* { dg-error "invalid hard register usage between earlyclobber operand and input operand" } */ - return var1; -} - -long -test3 (void) -{ - register long var1 asm (REG1); - register long var2 asm (REG1); - long var3; - asm ("blah %0 %1" : "=&r" (var1), "=r" (var3) : "1" (var2)); /* { dg-error "invalid hard register usage between earlyclobber operand and input operand" } */ - return var1 + var3; -} diff --git a/gcc/testsuite/gcc.dg/pr87600-3.c b/gcc/testsuite/gcc.dg/pr87600-3.c new file mode 100644 index 0000000..4f43a5f --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr87600-3.c @@ -0,0 +1,26 @@ +/* PR rtl-optimization/87600 */ +/* { dg-do compile { target aarch64*-*-* arm*-*-* i?86-*-* powerpc*-*-* s390*-*-* x86_64-*-* } } */ +/* { dg-options "-O2" } */ + +#include "pr87600.h" + +/* The following are all invalid uses of local register variables. */ + +long +test2 (void) +{ + register long var1 asm (REG1); + register long var2 asm (REG1); + asm ("blah %0 %1" : "=&r" (var1) : "r" (var2)); /* { dg-error "invalid hard register usage between earlyclobber operand and input operand" } */ + return var1; +} + +long +test3 (void) +{ + register long var1 asm (REG1); + register long var2 asm (REG1); + long var3; + asm ("blah %0 %1" : "=&r" (var1), "=r" (var3) : "1" (var2)); /* { dg-error "invalid hard register usage between earlyclobber operand and input operand" } */ + return var1 + var3; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr121194.c b/gcc/testsuite/gcc.dg/torture/pr121194.c new file mode 100644 index 0000000..20f5ff7 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr121194.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ + +int a, b, c, d; +void e() { + int *f = &b; + for (a = 0; a < 8; a++) { + *f = 0; + for (c = 0; c < 2; c++) + *f = *f == 0; + } +} +int main() { + e(); + int *g = &b; + *g = *g == (d == 0); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/tree-prof/afdo-crossmodule-1b.c b/gcc/testsuite/gcc.dg/tree-prof/afdo-crossmodule-1b.c index dd53295..79ba529 100644 --- a/gcc/testsuite/gcc.dg/tree-prof/afdo-crossmodule-1b.c +++ b/gcc/testsuite/gcc.dg/tree-prof/afdo-crossmodule-1b.c @@ -1,3 +1,8 @@ +/* { dg-require-effective-target lto } */ +/* { dg-additional-sources "afdo-crossmodule-1.c" } */ +/* { dg-options "-O3 -flto -fdump-ipa-afdo_offline -fdump-tree-einline-details" } */ +/* { dg-require-profiling "-fauto-profile" } */ + extern int foo2 (); int bar (int (*fooptr) (int (*)())) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/cmp-2.c b/gcc/testsuite/gcc.dg/tree-ssa/cmp-2.c new file mode 100644 index 0000000..9b02901 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/cmp-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -fdump-tree-forwprop" } */ + +/* PR tree-optimization/110949 */ +/* Transform `(cmp) - 1` into `-icmp`. */ + +int f1(int a) +{ + int t = a == 115; + return t - 1; +} + +/* { dg-final { scan-tree-dump " != 115" "forwprop1" } } */ +/* { dg-final { scan-tree-dump-not " == 115" "forwprop1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/max-bitcmp-1.c b/gcc/testsuite/gcc.dg/tree-ssa/max-bitcmp-1.c new file mode 100644 index 0000000..81b5a27 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/max-bitcmp-1.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -fdump-tree-forwprop -fdump-tree-optimized" } */ + +/* PR tree-optimization/95906 */ +/* this should become MAX_EXPR<a,b> */ + +int f2(int a, int b) +{ + int cmp = -(a > b); + return (cmp & a) | (~cmp & b); +} + +/* we should not end up with -_2 */ +/* we should not end up and & nor a `+ -1` */ +/* In optimized we should have a max. */ +/* { dg-final { scan-tree-dump-not " -\[a-zA-Z_\]" "forwprop1" } } */ +/* { dg-final { scan-tree-dump-not " & " "forwprop1" } } */ +/* { dg-final { scan-tree-dump-not " . -1" "forwprop1" } } */ +/* { dg-final { scan-tree-dump-times "MAX_EXPR " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr117423.c b/gcc/testsuite/gcc.dg/tree-ssa/pr117423.c new file mode 100644 index 0000000..a5d3b29 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr117423.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-options "-O1" } */ + +struct s4 { + int _0; +}; +struct s1 { + unsigned char _4; + long _1; +}; +struct s2 { + union { + struct s3 { + unsigned char _1; + struct s4 _0; + } var_0; + struct s1 var_1; + } DATA; +}; +int f1(int arg0) { return arg0 > 12345; } +__attribute__((noinline)) +struct s4 f2(int arg0) { + struct s4 rv = {arg0}; + return rv; +} +struct s2 f3(int arg0) { + struct s2 rv; + struct s1 var6 = {0}; + struct s4 var7; + if (f1(arg0)) { + rv.DATA.var_1 = var6; + return rv; + } else { + rv.DATA.var_0._1 = 2; + var7 = f2(arg0); + rv.DATA.var_0._0 = var7; + return rv; + } +} +int main() { + if (f3(12345).DATA.var_0._0._0 == 12345) + ; + else + __builtin_abort(); + if (f3(12344).DATA.var_0._0._0 == 12344) + ; + else + __builtin_abort(); +} diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr119085.c b/gcc/testsuite/gcc.dg/tree-ssa/pr119085.c new file mode 100644 index 0000000..e9811ce --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr119085.c @@ -0,0 +1,37 @@ +/* { dg-do run } */ +/* { dg-options "-O1" } */ + +struct with_hole { + int x; + long y; +}; +struct without_hole { + int x; + int y; +}; +union u { + struct with_hole with_hole; + struct without_hole without_hole; +}; + +void __attribute__((noinline)) +test (union u *up, union u u) +{ + union u u2; + volatile int f = 0; + u2 = u; + if (f) + u2.with_hole = u.with_hole; + *up = u2; +} + +int main(void) +{ + union u u; + union u u2; + u2.without_hole.y = -1; + test (&u, u2); + if (u.without_hole.y != -1) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr81627.c b/gcc/testsuite/gcc.dg/tree-ssa/pr81627.c index 9ba43be..ef35b29 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr81627.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr81627.c @@ -4,6 +4,7 @@ int a, b, c, d[6], e = 3, f; void abort (void); +void fn1 () __attribute__((noinline)); void fn1 () { for (b = 1; b < 5; b++) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-23.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-23.c new file mode 100644 index 0000000..f632dc8 --- /dev/null +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-23.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-sink1-details" } */ + +struct S { + int* x; + int* y; +}; + +void __attribute__((noreturn)) bar(const struct S* s); + +void foo(int a, int b) { + struct S s; + s.x = &a; + s.y = &b; + if (a < b) { + bar(&s); + } +} + +/* { dg-final { scan-tree-dump "Sinking.*s.y" "sink1" } } */ +/* { dg-final { scan-tree-dump "Sinking.*s.x" "sink1" } } */ diff --git a/gcc/testsuite/gcc.dg/uninit-pr120924.c b/gcc/testsuite/gcc.dg/uninit-pr120924.c new file mode 100644 index 0000000..bfc8ae9 --- /dev/null +++ b/gcc/testsuite/gcc.dg/uninit-pr120924.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wmaybe-uninitialized" } */ + +int foo(int); +enum { + BPF_TRACE_RAW_TP, + BPF_MODIFY_RETURN, + BPF_LSM_MAC, + BPF_TRACE_ITER, + BPF_LSM_CGROUP +}; +int btf_get_kernel_prefix_kind_prefix, obj_1, attach_name___trans_tmp_1; +char attach_name_fn_name; +void attach_name(int attach_type) +{ + int mod_len; + char mod_name = attach_name_fn_name; + if (attach_name_fn_name) + mod_len = mod_name; + for (; obj_1;) { + if (mod_name && foo(mod_len)) + continue; + switch (attach_type) { + case BPF_TRACE_RAW_TP: + case BPF_LSM_MAC: + case BPF_LSM_CGROUP: + btf_get_kernel_prefix_kind_prefix = 1; + case BPF_TRACE_ITER: + attach_name_fn_name = 2; + } + if (attach_name___trans_tmp_1) + return; + } +} diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-39.c b/gcc/testsuite/gcc.dg/vect/bb-slp-39.c index f05ce8f..255bb10 100644 --- a/gcc/testsuite/gcc.dg/vect/bb-slp-39.c +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-39.c @@ -16,5 +16,4 @@ void foo (double *p) } /* See that we vectorize three SLP instances. */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "slp2" { target { ! { s390*-*-* riscv*-*-* } } } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 5 "slp2" { target { s390*-*-* riscv*-*-* } } } } */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 3 "slp2" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr116125.c b/gcc/testsuite/gcc.dg/vect/pr116125.c index eab9efd..1b882ec 100644 --- a/gcc/testsuite/gcc.dg/vect/pr116125.c +++ b/gcc/testsuite/gcc.dg/vect/pr116125.c @@ -17,12 +17,12 @@ main (void) { check_vect (); - struct st a[9] = {}; + struct st a[10] = {}; - // input a = 0, 0, 0, 0, 0, 0, 0, 0, 0 + // input a = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 mem_overlap (&a[1], a); - // output a = 0, 1, 2, 3, 4, 5, 6, 7, 8 + // output a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 if (a[2].num == 2) return 0; else diff --git a/gcc/testsuite/gcc.dg/vect/pr121049.c b/gcc/testsuite/gcc.dg/vect/pr121049.c new file mode 100644 index 0000000..558c92a --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr121049.c @@ -0,0 +1,25 @@ +/* { dg-additional-options "--param vect-partial-vector-usage=1" } */ +/* { dg-additional-options "-march=x86-64-v4" { target avx512f_runtime } } */ + +#include "tree-vect.h" + +int mon_lengths[12] = { 1, 10, 100 }; + +__attribute__ ((noipa)) long +transtime (int mon) +{ + long value = 0; + for (int i = 0; i < mon; ++i) + value += mon_lengths[i] * 2l; + return value; +} + +int +main () +{ + check_vect (); + if (transtime (3) != 222) + __builtin_abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.dg/vect/pr121126.c b/gcc/testsuite/gcc.dg/vect/pr121126.c new file mode 100644 index 0000000..ae6603b --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr121126.c @@ -0,0 +1,30 @@ +/* { dg-additional-options "--param vect-partial-vector-usage=2" } */ + +#include "tree-vect.h" + +unsigned char a; +unsigned b; +int r[11]; +static void __attribute__((noipa)) +c(int e, unsigned s[][11][11]) +{ + for (int u = -(e ? 2000424973 : 0) - 2294542319; u < 7; u += 4) + for (int x = 0; x < 300000011; x += 4) + for (int y = 0; y < (0 < s[u][4][1]) + 11; y += 3) { + a = a ?: 1; + b = r[2]; + } +} +long long ab; +int e = 1; +unsigned s[11][11][11]; +int main() +{ + check_vect (); + for (int t = 0; t < 11; ++t) + r[t] = 308100; + c(e,s); + ab = b; + if (ab != 308100) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.dg/vect/slp-28.c b/gcc/testsuite/gcc.dg/vect/slp-28.c index 67b7be2..1f98787 100644 --- a/gcc/testsuite/gcc.dg/vect/slp-28.c +++ b/gcc/testsuite/gcc.dg/vect/slp-28.c @@ -59,8 +59,8 @@ main1 () abort (); } - /* Not vectorizable because of data dependencies: distance 3 is greater than - the actual VF with SLP (2), but the analysis fail to detect that for now. */ + /* Dependence distance 3 is greater than the actual VF with SLP (2), + thus vectorizable. */ for (i = 3; i < N/4; i++) { in3[i*4] = in3[(i-3)*4] + 5; @@ -91,7 +91,6 @@ int main (void) return 0; } -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target { ! vect32 } } } } */ -/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target vect32 } } } */ -/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 1 "vect" { target { ! vect32 } } } } */ +/* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "vectorizing stmts using SLP" 2 "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-127.c b/gcc/testsuite/gcc.dg/vect/vect-127.c new file mode 100644 index 0000000..8b913dc --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-127.c @@ -0,0 +1,15 @@ +// { dg-do compile } +// { dg-require-effective-target vect_int } + +void foo (int *p) +{ + for (int i = 0; i < 1024; ++i) + { + int a0 = p[2*i + 0]; + int a1 = p[2*i + 1]; + p[2*i + 4] = a0; + p[2*i + 5] = a1; + } +} + +/* { dg-final { scan-tree-dump "loop vectorized using 16 byte vectors" "vect" { target { vect128 && vect_hw_misalign } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-1.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-1.c new file mode 100644 index 0000000..258f17e --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-1.c @@ -0,0 +1,60 @@ +/* { dg-require-effective-target vect_int } */ +/* { dg-require-effective-target vect_condition } */ + +#include <stdarg.h> +#include "tree-vect.h" + +/* PR tree-optimization/119920 */ + +#define N 32 + +unsigned int ub[N]; + +/* Test vectorization of reduction of unsigned-int. */ + +__attribute__ ((noinline, noipa)) +void init(void) +{ + #pragma GCC novector + for(int i = 0;i < N; i++) + ub[i] = i; +} + + +__attribute__ ((noinline, noipa)) +void main1 (unsigned int b, unsigned int c) +{ + int i; + unsigned int usum = 0; + + init(); + + /* Summation. */ + for (i = 0; i < N; i++) { + if ( ub[i] < N/2 ) + { + usum += b; + } + else + { + usum += c; + } + } + + /* check results: */ + /* __builtin_printf("%d : %d\n", usum, (N/2*b + N/2*c)); */ + if (usum != N/2*b + N/2*c) + abort (); +} + +int main (void) +{ + check_vect (); + + main1 (0, 0); + main1 (1, 1); + main1 (10, 1); + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_int_add } } } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-2.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-2.c new file mode 100644 index 0000000..126a50f --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-2.c @@ -0,0 +1,62 @@ +/* { dg-require-effective-target vect_int } */ +/* { dg-require-effective-target vect_condition } */ +/* { dg-additional-options "-fdump-tree-ifcvt-details" } */ + +#include <stdarg.h> +#include "tree-vect.h" + +/* PR tree-optimization/119920 */ + +#define N 32 + +unsigned int ub[N]; +unsigned int ua[N]; + +/* Test vectorization of reduction of unsigned-int. */ + +__attribute__ ((noinline, noipa)) +void init(void) +{ + #pragma GCC novector + for(int i = 0;i < N; i++) { + ub[i] = i; + ua[i] = 1; + } +} + + +__attribute__ ((noinline, noipa)) +void main1 (unsigned int b, unsigned int c) +{ + int i; + unsigned int usum = 0; + + init(); + + /* Summation. */ + for (i = 0; i < N; i++) { + unsigned t = ua[i]; + if ( ub[i] < N/2 ) + usum += b * t; + else + usum += c * t; + } + + /* check results: */ + /* __builtin_printf("%d : %d\n", usum, (N/2*b*1 + N/2*c*1)); */ + if (usum != N/2*b + N/2*c) + abort (); +} + +int main (void) +{ + check_vect (); + + main1 (0, 0); + main1 (1, 1); + main1 (10, 1); + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_int_add } } } } */ +/* { dg-final { scan-tree-dump-times "changed to factor operation out from COND_EXPR" 2 "ifcvt" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-3.c b/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-3.c new file mode 100644 index 0000000..e425869 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/vect-reduc-cond-3.c @@ -0,0 +1,56 @@ +/* { dg-require-effective-target vect_int } */ + +#include <stdarg.h> +#include "tree-vect.h" + +/* PR tree-optimization/112324 */ +/* PR tree-optimization/110015 */ + +#define N 32 + +int ub[N]; + +/* Test vectorization of reduction of int max with some extra code involed. */ + +__attribute__ ((noinline, noipa)) +void init(void) +{ + #pragma GCC novector + for(int i = 0;i < N; i++) + ub[i] = (i&4) && (i&1) ? -i : i; +} + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) + +__attribute__ ((noinline, noipa)) +void main1 (void) +{ + int i; + int max = 0; + + init(); + + /* Summation. */ + for (i = 0; i < N; i++) { + int tmp = ub[i]; + if (tmp < 0) + max = MAX (-tmp, max); + else + max = MAX (tmp, max); + } + + /* check results: */ + /* __builtin_printf("%d : %d\n", max, N); */ + if (max != N - 1) + abort (); +} + +int main (void) +{ + check_vect (); + + main1 (); + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_int_min_max } } } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/asm-hard-reg-1.c b/gcc/testsuite/gcc.target/aarch64/asm-hard-reg-1.c new file mode 100644 index 0000000..7441dd7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-hard-reg-1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* Ensure that we error out in case no hard regs are available for an operand + with constraint y. The position/order of the y-constrained operand does not + matter. */ + +void +test (void) +{ + int x, a, b, c, d, e, f, g, h; + + __asm__ __volatile__ ("" : + "={v0}" (a), + "={v1}" (b), + "={v2}" (c), + "={v3}" (d), + "={v4}" (e), + "={v5}" (f), + "={v6}" (g), + "={v7}" (h)); + + __asm__ __volatile__ ("" : /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + "=y" (x), + "={v0}" (a), + "={v1}" (b), + "={v2}" (c), + "={v3}" (d), + "={v4}" (e), + "={v5}" (f), + "={v6}" (g), + "={v7}" (h)); + + __asm__ __volatile__ ("" : /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + "={v0}" (a), + "={v1}" (b), + "={v2}" (c), + "={v3}" (d), + "=y" (x), + "={v4}" (e), + "={v5}" (f), + "={v6}" (g), + "={v7}" (h)); + + __asm__ __volatile__ ("" : /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + "={v0}" (a), + "={v1}" (b), + "={v2}" (c), + "={v3}" (d), + "={v4}" (e), + "={v5}" (f), + "={v6}" (g), + "={v7}" (h), + "=y" (x)); +} diff --git a/gcc/testsuite/gcc.target/aarch64/asm-hard-reg-2.c b/gcc/testsuite/gcc.target/aarch64/asm-hard-reg-2.c new file mode 100644 index 0000000..7434063 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-hard-reg-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8-a+sve" } */ + +/* Test register pairs. */ + +#include <arm_sve.h> + +void +test (void) +{ + svuint32x2_t x, y; + svuint32x4_t z; + + __asm__ __volatile__ ("" : "={z4}" (x), "={z6}" (y)); + __asm__ __volatile__ ("" : "={z5}" (x), "={z6}" (y)); /* { dg-error "multiple outputs to hard register: v6" } */ + __asm__ __volatile__ ("" : "={z4}" (z), "={z6}" (y)); /* { dg-error "multiple outputs to hard register: v6" } */ +} diff --git a/gcc/testsuite/gcc.target/aarch64/inszero_split_1.c b/gcc/testsuite/gcc.target/aarch64/inszero_split_1.c new file mode 100644 index 0000000..5c739bd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/inszero_split_1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* Avoid INS from WZR register when optimizing for speed. */ + +#include <arm_neon.h> + +/* +** foo: +** movi? [vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0 +** ins v0.h\[2\], v(\1).h\[0\] +** ret +*/ +uint16x8_t foo(uint16x8_t a) { + a[2] = 0; + return a; +} diff --git a/gcc/testsuite/gcc.target/aarch64/simd/mf8_data_1.c b/gcc/testsuite/gcc.target/aarch64/simd/mf8_data_1.c index a3fd9b8..79d1ccf 100644 --- a/gcc/testsuite/gcc.target/aarch64/simd/mf8_data_1.c +++ b/gcc/testsuite/gcc.target/aarch64/simd/mf8_data_1.c @@ -1016,7 +1016,12 @@ mfloat8x8_t test_set_lane3(mfloat8x8_t a, const mfloat8_t *ptr) /* ** test_set_lane4: +** ( ** ins v0.b\[6\], wzr +** | +** movi? [vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0 +** ins v0.b\[6\], v(\1).b\[0\] +** ) ** ret */ mfloat8x8_t test_set_lane4(mfloat8x8_t a) @@ -1056,7 +1061,12 @@ mfloat8x16_t test_setq_lane3(mfloat8x16_t a, const mfloat8_t *ptr) /* ** test_setq_lane4: +** ( ** ins v0.b\[14\], wzr +** | +** movi? [vdz]([0-9]+)\.?(?:[0-9]*[bhsd])?, #?0 +** ins v0.b\[14\], v(\1).b\[0\] +** ) ** ret */ mfloat8x16_t test_setq_lane4(mfloat8x16_t a) diff --git a/gcc/testsuite/gcc.target/aarch64/sve/mask_load_2.c b/gcc/testsuite/gcc.target/aarch64/sve/mask_load_2.c new file mode 100644 index 0000000..66d9510 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/mask_load_2.c @@ -0,0 +1,23 @@ +// { dg-do compile } +// { dg-options "-march=armv8-a+sve -msve-vector-bits=128 -O3" } + +typedef struct Array { + int elems[3]; +} Array; + +int loop(Array **pp, int len, int idx) { + int nRet = 0; + + #pragma GCC unroll 0 + for (int i = 0; i < len; i++) { + Array *p = pp[i]; + if (p) { + nRet += p->elems[idx]; + } + } + + return nRet; +} + +// { dg-final { scan-assembler-times {ld1w\tz[0-9]+\.d, p[0-7]/z} 1 } } +// { dg-final { scan-assembler-times {add\tz[0-9]+\.s, p[0-7]/m} 1 } } diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_1.c new file mode 100644 index 0000000..e6aa047 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_1.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i], RHS) > c[i]) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1) + +TEST_ALL (__builtin_fmaxf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_fmaxf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_fmaxf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 6 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_2.c new file mode 100644 index 0000000..87125a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmax_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_builtin_fmax_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 9 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_1.c new file mode 100644 index 0000000..b9fded0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_1.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i], RHS) > c[i]) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1) + +TEST_ALL (__builtin_fminf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_fminf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_fminf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 6 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_2.c new file mode 100644 index 0000000..5923b67 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_builtin_fmin_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_builtin_fmin_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 9 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_1.c new file mode 100644 index 0000000..d328b37 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmax_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, b_i) + +TEST_ALL (__builtin_fmaxf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_fmaxf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_fmaxf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_1.c new file mode 100644 index 0000000..1821f03 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_builtin_fmin_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, b_i) + +TEST_ALL (__builtin_fminf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_fminf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_fminf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_cvtf_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_cvtf_1.c new file mode 100644 index 0000000..fa4dd15 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_cvtf_1.c @@ -0,0 +1,51 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define COND_CVT(TYPE0, TYPE1, TYPE2, COUNT) \ + void \ + test_##TYPE0##_##TYPE1##_##TYPE2 (TYPE0 *__restrict out, \ + TYPE1 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE2 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? (TYPE0)a[i] : b[i]; \ + } + +#define TEST_CVTF(PFX, T) \ + T (_Float16, PFX##int16_t, uint64_t, 32) \ + T (_Float16, PFX##int16_t, uint32_t, 64) \ + T (_Float16, PFX##int32_t, uint64_t, 32) \ + T (_Float16, PFX##int32_t, uint32_t, 64) \ + T (_Float16, PFX##int64_t, uint64_t, 32) \ + T (float, PFX##int32_t, uint64_t, 32) \ + T (float, PFX##int64_t, uint64_t, 32) + +#define TEST_ALL(T) \ + TEST_CVTF (, T) \ + TEST_CVTF (u, T) + +TEST_ALL (COND_CVT) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 8 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 6 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 8 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fabs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fabs_1.c new file mode 100644 index 0000000..d959aa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fabs_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_fabsf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_fabsf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_fabsf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fadd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fadd_1.c new file mode 100644 index 0000000..666cf89 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fadd_1.c @@ -0,0 +1,62 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] +#define imm_p5 0.5 + +#define ADD(A, B) A + B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, NAME, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##NAME##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b[i], a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b[i], b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b[i], c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, one, 1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, one, 1, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, none, -1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, none, -1, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, p5, 0.5, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, p5, 0.5, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, np5, -0.5, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, np5, -0.5, b_i) + +TEST_ALL (ADD, _Float16, uint64_t, 32) + +TEST_ALL (ADD, _Float16, uint32_t, 64) + +TEST_ALL (ADD, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 19 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 19 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 19 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 5 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 10 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fcvt_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fcvt_1.c new file mode 100644 index 0000000..3caae19 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fcvt_1.c @@ -0,0 +1,41 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define COND_CVT(TYPE0, TYPE1, TYPE2, COUNT) \ + void \ + test_##TYPE0##_##TYPE1##_##TYPE2 (TYPE0 *__restrict out, \ + TYPE1 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE2 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? (TYPE0)a[i] : b[i]; \ + } + +#define TEST_FCVT(T) \ + T (_Float16, float, uint64_t, 32) \ + T (_Float16, float, uint32_t, 64) \ + T (_Float16, double, uint64_t, 32) \ + T (float, double, uint64_t, 32) \ + T (float, _Float16, uint64_t, 32) \ + T (float, _Float16, uint32_t, 64) \ + T (double, _Float16, uint64_t,32) \ + T (double, float, uint64_t, 32) + +TEST_FCVT (COND_CVT) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.h\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvt\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fcvtz_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fcvtz_1.c new file mode 100644 index 0000000..426d3af --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fcvtz_1.c @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define COND_CVT(TYPE0, TYPE1, TYPE2, COUNT) \ + void \ + test_##TYPE0##_##TYPE1##_##TYPE2 (TYPE0 *__restrict out, \ + TYPE1 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE2 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? (TYPE0)a[i] : b[i]; \ + } + +#define TEST_FCVTZ(PFX, T) \ + T (PFX##int16_t, _Float16, uint64_t, 32) \ + T (PFX##int16_t, _Float16, uint32_t, 64) \ + T (PFX##int32_t, _Float16, uint64_t, 32) \ + T (PFX##int32_t, _Float16, uint32_t, 64) \ + T (PFX##int64_t, _Float16, uint64_t, 32) \ + T (PFX##int32_t, float, uint64_t, 32) \ + T (PFX##int64_t, float, uint64_t, 32) \ + T (PFX##int32_t, double, uint64_t, 32) + +#define TEST_ALL(T) \ + TEST_FCVTZ (, T) \ + TEST_FCVTZ (u, T) + +TEST_ALL (COND_CVT) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 10 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 6 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 8 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.h\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.h\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fdiv_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fdiv_1.c new file mode 100644 index 0000000..ec5653e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fdiv_1.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define DIV(A, B) A / B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) + +TEST_ALL (DIV, _Float16, uint64_t, 32) + +TEST_ALL (DIV, _Float16, uint32_t, 64) + +TEST_ALL (DIV, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfdivr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfdiv\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfdivr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfdiv\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmaxnm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmaxnm_1.c new file mode 100644 index 0000000..d34872f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmaxnm_1.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-signed-zeros -ffinite-math-only -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define MAX(A, B) (A > B) ? A : B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, b_i) + +TEST_ALL (MAX, _Float16, uint64_t, 32) + +TEST_ALL (MAX, _Float16, uint32_t, 64) + +TEST_ALL (MAX, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fminnm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fminnm_1.c new file mode 100644 index 0000000..d6c3c38 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fminnm_1.c @@ -0,0 +1,53 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-signed-zeros -ffinite-math-only -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] + +#define MIN(A, B) (A < B) ? A : B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, b_i) + +TEST_ALL (MIN, _Float16, uint64_t, 32) + +TEST_ALL (MIN, _Float16, uint32_t, 64) + +TEST_ALL (MIN, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmul_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmul_1.c new file mode 100644 index 0000000..1ae7678 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fmul_1.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] +#define imm_p5 0.5 + +#define MUL(A, B) A * B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, imm_p5, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, imm_p5, b_i) + +TEST_ALL (MUL, _Float16, uint64_t, 32) + +TEST_ALL (MUL, _Float16, uint32_t, 64) + +TEST_ALL (MUL, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 10 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 10 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 10 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fneg_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fneg_1.c new file mode 100644 index 0000000..7280f4e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fneg_1.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define NEG(X) -X + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (NEG, _Float16, uint64_t, 32) + +TEST_ALL (NEG, _Float16, uint32_t, 64) + +TEST_ALL (NEG, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_1.c new file mode 100644 index 0000000..ed4efb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_roundf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_roundf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_roundf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c new file mode 100644 index 0000000..f20e2e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinta_2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -mtune=generic -ftree-vectorize" } */ + +#include "unpacked_cond_frinta_1.c" + +/* Test that we don't drop SELs without -fno-trapping-math. */ + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-times {\tsel\t} 6 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinti_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinti_1.c new file mode 100644 index 0000000..d682d15 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frinti_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_nearbyintf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_nearbyintf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_nearbyintf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrinti\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrinti\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintm_1.c new file mode 100644 index 0000000..7d429b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintm_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_floorf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_floorf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_floorf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrintm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrintm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintp_1.c new file mode 100644 index 0000000..c6d0c8c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintp_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_ceilf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_ceilf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_ceilf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrintp\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrintp\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintx_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintx_1.c new file mode 100644 index 0000000..b8afef1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintx_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_rintf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_rintf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_rintf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrintx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrintx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintz_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintz_1.c new file mode 100644 index 0000000..d55279b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_frintz_1.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, MERGE) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##MERGE (TYPE1 *__restrict p, \ + TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i]) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (__builtin_truncf16, _Float16, uint64_t, 32) + +TEST_ALL (__builtin_truncf16, _Float16, uint32_t, 64) + +TEST_ALL (__builtin_truncf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfrintz\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrintz\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fsubr_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fsubr_1.c new file mode 100644 index 0000000..eafd169 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_cond_fsubr_1.c @@ -0,0 +1,56 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include <stdint.h> + +#define a_i a[i] +#define b_i b[i] +#define c_i c[i] +#define imm_p5 0.5 + +#define SUBR(A, B) B - A + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS, MERGE) \ + void \ + f_##TYPE0##_##TYPE1##_##RHS##_##MERGE (TYPE0 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c, \ + TYPE1 *__restrict p) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + out[i] = p[i] ? FN (a[i], (TYPE0)RHS) : MERGE; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, c_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, imm_p5, a_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, imm_p5, b_i) + +TEST_ALL (SUBR, _Float16, uint64_t, 32) + +TEST_ALL (SUBR, _Float16, uint32_t, 64) + +TEST_ALL (SUBR, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 13 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 13 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 3 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 6 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 4 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 4 } } */ + +/* { dg-final { scan-assembler-not {\tsel\t} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fabs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fabs_1.c new file mode 100644 index 0000000..f09cfe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fabs_1.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_fabsf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_fabsf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_fabsf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_1.c new file mode 100644 index 0000000..9675f56 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_1.c @@ -0,0 +1,52 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define ADD(A, B) A + B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, NAME, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##NAME (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i], (TYPE0)RHS) > c[i]) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i, b[i]) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, p5, 0.5) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, np5, -0.5) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, one, 1) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, none, -1) + +TEST_ALL (ADD, _Float16, uint64_t, 32) + +TEST_ALL (ADD, _Float16, uint32_t, 64) + +TEST_ALL (ADD, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 5 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 10 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 11 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 11 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 11 } } */ + +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_2.c new file mode 100644 index 0000000..7a74efd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fadd_2.c @@ -0,0 +1,26 @@ +/* { dg-do compile }*/ +/* { dg-options "-O2 -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fadd_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 12 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 11 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 11 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 11 } } */ + +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfadd\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_1.c new file mode 100644 index 0000000..78d0d9c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_1.c @@ -0,0 +1,38 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define b_i b[i] +#define DIV(A, B) A / B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i], (TYPE0)RHS) > c[i]) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) + +TEST_ALL (DIV, _Float16, uint64_t, 32) + +TEST_ALL (DIV, _Float16, uint32_t, 64) + +TEST_ALL (DIV, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfdivr?\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfdivr?\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_2.c new file mode 100644 index 0000000..a8f70e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fdiv_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfdivr?\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfdivr?\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_3.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_3.c new file mode 100644 index 0000000..ecd088f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fdiv_3.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -moverride=sve_width=2048 -mlow-precision-div" } */ + +#include "unpacked_fdiv_1.c" + +/* { dg-final { scan-assembler-not {\tfrecpe\tz[0-9]+\.h} } } */ +/* { dg-final { scan-assembler-not {\tfrecps\tz[0-9]+\.h} } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 3 } } */ + +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tfrecpe\tz[0-9]+\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrecps\tz[0-9]+\.s} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_1.c new file mode 100644 index 0000000..5239e4b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_1.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-signed-zeros -ffinite-math-only -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define b_i b[i] +#define MAX(A, B) (A > B) ? A : B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (c[i] = FN (a[i], RHS)) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1) + +TEST_ALL (MAX, _Float16, uint64_t, 32) + +TEST_ALL (MAX, _Float16, uint32_t, 64) + +TEST_ALL (MAX, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 6 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_2.c new file mode 100644 index 0000000..11aa7c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmaxnm_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-signed-zeros -ffinite-math-only -fno-trapping-math -moverride=sve_width=2048" } */ + +#include "unpacked_fmaxnm_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 9 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmaxnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_1.c new file mode 100644 index 0000000..02a5f46 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_1.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-signed-zeros -ffinite-math-only -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define b_i b[i] +#define MIN(A, B) (A < B) ? A : B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (c[i] = FN (a[i], RHS) ) \ + out[i] = 3; \ + } + + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 0) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1) + +TEST_ALL (MIN, _Float16, uint64_t, 32) + +TEST_ALL (MIN, _Float16, uint32_t, 64) + +TEST_ALL (MIN, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 6 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_2.c new file mode 100644 index 0000000..81f583b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fminnm_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fno-signed-zeros -ffinite-math-only -fno-trapping-math -moverride=sve_width=2048" } */ + +#include "unpacked_fminnm_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 9 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 4 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.0\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.0\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfminnm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_1.c new file mode 100644 index 0000000..a180a07 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_1.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define b_i b[i] +#define immp5 0.5 +#define MUL(A, B) A * B + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i], (TYPE0)RHS) > c[i]) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, immp5) + +TEST_ALL (MUL, _Float16, uint64_t, 32) + +TEST_ALL (MUL, _Float16, uint32_t, 64) + +TEST_ALL (MUL, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 4 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 5 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 5 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 5 } } */ + +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_2.c new file mode 100644 index 0000000..eb05600 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fmul_2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fmul_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 5 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 5 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 5 } } */ + +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfmul\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fneg_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fneg_1.c new file mode 100644 index 0000000..d489ecb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fneg_1.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define NEG(X) -X + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (NEG, _Float16, uint64_t, 32) + +TEST_FN (NEG, _Float16, uint32_t, 64) + +TEST_FN (NEG, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c new file mode 100644 index 0000000..3cbdef3 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_roundf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_roundf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_roundf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_2.c new file mode 100644 index 0000000..4564686 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinta_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include "unpacked_frinta_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrinta\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c new file mode 100644 index 0000000..7645fed --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_nearbyintf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_nearbyintf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_nearbyintf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrinti\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrinti\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_2.c new file mode 100644 index 0000000..eadce07 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frinti_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include "unpacked_frinti_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrinti\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrinti\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c new file mode 100644 index 0000000..98f85fb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_floorf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_floorf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_floorf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_2.c new file mode 100644 index 0000000..56988be --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintm_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include "unpacked_frintm_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintm\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintm\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c new file mode 100644 index 0000000..f233697 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_ceilf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_ceilf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_ceilf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintp\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintp\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_2.c new file mode 100644 index 0000000..c24c632 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintp_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include "unpacked_frintp_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintp\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintp\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c new file mode 100644 index 0000000..73403a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_rintf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_rintf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_rintf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_2.c new file mode 100644 index 0000000..e8b8924 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintx_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include "unpacked_frintx_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintx\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintx\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c new file mode 100644 index 0000000..7377843 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_1.c @@ -0,0 +1,31 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize" } */ + +#include <stdint.h> + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT) \ + void \ + f_##FN##_##TYPE0##_##TYPE1 (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i]) > b[i]) \ + out[i] = 3; \ + } + +TEST_FN (__builtin_truncf16, _Float16, uint64_t, 32) + +TEST_FN (__builtin_truncf16, _Float16, uint32_t, 64) + +TEST_FN (__builtin_truncf32, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 1 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintz\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintz\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_2.c new file mode 100644 index 0000000..1779122 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_frintz_2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048 -ftree-vectorize -fno-trapping-math" } */ + +#include "unpacked_frintz_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 3 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 2 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 2 } } */ + +/* { dg-final { scan-assembler-times {\tfrintz\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfrintz\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_1.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_1.c new file mode 100644 index 0000000..2cc8ec2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_1.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -moverride=sve_width=2048" } */ + +#include <stdint.h> + +#define b_i b[i] +#define immp5 0.5 +#define SUBR(A, B) B - A + +#define TEST_FN(FN, TYPE0, TYPE1, COUNT, RHS) \ + void \ + f_##FN##_##TYPE0##_##TYPE1##_##RHS (TYPE1 *__restrict out, \ + TYPE0 *__restrict a, \ + TYPE0 *__restrict b, \ + TYPE0 *__restrict c) \ + { \ + for (unsigned int i = 0; i < COUNT; i++) \ + if (FN (a[i], (TYPE0)RHS) > c[i]) \ + out[i] = 3; \ + } + +#define TEST_ALL(FN, TYPE0, TYPE1, COUNT) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, b_i) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, immp5) \ + TEST_FN (FN, TYPE0, TYPE1, COUNT, 1) + +TEST_ALL (SUBR, _Float16, uint64_t, 32) + +TEST_ALL (SUBR, _Float16, uint32_t, 64) + +TEST_ALL (SUBR, float, uint64_t, 32) + +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.s} 3 } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.d} 6 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tfsubr?\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfsubr?\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_2.c b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_2.c new file mode 100644 index 0000000..de9325c --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/unpacked_fsubr_2.c @@ -0,0 +1,20 @@ +/* { dg-do compile }*/ +/* { dg-options "-O2 -moverride=sve_width=2048 -fno-trapping-math" } */ + +#include "unpacked_fsubr_1.c" + +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.s} } } */ +/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.d} } } */ +/* { dg-final { scan-assembler-times {\tptrue\tp[0-7]\.b} 6 } } */ + +/* { dg-final { scan-assembler-times {\tld1w\tz[0-9]+\.d} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.s} 7 } } */ +/* { dg-final { scan-assembler-times {\tld1h\tz[0-9]+\.d} 7 } } */ + +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.s, z[0-9]+\.s, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #0.5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s, #1.0\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfsub\tz[0-9]+\.h, z[0-9]+\.h, z[0-9]+\.h\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #0.5\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tfsubr\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h, #1.0\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c b/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c index b34b902c..ba4696e 100644 --- a/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c +++ b/gcc/testsuite/gcc.target/aarch64/vec-set-zero.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2" } */ +/* { dg-options "-Os" } */ #include "arm_neon.h" diff --git a/gcc/testsuite/gcc.target/i386/asm-hard-reg-1.c b/gcc/testsuite/gcc.target/i386/asm-hard-reg-1.c new file mode 100644 index 0000000..8080f56 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/asm-hard-reg-1.c @@ -0,0 +1,80 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +test (void) +{ + int x, y; + + __asm__ __volatile__ ("" : "=a" (x), "={rbx}" (y)); + __asm__ __volatile__ ("" : "=a" (x), "={rax}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=a" (x) : "{rax}" (y)); + __asm__ __volatile__ ("" : "=&a" (x) : "{rax}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "a" (x), "{rax}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rbx}" (x), "=a" (y)); + __asm__ __volatile__ ("" : "={rax}" (x), "=a" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rax}" (x) : "a" (y)); + __asm__ __volatile__ ("" : "=&{rax}" (x) : "a" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rax}" (x), "a" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "=b" (x), "={rax}" (y)); + __asm__ __volatile__ ("" : "=b" (x), "={rbx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=b" (x) : "{rbx}" (y)); + __asm__ __volatile__ ("" : "=&b" (x) : "{rbx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "b" (x), "{rbx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rax}" (x), "=b" (y)); + __asm__ __volatile__ ("" : "={rbx}" (x), "=b" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rbx}" (x) : "b" (y)); + __asm__ __volatile__ ("" : "=&{rbx}" (x) : "b" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rbx}" (x), "b" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "=c" (x), "={rax}" (y)); + __asm__ __volatile__ ("" : "=c" (x), "={rcx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=c" (x) : "{rcx}" (y)); + __asm__ __volatile__ ("" : "=&c" (x) : "{rcx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "c" (x), "{rcx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rax}" (x), "=c" (y)); + __asm__ __volatile__ ("" : "={rcx}" (x), "=c" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rcx}" (x) : "c" (y)); + __asm__ __volatile__ ("" : "=&{rcx}" (x) : "c" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rcx}" (x), "c" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "=d" (x), "={rax}" (y)); + __asm__ __volatile__ ("" : "=d" (x), "={rdx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=d" (x) : "{rdx}" (y)); + __asm__ __volatile__ ("" : "=&d" (x) : "{rdx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "d" (x), "{rdx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rax}" (x), "=d" (y)); + __asm__ __volatile__ ("" : "={rdx}" (x), "=d" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rdx}" (x) : "d" (y)); + __asm__ __volatile__ ("" : "=&{rdx}" (x) : "d" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rdx}" (x), "d" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "=S" (x), "={rax}" (y)); + __asm__ __volatile__ ("" : "=S" (x), "={rsi}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=S" (x) : "{rsi}" (y)); + __asm__ __volatile__ ("" : "=&S" (x) : "{rsi}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "S" (x), "{rsi}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rax}" (x), "=S" (y)); + __asm__ __volatile__ ("" : "={rsi}" (x), "=S" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rsi}" (x) : "S" (y)); + __asm__ __volatile__ ("" : "=&{rsi}" (x) : "S" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rsi}" (x), "S" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "=D" (x), "={rax}" (y)); + __asm__ __volatile__ ("" : "=D" (x), "={rdi}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=D" (x) : "{rdi}" (y)); + __asm__ __volatile__ ("" : "=&D" (x) : "{rdi}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "D" (x), "{rdi}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rax}" (x), "=D" (y)); + __asm__ __volatile__ ("" : "={rdi}" (x), "=D" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rdi}" (x) : "D" (y)); + __asm__ __volatile__ ("" : "=&{rdi}" (x) : "D" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rdi}" (x), "D" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/asm-hard-reg-2.c b/gcc/testsuite/gcc.target/i386/asm-hard-reg-2.c new file mode 100644 index 0000000..b35cf53 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/asm-hard-reg-2.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +test (void) +{ + int x, y, yy; +#ifdef __x86_64__ + int z __attribute__ ((mode (TI))); +#else + long z; +#endif + + __asm__ __volatile__ ("" : "=A" (z), "={rbx}" (y)); + __asm__ __volatile__ ("" : "=A" (z), "={rax}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=A" (z), "={rdx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=A" (z) : "{rax}" (y)); + __asm__ __volatile__ ("" : "=A" (z) : "{rdx}" (y)); + __asm__ __volatile__ ("" : "=&A" (z) : "{rax}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=&A" (z) : "{rdx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "A" (z), "{rax}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "A" (z), "{rdx}" (y)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + __asm__ __volatile__ ("" : "={rbx}" (y), "=A" (z)); + __asm__ __volatile__ ("" : "={rax}" (y), "=A" (z)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rdx}" (y), "=A" (z)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "={rax}" (y) : "A" (z)); + __asm__ __volatile__ ("" : "={rdx}" (y) : "A" (z)); + __asm__ __volatile__ ("" : "=&{rax}" (y) : "A" (z)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=&{rdx}" (y) : "A" (z)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rax}" (y), "A" (z)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" :: "{rdx}" (y), "A" (z)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + + /* Note, we do not error for */ + __asm__ __volatile__ ("" : "=A" (x), "={rax}" (y)); + __asm__ __volatile__ ("" : "=A" (x), "={rdx}" (y)); + /* This is due to how constraint A is implemented. RA has the freedom to + choose between rax or rdx for operand 0 since x fits into a single + register and does not require a register pair. Of course, we error out if + rax and rdx are taken by other operands as in the following: */ + __asm__ __volatile__ ("" : "=A" (x), "={rax}" (y), "={rdx}" (yy)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + __asm__ __volatile__ ("" : "=A" (x), "={rdx}" (y), "={rax}" (yy)); /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ +} diff --git a/gcc/testsuite/gcc.target/i386/pr104447.c b/gcc/testsuite/gcc.target/i386/pr104447.c index f58170d..145ba90 100644 --- a/gcc/testsuite/gcc.target/i386/pr104447.c +++ b/gcc/testsuite/gcc.target/i386/pr104447.c @@ -1,6 +1,7 @@ /* { dg-do compile } */ /* { dg-require-profiling "-pg" } */ -/* { dg-options "-O2 -pg -mfentry -fno-pic" } */ +/* { dg-options "-O2 -pg" } */ +/* { dg-additional-options "-mfentry -fno-pic" { target *-*-gnu* } } */ int bar (int x) diff --git a/gcc/testsuite/gcc.target/i386/pr113122-3.c b/gcc/testsuite/gcc.target/i386/pr113122-3.c index c46805d..87b76de 100644 --- a/gcc/testsuite/gcc.target/i386/pr113122-3.c +++ b/gcc/testsuite/gcc.target/i386/pr113122-3.c @@ -1,7 +1,8 @@ /* PR target/113122 */ /* { dg-do assemble { target *-*-linux* } } */ /* { dg-require-effective-target masm_intel } */ -/* { dg-options "-fprofile -mfentry -fno-pic -O2 -masm=intel" } */ +/* { dg-options "-fprofile -O2 -masm=intel" } */ +/* { dg-additional-options "-mfentry -fno-pic" { target *-*-gnu* } } */ void func (void) diff --git a/gcc/testsuite/gcc.target/i386/pr119386-1.c b/gcc/testsuite/gcc.target/i386/pr119386-1.c index 39a3e1d..7a56eac 100644 --- a/gcc/testsuite/gcc.target/i386/pr119386-1.c +++ b/gcc/testsuite/gcc.target/i386/pr119386-1.c @@ -1,9 +1,9 @@ /* PR target/119386 */ /* { dg-do compile { target *-*-linux* } } */ /* { dg-options "-O2 -fpic -pg" } */ -/* { dg-additional-options "-mfentry" { target { ! ia32 } } } */ +/* { dg-additional-options "-mfentry" { target { *-*-gnu* && { ! ia32 } } } } */ /* { dg-final { scan-assembler "call\[ \t\]+mcount@PLT" { target ia32 } } } */ -/* { dg-final { scan-assembler "call\[ \t\]+__fentry__@PLT" { target { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+__fentry__@PLT" { target { *-*-gnu* && { ! ia32 } } } } } */ int main () diff --git a/gcc/testsuite/gcc.target/i386/pr119386-2.c b/gcc/testsuite/gcc.target/i386/pr119386-2.c index d516aa9..cddaaf0 100644 --- a/gcc/testsuite/gcc.target/i386/pr119386-2.c +++ b/gcc/testsuite/gcc.target/i386/pr119386-2.c @@ -1,8 +1,8 @@ /* PR target/119386 */ /* { dg-do compile { target *-*-linux* } } */ /* { dg-options "-O2 -fpic -fno-plt -pg" } */ -/* { dg-additional-options "-mfentry" { target { ! ia32 } } } */ -/* { dg-final { scan-assembler "call\[ \t\]+\\*__fentry__@GOTPCREL" { target { ! ia32 } } } } */ +/* { dg-additional-options "-mfentry" { target { *-*-gnu* && { ! ia32 } } } } */ +/* { dg-final { scan-assembler "call\[ \t\]+\\*__fentry__@GOTPCREL" { target { *-*-gnu* && { ! ia32 } } } } } */ /* { dg-final { scan-assembler "call\[ \t\]+\\*mcount@GOT\\(" { target ia32 } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-1.c b/gcc/testsuite/gcc.target/i386/pr121062-1.c new file mode 100644 index 0000000..799f856 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-1.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64-v3" } */ + +extern union { + int i; + float f; +} int_as_float_u; + +extern int render_result_from_bake_w; +extern int render_result_from_bake_h_seed_pass; +extern float *render_result_from_bake_h_primitive; +extern float *render_result_from_bake_h_seed; + +float +int_as_float(int i) +{ + int_as_float_u.i = i; + return int_as_float_u.f; +} + +void +render_result_from_bake_h(int tx) +{ + while (render_result_from_bake_w) { + for (; tx < render_result_from_bake_w; tx++) + render_result_from_bake_h_primitive[1] = + render_result_from_bake_h_primitive[2] = int_as_float(-1); + if (render_result_from_bake_h_seed_pass) { + *render_result_from_bake_h_seed = 0; + } + } +} + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+\\\$-1, %r\[a-z0-9\]+" 2 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-2.c b/gcc/testsuite/gcc.target/i386/pr121062-2.c new file mode 100644 index 0000000..723d68a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-2.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-Og -fno-dce -mtune=generic" } */ + +typedef int __attribute__((__vector_size__ (4))) S; +extern void bar (S); + +void +foo () +{ + bar ((S){-1}); +} + +/* { dg-final { scan-assembler-times "movl\[ \\t\]+\\\$-1, \\(%esp\\)" 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movl\[ \\t\]+\\\$-1, %edi" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-3a.c b/gcc/testsuite/gcc.target/i386/pr121062-3a.c new file mode 100644 index 0000000..effd4ff --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-3a.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target fpic } } */ +/* { dg-options "-O2 -march=x86-64 -fpic" } */ + +typedef struct { + struct { + unsigned short lo4; + unsigned short lo3; + unsigned short lo2; + unsigned short lo1; + } i; +} BID_BINARY80LDOUBLE; +extern BID_BINARY80LDOUBLE __bid64_to_binary80_x_out; +void +__bid64_to_binary80 (void) +{ + __bid64_to_binary80_x_out.i.lo4 + = __bid64_to_binary80_x_out.i.lo3 + = __bid64_to_binary80_x_out.i.lo2 + = __bid64_to_binary80_x_out.i.lo1 = 65535; +} + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+%xmm\[0-9\]+, " 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movq\[ \\t\]+\\\$-1, \\(%(e|r)\[a-z0-9\]+\\)" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-3b.c b/gcc/testsuite/gcc.target/i386/pr121062-3b.c new file mode 100644 index 0000000..eb89b5d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-3b.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { fpic && lp64 } } } */ +/* { dg-options "-O2 -march=x86-64 -fno-pic -mcmodel=large" } */ + +#include "pr121062-3a.c" + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+\\\$-1, \\(%r\[a-z0-9\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-3c.c b/gcc/testsuite/gcc.target/i386/pr121062-3c.c new file mode 100644 index 0000000..4c07029 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-3c.c @@ -0,0 +1,6 @@ +/* { dg-do compile { target { fpic && lp64 } } } */ +/* { dg-options "-O2 -march=x86-64 -fpic -mcmodel=large" } */ + +#include "pr121062-3a.c" + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+\\\$-1, \\(%r\[a-z0-9\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-4.c b/gcc/testsuite/gcc.target/i386/pr121062-4.c new file mode 100644 index 0000000..77a0c2e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64" } */ + +typedef long long int __attribute__((__vector_size__ (8))) S; + +void +foo (S *c) +{ + *c = (S){0x12345678badbeefULL}; +} + + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+%xmm\[0-9\]+, " 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movabsq\[ \\t\]+\\\$81985529250168559, %r\[a-z0-9\]+" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-5.c b/gcc/testsuite/gcc.target/i386/pr121062-5.c new file mode 100644 index 0000000..22c09a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-5.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64" } */ + +typedef int __attribute__((__vector_size__ (4))) S; + +void +foo (S *c) +{ + *c = (S){0x12345678}; +} + + +/* { dg-final { scan-assembler-times "movl\[ \\t\]+\\\$305419896, \\(%(e|r)\[a-z0-9\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-6.c b/gcc/testsuite/gcc.target/i386/pr121062-6.c new file mode 100644 index 0000000..780b496 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-6.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-Og -fno-dce -mtune=generic" } */ + +typedef int __attribute__((__vector_size__ (8))) S; + +void +foo (S *c) +{ + *c = (S){0x12345678,0xbadbeefULL}; +} + +/* { dg-final { scan-assembler-times "movq\[ \\t\]+%xmm\[0-9\]+, " 1 { target ia32 } } } */ +/* { dg-final { scan-assembler-times "movabsq\[ \\t\]+\\\$841538639400031864, %r\[a-z0-9\]+" 1 { target { ! ia32 } } } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr121062-7.c b/gcc/testsuite/gcc.target/i386/pr121062-7.c new file mode 100644 index 0000000..f1834f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr121062-7.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64" } */ + +typedef __bf16 __attribute__((__vector_size__ (4))) S; + +void +foo (S *c) +{ + *c = (S){-0.1, 2.1}; +} + + +/* { dg-final { scan-assembler-times "movl\[ \\t\]+\\\$1074183629, \\(%(e|r)\[a-z0-9\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/loongarch/pr121064.c b/gcc/testsuite/gcc.target/loongarch/pr121064.c new file mode 100644 index 0000000..a466c7a --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr121064.c @@ -0,0 +1,38 @@ +/* { dg-require-effective-target loongarch_sx_hw } */ +/* { dg-do run } */ +/* { dg-options "-march=loongarch64 -mfpu=64 -mlsx -O3" } */ + +typedef __INT32_TYPE__ int32_t; +typedef unsigned __INT32_TYPE__ uint32_t; + +__attribute__ ((noipa)) static int32_t +long_filter_ehigh_3830_1 (int32_t *buffer, int length) +{ + int i, j; + int32_t dotprod = 0; + int32_t delay[4] = { 0 }; + uint32_t coeffs[4] = { 0 }; + + for (i = 0; i < length; i++) + { + dotprod = 0; + for (j = 3; j >= 0; j--) + { + dotprod += delay[j] * coeffs[j]; + coeffs[j] += ((delay[j] >> 31) | 1); + } + for (j = 3; j > 0; j--) + delay[j] = delay[j - 1]; + delay[0] = buffer[i]; + } + + return dotprod; +} + +int +main () +{ + int32_t buffer[] = { -1, 1 }; + if (long_filter_ehigh_3830_1 (buffer, 2) != -1) + __builtin_trap (); +} diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c index 5095d50..312043b 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c +++ b/gcc/testsuite/gcc.target/powerpc/vsx-builtin-7.c @@ -1,8 +1,16 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-options "-O2 -mdejagnu-cpu=power7 -fno-inline-functions" } */ +/* { dg-options "-O2 -mdejagnu-cpu=power7 -fno-inline-functions -fno-ipa-icf" } */ /* { dg-require-effective-target powerpc_vsx } */ +/* PR testsuite/119382 + Note: Added -fno-ipa-icf to disable Interprocedural Identical Code + Folding (ICF). Without this, insert_di_0_v2 is merged with insert_di_0 + due to improved alias analysis introduced in commit r15-7961-gdc47161c1f32c3. + This results in the compiler replacing insert_di_0_v2 with a tail call to + insert_di_0, altering expected test behavior. Disabling ICF ensures correct + execution of the test. */ + /* Test simple extract/insert/slat operations. Make sure all types are supported with various options. */ diff --git a/gcc/testsuite/gcc.target/pru/pragma-ctable_entry-2.c b/gcc/testsuite/gcc.target/pru/pragma-ctable_entry-2.c new file mode 100644 index 0000000..a1c707d --- /dev/null +++ b/gcc/testsuite/gcc.target/pru/pragma-ctable_entry-2.c @@ -0,0 +1,22 @@ +/* Test for base addresses with bit 31 set (PR121124). */ + +/* { dg-do compile } */ +/* { dg-options "-O1" } */ + +/* -O1 in the options is significant. Without it LBCO/SBCO operations may + not be optimized to the respective instructions. */ + + +#pragma ctable_entry 12 0x80beef00 + +unsigned int +test_ctable (unsigned int val1, unsigned int val2) +{ + ((volatile unsigned short int *)0x80beef00)[0] = val2; + ((volatile unsigned int *)0x80beef00)[val1] = val2; + return ((volatile unsigned int *)0x80beef00)[5]; +} + +/* { dg-final { scan-assembler "sbco\\tr15.b\[012\]?, 12, 0, 2" } } */ +/* { dg-final { scan-assembler "sbco\\tr15.b0, 12, r14, 4" } } */ +/* { dg-final { scan-assembler "lbco\\tr14.b0, 12, 20, 4" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c b/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c index 81ebf5f..15cc3ee 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c @@ -1,7 +1,7 @@ /* Verify proper errors are generated for conflicted interrupt type. */ /* { dg-do compile } */ /* { dg-options "" } */ -void __attribute__ ((interrupt ("user"))) +void __attribute__ ((interrupt ("supervisor"))) foo(void); void __attribute__ ((interrupt ("machine"))) diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-rnmi.c b/gcc/testsuite/gcc.target/riscv/interrupt-rnmi.c new file mode 100644 index 0000000..f340108 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/interrupt-rnmi.c @@ -0,0 +1,11 @@ +/* Verify the return instruction is mnret. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_smrnmi" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_smrnmi" { target { rv64 } } } */ + +void __attribute__ ((interrupt ("rnmi"))) +foo (void) +{ +} + +/* { dg-final { scan-assembler {\mmnret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-umode.c b/gcc/testsuite/gcc.target/riscv/interrupt-umode.c deleted file mode 100644 index 042abf0..0000000 --- a/gcc/testsuite/gcc.target/riscv/interrupt-umode.c +++ /dev/null @@ -1,8 +0,0 @@ -/* Verify the return instruction is mret. */ -/* { dg-do compile } */ -/* { dg-options "" } */ -void __attribute__ ((interrupt ("user"))) -foo (void) -{ -} -/* { dg-final { scan-assembler {\muret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c index 138124c..31d3b43 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c @@ -6,7 +6,7 @@ #define NT int16_t #define WT int32_t -DEF_AVG_1(NT, WT, avg_ceil) +DEF_AVG_1_WRAP(NT, WT, avg_ceil) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c index 30438c9..7f30b9e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c @@ -6,7 +6,7 @@ #define NT int16_t #define WT int64_t -DEF_AVG_1(NT, WT, avg_ceil) +DEF_AVG_1_WRAP(NT, WT, avg_ceil) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c index 2e9cfa5..2e06d0a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c @@ -6,7 +6,7 @@ #define NT int32_t #define WT int64_t -DEF_AVG_1(NT, WT, avg_ceil) +DEF_AVG_1_WRAP(NT, WT, avg_ceil) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c new file mode 100644 index 0000000..ca23066 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int64_t +#define WT int128_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c index 2ebf294..dda84a6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c @@ -6,7 +6,7 @@ #define NT int8_t #define WT int16_t -DEF_AVG_1(NT, WT, avg_ceil) +DEF_AVG_1_WRAP(NT, WT, avg_ceil) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c index 64fec913..dfd2bb3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c @@ -6,7 +6,7 @@ #define NT int8_t #define WT int32_t -DEF_AVG_1(NT, WT, avg_ceil) +DEF_AVG_1_WRAP(NT, WT, avg_ceil) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c index a72642c..d1060cc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c @@ -6,7 +6,7 @@ #define NT int8_t #define WT int64_t -DEF_AVG_1(NT, WT, avg_ceil) +DEF_AVG_1_WRAP(NT, WT, avg_ceil) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c new file mode 100644 index 0000000..ee5330c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int128_t +#define NT int64_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h index a4a4536..49103f3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h @@ -345,8 +345,8 @@ int64_t TEST_AVG_DATA(int64_t, avg_ceil)[][3][N] = }, { 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, - 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, -2ull, -2ull, -2ull, -2ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, }, { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c index 16ba967..fc7943c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c @@ -6,7 +6,7 @@ #define NT int16_t #define WT int32_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c index b229b4b..e02e5df 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c @@ -6,7 +6,7 @@ #define NT int16_t #define WT int64_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c index 5f946bb..e36e424 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c @@ -6,7 +6,7 @@ #define NT int32_t #define WT int64_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c index c94dfc2..3e2d97d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c @@ -6,7 +6,7 @@ #define NT int64_t #define WT int128_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c index 5d9297a..cdbb299 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c @@ -6,7 +6,7 @@ #define NT int8_t #define WT int16_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c index 5c5d4ea..53508b0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c @@ -6,7 +6,7 @@ #define NT int8_t #define WT int32_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c index f297953..9a6d1a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c @@ -6,7 +6,7 @@ #define NT int8_t #define WT int64_t -DEF_AVG_0(NT, WT, avg_floor) +DEF_AVG_0_WRAP(NT, WT, avg_floor) /* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ /* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c index 4dc5703..0fa1ea0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c @@ -72,7 +72,7 @@ f_vnx128qi (int8_t *out) *(vnx128qi *) out = v; } -/* { dg-final { scan-assembler-times {vmv.v.x\tv[0-9]+,\s*[a-x0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {vmv.v.x\tv[0-9]+,\s*[a-x0-9]+} 7 } } */ /* { dg-final { scan-assembler-times {slli\t[a-x0-9]+,\s*[a-x0-9]+,\s*8} 6 } } */ /* { dg-final { scan-assembler-times {or\t[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+} 6 } } */ /* { dg-final { scan-assembler-times {vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c index b17fd8e..811f26c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c @@ -13,6 +13,8 @@ DEF_VF_MULOP_ACC_CASE_0 (_Float16, +, -, nacc) DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, -, nsac) DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -24,3 +26,5 @@ DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, +, sac) /* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c index efd887d..ca82ead 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c @@ -13,6 +13,8 @@ DEF_VF_MULOP_ACC_CASE_0 (float, +, -, nacc) DEF_VF_MULOP_ACC_CASE_0 (float, -, -, nsac) DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac) /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ @@ -24,3 +26,5 @@ DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, +, sac) /* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwmacc.vf} 1 } } */ /* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c index 84987a9..3a39303 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c @@ -13,5 +13,7 @@ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ -/* { dg-final { scan-assembler-times {fcvt.s.h} 2 } } */ -/* { dg-final { scan-assembler-times {vfmv.v.f} 10 } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-times {fcvt.s.h} 4 } } */ +/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c index dbd3d02..b4618bae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c @@ -13,5 +13,7 @@ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ -/* { dg-final { scan-assembler-times {fcvt.d.s} 2 } } */ -/* { dg-final { scan-assembler-times {vfmv.v.f} 10 } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-times {fcvt.d.s} 4 } } */ +/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c index 5f0d758..58afaa4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c @@ -13,6 +13,8 @@ DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, -, nacc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, -, nsac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -24,3 +26,5 @@ DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, +, sac) /* { dg-final { scan-assembler {vfnmsac.vf} } } */ /* { dg-final { scan-assembler {vfwmacc.vf} } } */ /* { dg-final { scan-assembler {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c index 951b0ef..0e95774 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c @@ -13,6 +13,8 @@ DEF_VF_MULOP_ACC_CASE_1 (float, +, -, nacc, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_ACC_CASE_1 (float, -, -, nsac, VF_MULOP_ACC_BODY_X128) DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, +, acc) DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac) /* { dg-final { scan-assembler {vfmadd.vf} } } */ /* { dg-final { scan-assembler {vfmsub.vf} } } */ @@ -24,3 +26,5 @@ DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, +, sac) /* { dg-final { scan-assembler {vfnmsac.vf} } } */ /* { dg-final { scan-assembler {vfwmacc.vf} } } */ /* { dg-final { scan-assembler {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c index a4edd92..559df6c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c @@ -13,4 +13,6 @@ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ /* { dg-final { scan-assembler {fcvt.s.h} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c index 4eb28e5..03f9c5a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c @@ -13,4 +13,6 @@ /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ /* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ /* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ /* { dg-final { scan-assembler {fcvt.d.s} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c index 982dd97..fd8aa30 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c @@ -1,5 +1,9 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ #include "vf_mulop.h" #include "vf_mulop_data.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c index 400bbcd..8fd8552 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c @@ -1,5 +1,9 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ #include "vf_mulop.h" #include "vf_mulop_data.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c index 21c1860..e91fd15 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c @@ -1,5 +1,9 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ #include "vf_mulop.h" #include "vf_mulop_data.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c index 163b5bd..ca7e0db 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c @@ -1,5 +1,9 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ #include "vf_mulop.h" #include "vf_mulop_data.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c index 71f350f..b38e800 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c @@ -1,5 +1,9 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ #include "vf_mulop.h" #include "vf_mulop_data.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c index e252e0d..fef5d77 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c @@ -1,5 +1,9 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ #include "vf_mulop.h" #include "vf_mulop_data.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c index 439fd3e..7951d40 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c @@ -1,5 +1,9 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ #include "vf_mulop.h" #include "vf_mulop_data.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c index b9d66ba..d0def86 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c @@ -1,5 +1,9 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ #include "vf_mulop.h" #include "vf_mulop_data.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c index d78cf73..d4c527a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c @@ -1,5 +1,9 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ #include "vf_mulop.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c index 6422bba..abce2f2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c @@ -1,5 +1,9 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ #include "vf_mulop.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c new file mode 100644 index 0000000..6be7d72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME nacc +#define OP + +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c new file mode 100644 index 0000000..851c335 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME nacc +#define OP + +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c new file mode 100644 index 0000000..dd28234 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-march=rv64gcv_zvfh --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME nsac +#define OP - +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c new file mode 100644 index 0000000..9eacace --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME nsac +#define OP - +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c index b064748..cb62e0f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -19,3 +19,4 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c index e334bb3..e2a5dbb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -19,3 +19,4 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c index 3e8ca05..e7b1ef0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -19,3 +19,4 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 1 { target { no-opts "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c index 1f995cd..559887e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c @@ -19,3 +19,4 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ /* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ /* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c index f7fae37..365e650 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -19,3 +19,4 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c index b111a4e..c8fd42a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -19,3 +19,4 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c index 4640d16..bdb76b4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -19,3 +19,4 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c index 58341ad..fc9c101 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c @@ -19,3 +19,4 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c index 406b999..121daeb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -19,3 +19,4 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c index 6792b6b..9616e7f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -19,3 +19,4 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c index 692a709..cf985f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -19,3 +19,4 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c index 4e30498..3bb382d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c @@ -19,3 +19,4 @@ TEST_BINARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c index afb5a85..c851f23 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c @@ -19,6 +19,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -32,3 +33,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler {vsaddu.vx} } } */ /* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c index a907e9b..b7805c1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c @@ -19,6 +19,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -31,3 +32,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vmaxu.vx} } } */ /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c index efabf99..8295dc2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c @@ -19,6 +19,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -32,3 +33,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} { target { no-opts "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c index 7b2b088..d214da9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c @@ -19,6 +19,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -32,3 +33,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler {vsaddu.vx} } } */ /* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c index da1b1be..b7c7ad4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c @@ -19,6 +19,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -32,3 +33,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler {vsaddu.vx} } } */ /* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c index b7ec6c9..dd9c845 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c @@ -19,6 +19,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -32,3 +33,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c index dce78b1..1fda062 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c @@ -19,6 +19,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -32,3 +33,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c index c5c6fb8..ee6d6aa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c @@ -19,6 +19,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -32,3 +33,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler {vsaddu.vx} } } */ /* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c index 5952a7c..3a215ea 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c @@ -19,6 +19,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -32,3 +33,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler {vsaddu.vx} } } */ /* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c index 5bbc585..ac4d100 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c @@ -19,6 +19,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -32,3 +33,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c index 255ae62..5eb0ed6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c @@ -19,6 +19,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) /* { dg-final { scan-assembler-not {vadd.vx} } } */ /* { dg-final { scan-assembler-not {vsub.vx} } } */ @@ -32,3 +33,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler-not {vminu.vx} } } */ /* { dg-final { scan-assembler-not {vsaddu.vx} } } */ /* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c index 63cd449..8b404b6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c @@ -19,6 +19,7 @@ DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) /* { dg-final { scan-assembler {vadd.vx} } } */ /* { dg-final { scan-assembler {vsub.vx} } } */ @@ -32,3 +33,4 @@ DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BOD /* { dg-final { scan-assembler {vminu.vx} } } */ /* { dg-final { scan-assembler {vsaddu.vx} } } */ /* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u16.c new file mode 100644 index 0000000..bd36429 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 8 + +#include "vx-fixed-vxrm.h" + +#define VT vuint16m1_t +#define T uint16_t +#define ELEM_SIZE 16 +#define SUFFIX u16 +#define FUNC __riscv_vaaddu_vv_u16m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u32.c new file mode 100644 index 0000000..f023a76 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 4 + +#include "vx-fixed-vxrm.h" + +#define VT vuint32m1_t +#define T uint32_t +#define ELEM_SIZE 32 +#define SUFFIX u32 +#define FUNC __riscv_vaaddu_vv_u32m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u64.c new file mode 100644 index 0000000..d9a37ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u64.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 2 + +#include "vx-fixed-vxrm.h" + +#define VT vuint64m1_t +#define T uint64_t +#define ELEM_SIZE 64 +#define SUFFIX u64 +#define FUNC __riscv_vaaddu_vv_u64m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u8.c new file mode 100644 index 0000000..328e5d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 16 + +#include "vx-fixed-vxrm.h" + +#define VT vuint8m1_t +#define T uint8_t +#define ELEM_SIZE 8 +#define SUFFIX u8 +#define FUNC __riscv_vaaddu_vv_u8m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm.h new file mode 100644 index 0000000..438c7ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm.h @@ -0,0 +1,28 @@ +#ifndef HAVE_DEFINED_VX_FIXED_VXRM_H +#define HAVE_DEFINED_VX_FIXED_VXRM_H + +#include <riscv_vector.h> + +int64_t go[VL] = {}; +int64_t ga[VL] = {}; + +#define DEF_FIXED_BINARY_VX(VT, T, ES, SX, VXRM, FUNC) \ +void __attribute__((noinline)) \ +test_fixed_binary_##VT##_##VXRM##_##FUNC##_vx () { \ + VT a = __riscv_vle##ES##_v_##SX##m1((T *)ga, VL); \ + VT b; \ + T *bp = (T *)&b; \ + \ + for (int i = 0; i < VL; i++) { \ + bp[i] = 123; \ + } \ + \ + VT d = FUNC (a, b, VXRM, VL); \ + \ + __riscv_vse##ES##_v_##SX##m1((T *)&go, d, VL); \ +} + +#define DEF_FIXED_BINARY_VX_WRAP(VT, T, ES, SX, VXRM, FUNC) \ + DEF_FIXED_BINARY_VX(VT, T, ES, SX, VXRM, FUNC) + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h index 6d4d720..38f2f72 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -3,6 +3,13 @@ #include <stdint.h> +#undef HAS_UINT128 + +#if __riscv_xlen == 64 +#define HAS_UINT128 +typedef unsigned __int128 uint128_t; +#endif + #define DEF_VX_BINARY_CASE_0(T, OP, NAME) \ void \ test_vx_binary_##NAME##_##T##_case_0 (T * restrict out, T * restrict in, \ @@ -340,6 +347,24 @@ DEF_SAT_S_SUB(int64_t, uint64_t, INT64_MIN, INT64_MAX) #define SAT_S_SUB_FUNC(T) test_##T##_sat_sub #define SAT_S_SUB_FUNC_WRAP(T) SAT_S_SUB_FUNC(T) +#define DEF_AVG_FLOOR(NT, WT) \ +NT \ +test_##NT##_avg_floor(NT x, NT y) \ +{ \ + return (NT)(((WT)x + (WT)y) >> 1); \ +} + +DEF_AVG_FLOOR(uint8_t, uint16_t) +DEF_AVG_FLOOR(uint16_t, uint32_t) +DEF_AVG_FLOOR(uint32_t, uint64_t) + +#ifdef HAS_UINT128 + DEF_AVG_FLOOR(uint64_t, uint128_t) +#endif + +#define AVG_FLOOR_FUNC(T) test_##T##_avg_floor +#define AVG_FLOOR_FUNC_WRAP(T) AVG_FLOOR_FUNC(T) + #define TEST_BINARY_VX_SIGNED_0(T) \ DEF_VX_BINARY_CASE_0_WRAP(T, +, add) \ DEF_VX_BINARY_CASE_0_WRAP(T, -, sub) \ @@ -357,20 +382,21 @@ DEF_SAT_S_SUB(int64_t, uint64_t, INT64_MIN, INT64_MAX) DEF_VX_BINARY_CASE_2_WRAP(T, SAT_S_ADD_FUNC(T), sat_add) \ DEF_VX_BINARY_CASE_2_WRAP(T, SAT_S_SUB_FUNC(T), sat_sub) \ -#define TEST_BINARY_VX_UNSIGNED_0(T) \ - DEF_VX_BINARY_CASE_0_WRAP(T, +, add) \ - DEF_VX_BINARY_CASE_0_WRAP(T, -, sub) \ - DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub) \ - DEF_VX_BINARY_CASE_0_WRAP(T, &, and) \ - DEF_VX_BINARY_CASE_0_WRAP(T, |, or) \ - DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) \ - DEF_VX_BINARY_CASE_0_WRAP(T, /, div) \ - DEF_VX_BINARY_CASE_0_WRAP(T, %, rem) \ - DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \ - DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \ - DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \ - DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_1_WARP(T), min) \ - DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_ADD_FUNC(T), sat_add) \ - DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_SUB_FUNC(T), sat_sub) \ +#define TEST_BINARY_VX_UNSIGNED_0(T) \ + DEF_VX_BINARY_CASE_0_WRAP(T, +, add) \ + DEF_VX_BINARY_CASE_0_WRAP(T, -, sub) \ + DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub) \ + DEF_VX_BINARY_CASE_0_WRAP(T, &, and) \ + DEF_VX_BINARY_CASE_0_WRAP(T, |, or) \ + DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) \ + DEF_VX_BINARY_CASE_0_WRAP(T, /, div) \ + DEF_VX_BINARY_CASE_0_WRAP(T, %, rem) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_1_WARP(T), min) \ + DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_ADD_FUNC(T), sat_add) \ + DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_SUB_FUNC(T), sat_sub) \ + DEF_VX_BINARY_CASE_2_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor) \ #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h index 47f6128..b742856 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -4906,4 +4906,200 @@ int64_t TEST_BINARY_DATA(int64_t, sat_sub)[][3][N] = }, }; +uint8_t TEST_BINARY_DATA(uint8_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + 191, 191, 191, 191, + 64, 64, 64, 64, + }, + }, + { + { 255 }, + { + 0, 0, 0, 0, + 255, 255, 255, 255, + 254, 254, 254, 254, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 255, 255, 255, 255, + 254, 254, 254, 254, + 128, 128, 128, 128, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 49151, 49151, 49151, 49151, + 16384, 16384, 16384, 16384, + }, + }, + { + { 65535 }, + { + 0, 0, 0, 0, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 32768, 32768, 32768, 32768, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 3221225471, 3221225471, 3221225471, 3221225471, + 1073741824, 1073741824, 1073741824, 1073741824, + }, + }, + { + { 4294967295 }, + { + 0, 0, 0, 0, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, + 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, + }, + }, + { + { 18446744073709551615ull }, + { + 0, 0, 0, 0, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u16.c new file mode 100644 index 0000000..73d1a57 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u32.c new file mode 100644 index 0000000..60a7aa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u64.c new file mode 100644 index 0000000..803bcba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u8.c new file mode 100644 index 0000000..f28147b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c index 04dec7b..4f6785a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c @@ -6,9 +6,9 @@ /* ** foo: -** addi\t[a-x0-9]+,\s*[a-x0-9]+,100 +** ... ** vsetvli\tzero,a2,e64,m2,t[au],m[au] -** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero +** vmv.s.x\tv[0-9]+.* ** vs2r.v\tv[0-9]+,0\([a-x0-9]+\) ** ret */ @@ -23,7 +23,7 @@ void foo (void *base, void *out, size_t vl) ** foo2: ** fld\tfa[0-9]+,\s*100\(a0\) ** vsetvli\tzero,a2,e64,m2,t[au],m[au] -** vfmv\.v\.f\tv[0-9]+,\s*fa[0-9]+ +** vfmv\.s\.f\tv[0-9]+,\s*fa[0-9]+ ** vs2r.v\tv[0-9]+,0\([a-x0-9]+\) ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c index 0ebb92e..a8c9263c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c @@ -23,7 +23,7 @@ void foo (void *base, void *out, size_t vl) ** foo2: ** fld\tfa[0-9]+,\s*100\(a0\) ** vsetvli\tzero,a2,e64,m2,t[au],m[au] -** vfmv\.v\.f\tv[0-9]+,\s*fa[0-9]+ +** vfmv\.s\.f\tv[0-9]+,\s*fa[0-9]+ ** vs2r.v\tv[0-9]+,0\([a-x0-9]+\) ** ret */ @@ -52,7 +52,7 @@ void foo3 (void *base, void *out, size_t vl) /* ** foo4: ** ... -** vfmv\.v\.f\tv[0-9]+,\s*fa[0-9]+ +** vfmv\.s\.f\tv[0-9]+,\s*fa[0-9]+ ** ... ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c index 512fa62..cf53aca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c @@ -6,9 +6,9 @@ /* ** foo: -** addi\t[a-x0-9]+,\s*[a-x0-9]+,100 +** ... ** vsetvli\tzero,a2,e64,m2,t[au],m[au] -** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero +** vmv\.v\.x\tv[0-9]+,\s*a[0-9]+ ** vs2r.v\tv[0-9]+,0\([a-x0-9]+\) ** ret */ @@ -37,7 +37,7 @@ void foo2 (void *base, void *out, size_t vl) /* ** foo3: ** ... -** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero +** vmv\.v\.x\tv[0-9]+,\s*a[0-9]+ ** ... ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-8.c index d9d10f3..fd3b7c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-8.c @@ -175,9 +175,8 @@ void foo12 (void *base, void *out, size_t vl) /* ** foo13: ** ... -** vmv.v.x\tv[0-9]+,\s*[a-x0-9]+ +** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero ** ... -** ret */ void foo13 (void *base, void *out, size_t vl) { @@ -189,7 +188,7 @@ void foo13 (void *base, void *out, size_t vl) /* ** foo14: ** ... -** vmv.v.x\tv[0-9]+,\s*[a-x0-9]+ +** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero ** ... */ void foo14 (void *base, void *out, size_t vl) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c index 80ee1b5..64c22dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c @@ -23,4 +23,3 @@ vuint64m2_t f3(vuint64m2_t var_17, uint64_t var_60, size_t vl) /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*0,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */ /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */ -/* { dg-final { scan-assembler-times {sgtu} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/pr121073.c b/gcc/testsuite/gcc.target/riscv/rvv/pr121073.c new file mode 100644 index 0000000..2789d0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/pr121073.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fsigned-char -fno-strict-aliasing -fwrapv -Wno-stringop-overflow -Wno-aggressive-loop-optimizations" } */ + +int a; +unsigned char p[1][21]; +void init() { + for (int s = 0; s < 21; ++s) + for (int t = 0; t < 21; ++t) + p[s][t] = 39; + for (short t = 0; t < 9; t += -5077966496202321318LL + 28071) + a = p[3][t] && p[2][t]; +} diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h index 7e2c93e..e40902a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h @@ -73,6 +73,22 @@ sat_u_add_##WT##_##T##_fmt_7(T x, T y) \ } #define DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) DEF_SAT_U_ADD_FMT_7(WT, T) +#define DEF_SAT_U_ADD_FMT_8(T) \ +T __attribute__((noinline)) \ +sat_u_add_##T##_fmt_8(T x, T y) \ +{ \ + return x <= (T)(x + y) ? (x + y) : -1; \ +} +#define DEF_SAT_U_ADD_FMT_8_WRAP(T) DEF_SAT_U_ADD_FMT_8(T) + +#define DEF_SAT_U_ADD_FMT_9(T) \ +T __attribute__((noinline)) \ +sat_u_add_##T##_fmt_9(T x, T y) \ +{ \ + return x > (T)(x + y) ? -1 : (x + y); \ +} +#define DEF_SAT_U_ADD_FMT_9_WRAP(T) DEF_SAT_U_ADD_FMT_9(T) + #define RUN_SAT_U_ADD_FMT_1(T, x, y) sat_u_add_##T##_fmt_1(x, y) #define RUN_SAT_U_ADD_FMT_1_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_1(T, x, y) #define RUN_SAT_U_ADD_FMT_2(T, x, y) sat_u_add_##T##_fmt_2(x, y) @@ -97,6 +113,10 @@ sat_u_add_##WT##_##T##_fmt_7(T x, T y) \ sat_u_add_uint64_t_##T##_fmt_7(x, y) #define RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T, x, y) \ RUN_SAT_U_ADD_FMT_7_FROM_U64(T, x, y) +#define RUN_SAT_U_ADD_FMT_8(T, x, y) sat_u_add_##T##_fmt_8(x, y) +#define RUN_SAT_U_ADD_FMT_8_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_8(T, x, y) +#define RUN_SAT_U_ADD_FMT_9(T, x, y) sat_u_add_##T##_fmt_9(x, y) +#define RUN_SAT_U_ADD_FMT_9_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_9(T, x, y) #define DEF_SAT_U_ADD_IMM_FMT_1(T, IMM) \ T __attribute__((noinline)) \ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u16.c new file mode 100644 index 0000000..a7062b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_8(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u32.c new file mode 100644 index 0000000..2e43c7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_8(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u64.c new file mode 100644 index 0000000..4ad18c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_8(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u8.c new file mode 100644 index 0000000..608d31b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_8(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u16.c new file mode 100644 index 0000000..b9766d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_9(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u32.c new file mode 100644 index 0000000..2456d39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_9(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u64.c new file mode 100644 index 0000000..0a0ff24 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_9(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u8.c new file mode 100644 index 0000000..53879dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_9(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u16.c new file mode 100644 index 0000000..aaf13be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_8_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_8_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u32.c new file mode 100644 index 0000000..0ec8d90 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_8_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_8_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u64.c new file mode 100644 index 0000000..f367f67 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_8_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_8_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u8.c new file mode 100644 index 0000000..0fd4036 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_8_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_8_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u16.c new file mode 100644 index 0000000..4289e2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_9_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_9_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u32.c new file mode 100644 index 0000000..d3dd52e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_9_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_9_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u64.c new file mode 100644 index 0000000..a9f0964 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_9_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_9_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u8.c new file mode 100644 index 0000000..91cdb7e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_9_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_9_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/xtheadint-push-pop.c b/gcc/testsuite/gcc.target/riscv/xtheadint-push-pop.c index dc5609c..167fa15 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadint-push-pop.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadint-push-pop.c @@ -20,12 +20,6 @@ void func_machine (void) /* { dg-final { scan-assembler-times {\mth\.ipop\M} 2 { target { rv32 } } } } */ -__attribute__ ((interrupt ("user"))) -void func_usr (void) -{ - f (); -} - __attribute__ ((interrupt ("supervisor"))) void func_supervisor (void) { diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-1.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-1.c new file mode 100644 index 0000000..671c0ed --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-1.c @@ -0,0 +1,103 @@ +/* { dg-do compile { target { lp64 } } } */ +/* { dg-options "-O2 -march=z13 -mzarch" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* +** test_in_1: +** foo %r2 +** br %r14 +*/ + +int +test_in_1 (int x) +{ + asm ("foo %0" :: "{r2}" (x)); + return x; +} + +/* +** test_in_2: +** lgr (%r[0-9]+),%r2 +** lr %r2,%r3 +** foo %r2 +** lgr %r2,\1 +** br %r14 +*/ + +int +test_in_2 (int x, int y) +{ + asm ("foo %0" :: "{r2}" (y)); + return x; +} + +/* +** test_in_3: +** stmg %r12,%r15,96\(%r15\) +** lay %r15,-160\(%r15\) +** lgr (%r[0-9]+),%r2 +** ahi %r2,1 +** lgfr %r2,%r2 +** brasl %r14,foo@PLT +** lr %r3,%r2 +** lr %r2,\1 +** foo %r3,%r2 +** lgr %r2,\1 +** lmg %r12,%r15,256\(%r15\) +** br %r14 +*/ + +extern int foo (int); + +int +test_in_3 (int x) +{ + asm ("foo %0,%1\n" :: "{r3}" (foo (x + 1)), "{r2}" (x)); + return x; +} + +/* +** test_out_1: +** foo %r3 +** lgfr %r2,%r3 +** br %r14 +*/ + +int +test_out_1 (void) +{ + int x; + asm ("foo %0" : "={r3}" (x)); + return x; +} + +/* +** test_out_2: +** lgr (%r[0-9]+),%r2 +** foo %r2 +** ark (%r[0-9]+),\1,%r2 +** lgfr %r2,\2 +** br %r14 +*/ + +int +test_out_2 (int x) +{ + int y; + asm ("foo %0" : "={r2}" (y)); + return x + y; +} + +/* +** test_inout_1: +** foo %r2 +** lgfr %r2,%r2 +** br %r14 +*/ + +int +test_inout_1 (int x) +{ + asm ("foo %0" : "+{r2}" (x)); + return x; +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-2.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-2.c new file mode 100644 index 0000000..a892fe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-2.c @@ -0,0 +1,43 @@ +/* { dg-do compile { target { lp64 } } } */ +/* { dg-options "-O2 -march=z13 -mzarch" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ +/* { dg-final { scan-assembler {\.LC0:\n\t\.long\t1078523331\n} } } */ + + +/* +** test_float_into_gpr: +** lrl %r4,.LC0 +** foo %r4 +** br %r14 +*/ + +void +test_float_into_gpr (void) +{ + // This is the counterpart to + // register float x asm ("r4") = 3.14f; + // asm ("foo %0" :: "r" (x)); + // where the bit-pattern of 3.14f is loaded into GPR. + asm ("foo %0" :: "{r4}" (3.14f)); +} + +/* +** test_float: +** ( +** ldr %f4,%f0 +** ldr %f5,%f2 +** | +** ldr %f5,%f2 +** ldr %f4,%f0 +** ) +** aebr %f5,%f4 +** ldr %f0,%f5 +** br %r14 +*/ + +float +test_float (float x, float y) +{ + asm ("aebr %0,%1" : "+{f5}" (y) : "{f4}" (x)); + return y; +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-3.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-3.c new file mode 100644 index 0000000..5df37b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-3.c @@ -0,0 +1,42 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -march=z13 -mzarch" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ +/* { dg-final { scan-assembler {\.LC0:\n\t\.long\t1074339512\n\t\.long\t1374389535\n} } } */ + +/* +** test_double_into_gpr: +** lgrl %r4,.LC0 +** foo %r4 +** br %r14 +*/ + +void +test_double_into_gpr (void) +{ + // This is the counterpart to + // register double x asm ("r4") = 3.14; + // asm ("foo %0" :: "r" (x)); + // where the bit-pattern of 3.14 is loaded into GPR. + asm ("foo %0" :: "{r4}" (3.14)); +} + +/* +** test_double: +** ( +** ldr %f4,%f0 +** ldr %f5,%f2 +** | +** ldr %f5,%f2 +** ldr %f4,%f0 +** ) +** adbr %f5,%f4 +** ldr %f0,%f5 +** br %r14 +*/ + +double +test_double (double x, double y) +{ + asm ("adbr %0,%1" : "+{f5}" (y) : "{f4}" (x)); + return y; +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-4.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-4.c new file mode 100644 index 0000000..29927ce --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-4.c @@ -0,0 +1,6 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2 -march=z13 -mzarch" } */ + +/* Test TARGET_MD_ASM_ADJUST for z13 and long double. */ + +#include "asm-hard-reg-longdouble.h" diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-5.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-5.c new file mode 100644 index 0000000..eaf34d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-5.c @@ -0,0 +1,6 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2 -march=z14 -mzarch" } */ + +/* Test TARGET_MD_ASM_ADJUST for z14 and long double. */ + +#include "asm-hard-reg-longdouble.h" diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-6.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-6.c new file mode 100644 index 0000000..d012966 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-6.c @@ -0,0 +1,152 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +test (void) +{ + // GPRs + { + int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p; + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14" + : "=r" (a), + "=r" (b), + "=r" (c), + "=r" (d), + "=r" (e), + "=r" (f), + "=r" (g), + "=r" (h), + "=r" (i), + "=r" (j), + "=r" (k), + "=r" (l), + "=r" (m), + "=r" (n), + "=r" (o)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14" + : "={r0}" (a), + "={r1}" (b), + "={r2}" (c), + "={r3}" (d), + "={r4}" (e), + "={r5}" (f), + "={r6}" (g), + "={r7}" (h), + "={r8}" (i), + "={r9}" (j), + "={r10}" (k), + "={r11}" (l), + "={r12}" (m), + "={r13}" (n), + "={r14}" (o)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15" /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + : "=r" (a), + "=r" (b), + "=r" (c), + "=r" (d), + "=r" (e), + "=r" (f), + "=r" (g), + "=r" (h), + "=r" (i), + "=r" (j), + "=r" (k), + "=r" (l), + "=r" (m), + "=r" (n), + "=r" (o), + "=r" (p)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15" /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + : "=r" (a), + "=r" (b), + "=r" (c), + "=r" (d), + "=r" (e), + "=r" (f), + "=r" (g), + "=r" (h), + "=r" (i), + "=r" (j), + "=r" (k), + "=r" (l), + "=r" (m), + "=r" (n), + "=r" (o), + "={r4}" (p)); + } + + // FPRs + { + float a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q; + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15" + : "=f" (a), + "=f" (b), + "=f" (c), + "=f" (d), + "=f" (e), + "=f" (f), + "=f" (g), + "=f" (h), + "=f" (i), + "=f" (j), + "=f" (k), + "=f" (l), + "=f" (m), + "=f" (n), + "=f" (o), + "=f" (p)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15" + : "={f0}" (a), + "={f1}" (b), + "={f2}" (c), + "={f3}" (d), + "={f4}" (e), + "={f5}" (f), + "={f6}" (g), + "={f7}" (h), + "={f8}" (i), + "={f9}" (j), + "={f10}" (k), + "={f11}" (l), + "={f12}" (m), + "={f13}" (n), + "={f14}" (o), + "={f15}" (p)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16" /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + : "=f" (a), + "=f" (b), + "=f" (c), + "=f" (d), + "=f" (e), + "=f" (f), + "=f" (g), + "=f" (h), + "=f" (i), + "=f" (j), + "=f" (k), + "=f" (l), + "=f" (m), + "=f" (n), + "=f" (o), + "=f" (p), + "=f" (q)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16" /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + : "=f" (a), + "=f" (b), + "=f" (c), + "=f" (d), + "=f" (e), + "=f" (f), + "=f" (g), + "=f" (h), + "=f" (i), + "=f" (j), + "=f" (k), + "=f" (l), + "=f" (m), + "=f" (n), + "=f" (o), + "=f" (p), + "={f4}" (q)); + } +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-7.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-7.c new file mode 100644 index 0000000..923c9d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-7.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=z13" } */ + +/* Test register pairs. */ + +void +test (void) +{ + register double f0 __asm__ ("f0"); + register double f2 __asm__ ("f2"); + register long double f0f2 __asm__ ("f0"); + double x; + long double y; + + /* Outputs */ + __asm__ __volatile__ ("" : "=r" (f0), "=r" (f0f2)); + __asm__ __volatile__ ("" : "=r" (f0f2), "={f0}" (y)); /* { dg-error "multiple outputs to hard register: %f0" } */ + __asm__ __volatile__ ("" : "={f0}" (x), "=r" (f0f2)); /* { dg-error "multiple outputs to hard register: %f0" } */ + + __asm__ __volatile__ ("" : "=r" (f2), "=r" (f0f2)); + __asm__ __volatile__ ("" : "={f2}" (x), "={f0}" (y)); /* { dg-error "multiple outputs to hard register: %f2" } */ + __asm__ __volatile__ ("" : "=r" (f2), "={f0}" (y)); /* { dg-error "multiple outputs to hard register: %f2" } */ + __asm__ __volatile__ ("" : "={f2}" (x), "=r" (f0f2)); /* { dg-error "multiple outputs to hard register: %f2" } */ + + /* Inputs */ + __asm__ __volatile__ ("" :: "r" (f0), "r" (f0f2)); + __asm__ __volatile__ ("" :: "r" (f0f2), "{f0}" (y)); /* { dg-error "multiple inputs to hard register: %f0" } */ + __asm__ __volatile__ ("" :: "{f0}" (x), "r" (f0f2)); /* { dg-error "multiple inputs to hard register: %f0" } */ + + __asm__ __volatile__ ("" :: "r" (f2), "r" (f0f2)); + __asm__ __volatile__ ("" :: "{f2}" (x), "{f0}" (y)); /* { dg-error "multiple inputs to hard register: %f2" } */ + __asm__ __volatile__ ("" :: "r" (f2), "{f0}" (y)); /* { dg-error "multiple inputs to hard register: %f2" } */ + __asm__ __volatile__ ("" :: "{f2}" (x), "r" (f0f2)); /* { dg-error "multiple inputs to hard register: %f2" } */ +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-longdouble.h b/gcc/testsuite/gcc.target/s390/asm-hard-reg-longdouble.h new file mode 100644 index 0000000..9f4adad --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-longdouble.h @@ -0,0 +1,18 @@ +__attribute__ ((noipa)) +long double +test_longdouble (long double x) +{ + long double y; + asm ("sqxbr\t%0,%1" : "={f4}" (y) : "{f5}" (x)); + return y; +} + +int +main (void) +{ + long double x = test_longdouble (42.L); + long double y = 6.48074069840786023096596743608799656681773277430814773408787249757445105002862106857719481922686100006103515625L; + if (x != y) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c index 2ff5a37..e1c7806 100644 --- a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c +++ b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c @@ -3,8 +3,10 @@ #include "isfinite-isinf-isnormal-signbit.h" -/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 1 } } SIGNBIT long double */ -/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 } } SIGNBIT _Decimal128 */ +/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 0 { target lp64 } } } SIGNBIT long double */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 0 { target lp64 } } } SIGNBIT _Decimal128 */ +/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } SIGNBIT long double */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } SIGNBIT _Decimal128 */ /* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,4032} 1 } } ISFINITE long double */ /* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,4032} 1 } } ISFINITE _Decimal128 */ /* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,48} 1 } } ISINF long double */ diff --git a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c index 8f67553..5c9986d 100644 --- a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c +++ b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c @@ -3,8 +3,10 @@ #include "isfinite-isinf-isnormal-signbit.h" -/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 1 } } */ -/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 } } */ +/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 0 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 0 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } */ /* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,4032} 1 } } */ /* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,4032} 1 } } */ /* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,48} 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/signbit-1.c b/gcc/testsuite/gcc.target/s390/signbit-1.c new file mode 100644 index 0000000..45f608a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -march=z900 -save-temps" } */ +/* { dg-final { scan-assembler-times {\ttceb\t} 2 } } */ +/* { dg-final { scan-assembler-times {\ttcdb\t} 2 } } */ +/* { dg-final { scan-assembler-times {\ttcxb\t} 2 } } */ + +/* Binary Floating-Point */ + +__attribute__ ((noipa)) +int signbit_float_reg (float x) { return __builtin_signbit (x); } +__attribute__ ((noipa)) +int signbit_float_mem (float *x) { return __builtin_signbit (*x); } +__attribute__ ((noipa)) +int signbit_double_reg (double x) { return __builtin_signbit (x); } +__attribute__ ((noipa)) +int signbit_double_mem (double *x) { return __builtin_signbit (*x); } + +__attribute__ ((noipa)) +int +signbit_longdouble_reg (long double x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +__attribute__ ((noipa)) +int signbit_longdouble_mem (long double *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (float, float, __builtin_inff(), __builtin_nanf("42"), 0.f, 42.f) +TEST (double, double, __builtin_inf(), __builtin_nan("42"), 0., 42.) +TEST (longdouble, long double, __builtin_infl(), __builtin_nanl("42"), 0.L, 42.L) + +int +main (void) +{ + test_float (); + test_double (); + test_longdouble (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit-2.c b/gcc/testsuite/gcc.target/s390/signbit-2.c new file mode 100644 index 0000000..488c477 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-2.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -march=z9-ec -mzarch -save-temps" } */ +/* { dg-final { scan-assembler-times {\ttdcet\t} 2 } } */ +/* { dg-final { scan-assembler-times {\ttdcdt\t} 2 } } */ +/* { dg-final { scan-assembler-times {\ttdcxt\t} 2 } } */ + +/* Decimal Floating-Point */ + +__attribute__ ((noipa)) +int signbit_dec32_reg (_Decimal32 x) { return __builtin_signbit (x); } +__attribute__ ((noipa)) +int signbit_dec32_mem (_Decimal32 *x) { return __builtin_signbit (*x); } +__attribute__ ((noipa)) +int signbit_dec64_reg (_Decimal64 x) { return __builtin_signbit (x); } +__attribute__ ((noipa)) +int signbit_dec64_mem (_Decimal64 *x) { return __builtin_signbit (*x); } + +__attribute__ ((noipa)) +int +signbit_dec128_reg (_Decimal128 x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +__attribute__ ((noipa)) +int signbit_dec128_mem (_Decimal128 *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (dec32, _Decimal32, __builtin_infd32(), __builtin_nand32("42"), 0.df, 42.df) +TEST (dec64, _Decimal64, __builtin_infd64(), __builtin_nand64("42"), 0.dd, 42.dd) +TEST (dec128, _Decimal128, __builtin_infd128(), __builtin_nand128("42"), 0.dl, 42.dl) + +int +main (void) +{ + test_dec32 (); + test_dec64 (); + test_dec128 (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit-3.c b/gcc/testsuite/gcc.target/s390/signbit-3.c new file mode 100644 index 0000000..2fad58b --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-3.c @@ -0,0 +1,152 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2 -march=z10 -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* Binary Floating-Point */ + +/* +** signbit_float_reg: +** lgdr (%r[0-9]+),%f0 +** srlg (%r[0-9]+),\1,63 +** lgfr %r2,\2 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_float_reg (float x) { return __builtin_signbit (x); } + +/* +** signbit_float_mem: +** l (%r[0-9]+),0\(%r2\) +** srl \1,31 +** lgfr %r2,\1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_float_mem (float *x) { return __builtin_signbit (*x); } + +/* +** signbit_double_reg: +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_double_reg (double x) { return __builtin_signbit (x); } + +/* +** signbit_double_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_double_mem (double *x) { return __builtin_signbit (*x); } + +/* +** signbit_longdouble_reg: +** ld %f0,0\(%r2\) +** ld %f2,8\(%r2\) +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int +signbit_longdouble_reg (long double x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +/* +** signbit_longdouble_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_longdouble_mem (long double *x) { return __builtin_signbit (*x); } + +/* Decimal Floating-Point */ + +/* +** signbit_dec32_reg: +** lgdr (%r[0-9]+),%f0 +** srlg (%r[0-9]+),\1,63 +** lgfr %r2,\2 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec32_reg (_Decimal32 x) { return __builtin_signbit (x); } + +/* +** signbit_dec32_mem: +** l (%r[0-9]+),0\(%r2\) +** srl \1,31 +** lgfr %r2,\1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec32_mem (_Decimal32 *x) { return __builtin_signbit (*x); } + +/* +** signbit_dec64_reg: +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec64_reg (_Decimal64 x) { return __builtin_signbit (x); } + +/* +** signbit_dec64_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec64_mem (_Decimal64 *x) { return __builtin_signbit (*x); } + +/* +** signbit_dec128_reg: +** ld %f0,0\(%r2\) +** ld %f2,8\(%r2\) +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int +signbit_dec128_reg (_Decimal128 x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +/* +** signbit_dec128_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec128_mem (_Decimal128 *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (float, float, __builtin_inff(), __builtin_nanf("42"), 0.f, 42.f) +TEST (double, double, __builtin_inf(), __builtin_nan("42"), 0., 42.) +TEST (longdouble, long double, __builtin_infl(), __builtin_nanl("42"), 0.L, 42.L) +TEST (dec32, _Decimal32, __builtin_infd32(), __builtin_nand32("42"), 0.df, 42.df) +TEST (dec64, _Decimal64, __builtin_infd64(), __builtin_nand64("42"), 0.dd, 42.dd) +TEST (dec128, _Decimal128, __builtin_infd128(), __builtin_nand128("42"), 0.dl, 42.dl) + +int +main (void) +{ + test_float (); + test_double (); + test_longdouble (); + test_dec32 (); + test_dec64 (); + test_dec128 (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit-4.c b/gcc/testsuite/gcc.target/s390/signbit-4.c new file mode 100644 index 0000000..2cb743e --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-4.c @@ -0,0 +1,55 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-require-effective-target s390_vx } */ +/* { dg-options "-O2 -march=z13 -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* Binary Floating-Point */ + +/* +** signbit_float_reg: +** vlgvf (%r[0-9]+),%v0,0 +** risbgn %r2,\1,64-1,128\+63,32\+1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_float_reg (float x) { return __builtin_signbit (x); } + +/* +** signbit_float_mem: +** l (%r[0-9]+),0\(%r2\) +** risbgn %r2,\1,64-1,128\+63,32\+1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_float_mem (float *x) { return __builtin_signbit (*x); } + +/* Decimal Floating-Point */ + +/* +** signbit_dec32_reg: +** vlgvf (%r[0-9]+),%v0,0 +** risbgn %r2,\1,64-1,128\+63,32\+1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec32_reg (_Decimal32 x) { return __builtin_signbit (x); } + +/* +** signbit_dec32_mem: +** l (%r[0-9]+),0\(%r2\) +** risbgn %r2,\1,64-1,128\+63,32\+1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec32_mem (_Decimal32 *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (float, float, __builtin_inff(), __builtin_nanf("42"), 0.f, 42.f) +TEST (dec32, _Decimal32, __builtin_infd32(), __builtin_nand32("42"), 0.df, 42.df) + +int +main (void) +{ + test_float (); + test_dec32 (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit-5.c b/gcc/testsuite/gcc.target/s390/signbit-5.c new file mode 100644 index 0000000..6840327 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-5.c @@ -0,0 +1,35 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2 -march=z14 -save-temps" } */ + +/* +** signbit_longdouble_reg: +** ld %f0,0(%r2);ld %f2,8+0(%r2) +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int +signbit_longdouble_reg (long double x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +/* +** signbit_longdouble_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_longdouble_mem (long double *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (longdouble, long double, __builtin_infl(), __builtin_nanl("42"), 0.L, 42.L) + +int +main (void) +{ + test_longdouble (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit.h b/gcc/testsuite/gcc.target/s390/signbit.h new file mode 100644 index 0000000..730e387 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit.h @@ -0,0 +1,36 @@ +#define TEST(T, U, I, N, C0, C42) \ + void test_##T (void) \ + { \ + U tmp; \ + int x; \ + \ + x = signbit_##T##_reg(C42); \ + x += signbit_##T##_reg(C0); \ + x += signbit_##T##_reg(I); \ + x += signbit_##T##_reg(N); \ + tmp = C42; \ + x += signbit_##T##_mem(&tmp); \ + tmp = C0; \ + x += signbit_##T##_mem(&tmp); \ + tmp = I; \ + x += signbit_##T##_mem(&tmp); \ + tmp = N; \ + x += signbit_##T##_mem(&tmp); \ + if (x != 0) \ + __builtin_abort(); \ + \ + x = signbit_##T##_reg(-C42); \ + x += signbit_##T##_reg(-C0); \ + x += signbit_##T##_reg(-I); \ + x += signbit_##T##_reg(-N); \ + tmp = -C42; \ + x += signbit_##T##_mem(&tmp); \ + tmp = -C0; \ + x += signbit_##T##_mem(&tmp); \ + tmp = -I; \ + x += signbit_##T##_mem(&tmp); \ + tmp = -N; \ + x += signbit_##T##_mem(&tmp); \ + if (x != 8) \ + __builtin_abort(); \ + } diff --git a/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c new file mode 100644 index 0000000..11df6c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c @@ -0,0 +1,71 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target s390_vx } */ +/* { dg-additional-options "-O2" } */ +/* { dg-final { scan-assembler-not {\tllg?[fhc]r\t} } } */ + +typedef unsigned char __attribute__ ((vector_size (1))) V1QI; +typedef unsigned char __attribute__ ((vector_size (2))) V2QI; +typedef unsigned char __attribute__ ((vector_size (4))) V4QI; +typedef unsigned char __attribute__ ((vector_size (8))) V8QI; +typedef unsigned char __attribute__ ((vector_size (16))) V16QI; + +typedef unsigned short __attribute__ ((vector_size (2))) V1HI; +typedef unsigned short __attribute__ ((vector_size (4))) V2HI; +typedef unsigned short __attribute__ ((vector_size (8))) V4HI; +typedef unsigned short __attribute__ ((vector_size (16))) V8HI; + +typedef unsigned int __attribute__ ((vector_size (4))) V1SI; +typedef unsigned int __attribute__ ((vector_size (8))) V2SI; +typedef unsigned int __attribute__ ((vector_size (16))) V4SI; + +unsigned short ushort; +unsigned int uint; + +#define TEST(T, U, I) \ + unsigned T test_ ## I ## _ ## U (U x) { return x[I]; } \ + void test_ ## I ## _ ## U ## _ushort (U x) { ushort = x[I]; } \ + void test_ ## I ## _ ## U ## _uint (U x) { uint = x[I]; } + +#define TEST1(T, U) \ + TEST(T, U, 0) + +#define TEST2(T, U) \ + TEST1 (T, U) \ + TEST(T, U, 1) + +#define TEST4(T, U) \ + TEST2 (T, U) \ + TEST(T, U, 2) \ + TEST(T, U, 3) + +#define TEST8(T, U) \ + TEST4 (T, U) \ + TEST(T, U, 4) \ + TEST(T, U, 5) \ + TEST(T, U, 6) \ + TEST(T, U, 7) + +#define TEST16(T, U) \ + TEST8 (T, U) \ + TEST(T, U, 9) \ + TEST(T, U, 10) \ + TEST(T, U, 11) \ + TEST(T, U, 12) \ + TEST(T, U, 13) \ + TEST(T, U, 14) \ + TEST(T, U, 15) + +TEST1 (char, V1QI) +TEST2 (char, V2QI) +TEST4 (char, V4QI) +TEST8 (char, V8QI) +TEST16 (char, V16QI) + +TEST1 (short, V1HI) +TEST2 (short, V2HI) +TEST4 (short, V4HI) +TEST8 (short, V8HI) + +TEST1 (int, V1SI) +TEST2 (int, V2SI) +TEST4 (int, V4SI) diff --git a/gcc/testsuite/gfortran.dg/array_constructor_58.f90 b/gcc/testsuite/gfortran.dg/array_constructor_58.f90 new file mode 100644 index 0000000..1473be0 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/array_constructor_58.f90 @@ -0,0 +1,17 @@ +!{ dg-do run } + +! Contributed by Federico Perini <federico.perini@gmail.com> +! Check that PR fortran/119106 is fixed. + +program char_param_array +implicit none +character, parameter :: p(5) = ['1','2','3','4','5'] +character, save :: n(5) = ['1','2','3','4','5'] +integer :: i(10), j + +i = 4 +if (any([(n(i(j)),j=1,10)] /= '4')) stop 1 ! OK +if (any([(p(i(j)),j=1,10)] /= '4')) stop 2 ! used to runtime out-of-bounds error + +end program char_param_array + diff --git a/gcc/testsuite/gfortran.dg/function_charlen_4.f90 b/gcc/testsuite/gfortran.dg/function_charlen_4.f90 new file mode 100644 index 0000000..ed39aca --- /dev/null +++ b/gcc/testsuite/gfortran.dg/function_charlen_4.f90 @@ -0,0 +1,34 @@ +! { dg-do run } +! { dg-options "-O2 -std=legacy -fdump-tree-optimized" } +! +! PR fortran/121203 - fix passing of character length of function to procedure + +program p + character(10), external :: f + call eval (f,"abc") + call eval2(f,"abc") +contains + subroutine eval2(func,c_arg) + character(*) c_arg + character(*) func + external func + ! These tests should get optimized: + if (len (c_arg) /= 3) stop 1 + if (len (func(c_arg)) /= 10) stop 2 + end subroutine +end + +character(10) function f(arg) + character(*) arg + f=arg +end + +subroutine eval(func,c_arg) + character(*) c_arg + character(*) func + external func + if (len (c_arg) /= 3) error stop 3 + if (len (func(c_arg)) /= 10) error stop 4 +end subroutine + +! { dg-final { scan-tree-dump-not "_gfortran_stop_numeric" "optimized" } } diff --git a/gcc/testsuite/gfortran.dg/pointer_check_15.f90 b/gcc/testsuite/gfortran.dg/pointer_check_15.f90 new file mode 100644 index 0000000..13c6820 --- /dev/null +++ b/gcc/testsuite/gfortran.dg/pointer_check_15.f90 @@ -0,0 +1,46 @@ +! { dg-do run } +! { dg-additional-options "-O -fcheck=pointer -fdump-tree-original" } +! +! PR fortran/121145 +! Erroneous runtime error: Proc-pointer actual argument 'ptr' is not associated +! +! Contributed by Federico Perini. + +module m + implicit none + + abstract interface + subroutine fun(x) + real, intent(in) :: x + end subroutine fun + end interface + +contains + + subroutine with_fun(sub) + procedure(fun), optional :: sub + if (present(sub)) stop 1 + end subroutine + + subroutine with_non_optional(sub) + procedure(fun) :: sub + end subroutine + +end module m + +program p + use m + implicit none + + procedure(fun), pointer :: ptr1 => null() + procedure(fun), pointer :: ptr2 => null() + + call with_fun() + call with_fun(sub=ptr1) ! no runtime check here + + if (associated (ptr2)) then + call with_non_optional(sub=ptr2) ! runtime check here + end if +end + +! { dg-final { scan-tree-dump-times "Proc-pointer actual argument .'ptr2.'" 1 "original" } } diff --git a/gcc/testsuite/gm2/switches/pedantic-params/fail/arrayofchar.def b/gcc/testsuite/gm2/switches/pedantic-params/fail/arrayofchar.def new file mode 100644 index 0000000..a24f7d3 --- /dev/null +++ b/gcc/testsuite/gm2/switches/pedantic-params/fail/arrayofchar.def @@ -0,0 +1,12 @@ +DEFINITION MODULE arrayofchar ; + +FROM FIO IMPORT File ; + +(* + Description: provides write procedures for ARRAY OF CHAR. +*) + +PROCEDURE Write (f: File; str: ARRAY OF CHAR) ; +PROCEDURE WriteLn (f: File) ; + +END arrayofchar. diff --git a/gcc/testsuite/gm2/switches/pedantic-params/fail/arrayofchar.mod b/gcc/testsuite/gm2/switches/pedantic-params/fail/arrayofchar.mod new file mode 100644 index 0000000..4e630a9 --- /dev/null +++ b/gcc/testsuite/gm2/switches/pedantic-params/fail/arrayofchar.mod @@ -0,0 +1,30 @@ +IMPLEMENTATION MODULE arrayofchar ; + +FROM FIO IMPORT WriteChar, WriteLine ; +IMPORT StrLib ; + + +(* + Write - writes a string to file f. +*) + +PROCEDURE Write (f: File; a: ARRAY OF CHAR) ; +VAR + len, i: CARDINAL ; +BEGIN + len := StrLib.StrLen (a) ; + i := 0 ; + WHILE i < len DO + WriteChar (f, a[i]) ; + INC (i) + END +END Write ; + + +PROCEDURE WriteLn (f: File) ; +BEGIN + WriteLine (f) +END WriteLn ; + + +END arrayofchar. diff --git a/gcc/testsuite/lib/gcc-defs.exp b/gcc/testsuite/lib/gcc-defs.exp index 2f8b7d4..d66c833 100644 --- a/gcc/testsuite/lib/gcc-defs.exp +++ b/gcc/testsuite/lib/gcc-defs.exp @@ -599,15 +599,16 @@ proc aarch64-arch-dg-options { args } { set add_arch 1 set add_tune 1 + set add_override 1 set checks_output [string equal [lindex $do_what 0] "compile"] set options [lindex $args 1] foreach option [split $options] { switch -glob -- $option { -march=* { set add_arch 0 } - -mcpu=* { set add_arch 0; set add_tune 0 } - -mtune=* { set add_tune 0 } - -moverride=* { set add_tune 0 } + -mcpu=* { set add_arch 0; set add_tune 0; set add_override 0} + -mtune=* { set add_tune 0; set add_override 0 } + -moverride=* { set add_override 0 } -save-temps { set checks_output 1 } --save-temps { set checks_output 1 } -fdump* { set checks_output 1 } @@ -619,9 +620,14 @@ proc aarch64-arch-dg-options { args } { append options " $aarch64_default_testing_arch" } - if { $add_tune && $checks_output } { + if { $checks_output } { # Turn off any default tuning and codegen tweaks. - append options " -mtune=generic -moverride=tune=none" + if { $add_tune } { + append options " -mtune=generic" + } + if { $add_override } { + append options " -moverride=tune=none" + } } uplevel 1 aarch64-old-dg-options [lreplace $args 1 1 $options] diff --git a/gcc/testsuite/lib/scanasm.exp b/gcc/testsuite/lib/scanasm.exp index a2311de..51952a6 100644 --- a/gcc/testsuite/lib/scanasm.exp +++ b/gcc/testsuite/lib/scanasm.exp @@ -896,6 +896,10 @@ proc configure_check-function-bodies { config } { set up_config(fluff) {^\s*(?://)} } elseif { [istarget *-*-darwin*] } { set up_config(fluff) {^\s*(?:\.|//|@)|^L[0-9ABCESV]} + } elseif { [istarget s390*-*-*] } { + # Additionally to the defaults skip lines beginning with a # resulting + # from inline asm. + set up_config(fluff) {^\s*(?:\.|//|@|$|#)} } else { # Skip lines beginning with labels ('.L[...]:') or other directives # ('.align', '.cfi_startproc', '.quad [...]', '.text', etc.), '//' or diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 4486a6a..e375b1e 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -1017,6 +1017,18 @@ proc check_effective_target_label_values {} { return 1 } + +# Return 1 if builtin_trap expands not into a call but an instruction, +# 0 otherwise. +proc check_effective_target_trap { } { + return [check_no_messages_and_pattern trap "!\\(call" rtl-expand { + void foo () + { + return __builtin_trap (); + } + } "" ] +} + # Return 1 if builtin_return_address and builtin_frame_address are # supported, 0 otherwise. @@ -2428,7 +2440,7 @@ proc check_effective_target_riscv_v_misalign_ok { } { = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; asm ("vsetivli zero,7,e8,m1,ta,ma"); asm ("addi a7,%0,1" : : "r" (a) : "a7" ); - asm ("vle8.v v8,0(a7)" : : : "v8"); + asm ("vle16.v v8,0(a7)" : : : "v8"); return 0; } } "-march=${gcc_march}"] } { return 1 } @@ -2685,6 +2697,14 @@ proc remove_options_for_riscv_zvbb { flags } { return [add_options_for_riscv_z_ext zvbb $flags] } +proc add_options_for_riscv_zvfh { flags } { + return [add_options_for_riscv_z_ext zvfh $flags] +} + +proc remove_options_for_riscv_zvfh { flags } { + return [add_options_for_riscv_z_ext zvfh $flags] +} + # Return 1 if the target is ia32 or x86_64. proc check_effective_target_x86 { } { @@ -5800,6 +5820,13 @@ proc add_options_for_aarch64_sve { flags } { return "$flags -march=armv8.2-a+sve" } +proc add_options_for_aarch64_sme { flags } { + if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sme] } { + return "$flags" + } + return "$flags -march=armv9-a+sme" +} + # Return 1 if this is an ARM target supporting the FP16 alternative # format. Some multilibs may be incompatible with the options needed. Also # set et_arm_fp16_alternative_flags to the best options to add. @@ -6539,6 +6566,22 @@ foreach N { 128 256 512 1024 2048 } { }] } +# Return true if this is an AArch64 target that can run SME code. + +proc check_effective_target_aarch64_sme_hw { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_runtime aarch64_sme_hw_available { + int + main (void) + { + asm volatile ("rdsvl x0, #1"); + return 0; + } + } [add_options_for_aarch64_sme ""]] +} + proc check_effective_target_arm_neonv2_hw { } { return [check_runtime arm_neon_hwv2_available { #include "arm_neon.h" |