x86_cse: Convert CONST_VECTOR load to constant integer loadHEADtrunkmaster

Convert CONST_VECTOR load no larger than integer register:

  (set (reg:V2SI 106)
       (const_vector:V2SI [(const_int 1 [1]) repeated x2]))

to constant integer load:

  (set (subreg:DI (reg:V2SI 106 [ _20 ]) 0)
       (const_int 4294967297 [0x100000001]))

and keep redundant constant integer load.  Generate zero CONST_VECTOR
load which works for both MMX and XMM registers.

Tested on Linux/x86-64 and Linux/i686.

gcc/

	PR target/125026
	PR target/125032
	* config/i386/i386-features.cc (ix86_place_single_vector_set):
	Don't check CONST_VECTOR load size.
	(replace_vector_const): Handle constant integer load.
	(x86_cse::x86_cse): Convert CONST_VECTOR load no larger than
	integer to constant integer load and keep redundant constant
	integer load.  Generate zero CONST_VECTOR load.

gcc/testsuite/

	PR target/125026
	PR target/125032
	* gcc.target/i386/pr125026.c: New test.
	* gcc.target/i386/pr125032-1.c: Likewise.
	* gcc.target/i386/pr125032-2.c: Likewise.

Signed-off-by: H.J. Lu <hjl.tools@gmail.com>

3 files changed, 63 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.target/i386/pr125026.c b/gcc/testsuite/gcc.target/i386/pr125026.c
new file mode 100644
index 000000000000..96ac6a9ef207
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr125026.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=x86-64" } */
+
+extern void a(int[]);
+int b;
+int d(int e, volatile int f) {
+  b = f - e;
+  int t[2] = {b, b};
+  a(t);
+}
+void g(int h[1]) {
+  if (d(0, 1))
+    h[0] = 0;
+  d(0, 1);
+}
+
+/* { dg-final { scan-assembler-times "movabsq\[ \\t\]+\\\$4294967297, %r\[a-z0-9\]+" 2 { target { ! ia32 } } } } */
+/* { dg-final { scan-assembler-not "xmm" { target { ! ia32 } } } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr125032-1.c b/gcc/testsuite/gcc.target/i386/pr125032-1.c
new file mode 100644
index 000000000000..7c54bab332aa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr125032-1.c
@@ -0,0 +1,30 @@
+/* { dg-do compile { target { ia32 && pie } } } */
+/* { dg-options "-O2 -march=i686 -mmmx -fPIE" } */
+
+typedef int __m64 __attribute__((__vector_size__(8)));
+typedef short __v4hi __attribute__((__vector_size__(8)));
+typedef char __v8qi __attribute__((__vector_size__(8)));
+int mmx_composite_over_n_8_0565_info_0, mmx_composite_over_n_8_0565_w;
+long long mmx_composite_over_n_8_0565_m3;
+__m64 mmx_composite_over_n_8_0565_v2, mmx_composite_over_n_8_0565_v3;
+__m64 in_over(__m64 src)
+{
+  __m64 __m1 = src, __m2;
+  return (__m64)__builtin_ia32_pmullw((__v4hi)__m1, (__v4hi)__m2);
+}
+__m64 load8888()
+{
+  __m64 __m2, __m1;
+  return (__m64)__builtin_ia32_punpcklbw((__v8qi)__m1, (__v8qi)__m2);
+}
+void mmx_composite_over_n_8_0565()
+{
+  __m64 vsrc = load8888();
+  mmx_composite_over_n_8_0565_w = mmx_composite_over_n_8_0565_info_0;
+  while (mmx_composite_over_n_8_0565_info_0)
+    if (mmx_composite_over_n_8_0565_m3)
+      {
+	mmx_composite_over_n_8_0565_v2 = in_over(vsrc);
+	mmx_composite_over_n_8_0565_v3 = in_over(vsrc);
+      }
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr125032-2.c b/gcc/testsuite/gcc.target/i386/pr125032-2.c
new file mode 100644
index 000000000000..71b072a7bfe2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr125032-2.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target fpic } } */
+/* { dg-options "-O2 -fPIC" } */
+
+long _HMAC_SHA256_Init_Klen;
+char _crypt_HMAC_SHA256_Init_pad[64];
+char _crypt_HMAC_SHA256_Init_pad_0, _crypt_HMAC_SHA256_Init_K_0;
+void _crypt_HMAC_SHA256_Init_i() {
+  if (_HMAC_SHA256_Init_Klen)
+    _HMAC_SHA256_Init_Klen = 2;
+  long __trans_tmp_1 =
+      __builtin_dynamic_object_size(_crypt_HMAC_SHA256_Init_pad, 0);
+  __builtin___memset_chk(_crypt_HMAC_SHA256_Init_pad, 2, 64, __trans_tmp_1);
+  for (; _HMAC_SHA256_Init_Klen;)
+    _crypt_HMAC_SHA256_Init_pad_0 ^= _crypt_HMAC_SHA256_Init_K_0;
+}