diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/s390')
24 files changed, 1038 insertions, 4 deletions
diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-1.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-1.c new file mode 100644 index 0000000..671c0ed --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-1.c @@ -0,0 +1,103 @@ +/* { dg-do compile { target { lp64 } } } */ +/* { dg-options "-O2 -march=z13 -mzarch" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* +** test_in_1: +** foo %r2 +** br %r14 +*/ + +int +test_in_1 (int x) +{ + asm ("foo %0" :: "{r2}" (x)); + return x; +} + +/* +** test_in_2: +** lgr (%r[0-9]+),%r2 +** lr %r2,%r3 +** foo %r2 +** lgr %r2,\1 +** br %r14 +*/ + +int +test_in_2 (int x, int y) +{ + asm ("foo %0" :: "{r2}" (y)); + return x; +} + +/* +** test_in_3: +** stmg %r12,%r15,96\(%r15\) +** lay %r15,-160\(%r15\) +** lgr (%r[0-9]+),%r2 +** ahi %r2,1 +** lgfr %r2,%r2 +** brasl %r14,foo@PLT +** lr %r3,%r2 +** lr %r2,\1 +** foo %r3,%r2 +** lgr %r2,\1 +** lmg %r12,%r15,256\(%r15\) +** br %r14 +*/ + +extern int foo (int); + +int +test_in_3 (int x) +{ + asm ("foo %0,%1\n" :: "{r3}" (foo (x + 1)), "{r2}" (x)); + return x; +} + +/* +** test_out_1: +** foo %r3 +** lgfr %r2,%r3 +** br %r14 +*/ + +int +test_out_1 (void) +{ + int x; + asm ("foo %0" : "={r3}" (x)); + return x; +} + +/* +** test_out_2: +** lgr (%r[0-9]+),%r2 +** foo %r2 +** ark (%r[0-9]+),\1,%r2 +** lgfr %r2,\2 +** br %r14 +*/ + +int +test_out_2 (int x) +{ + int y; + asm ("foo %0" : "={r2}" (y)); + return x + y; +} + +/* +** test_inout_1: +** foo %r2 +** lgfr %r2,%r2 +** br %r14 +*/ + +int +test_inout_1 (int x) +{ + asm ("foo %0" : "+{r2}" (x)); + return x; +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-2.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-2.c new file mode 100644 index 0000000..a892fe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-2.c @@ -0,0 +1,43 @@ +/* { dg-do compile { target { lp64 } } } */ +/* { dg-options "-O2 -march=z13 -mzarch" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ +/* { dg-final { scan-assembler {\.LC0:\n\t\.long\t1078523331\n} } } */ + + +/* +** test_float_into_gpr: +** lrl %r4,.LC0 +** foo %r4 +** br %r14 +*/ + +void +test_float_into_gpr (void) +{ + // This is the counterpart to + // register float x asm ("r4") = 3.14f; + // asm ("foo %0" :: "r" (x)); + // where the bit-pattern of 3.14f is loaded into GPR. + asm ("foo %0" :: "{r4}" (3.14f)); +} + +/* +** test_float: +** ( +** ldr %f4,%f0 +** ldr %f5,%f2 +** | +** ldr %f5,%f2 +** ldr %f4,%f0 +** ) +** aebr %f5,%f4 +** ldr %f0,%f5 +** br %r14 +*/ + +float +test_float (float x, float y) +{ + asm ("aebr %0,%1" : "+{f5}" (y) : "{f4}" (x)); + return y; +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-3.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-3.c new file mode 100644 index 0000000..5df37b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-3.c @@ -0,0 +1,42 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -march=z13 -mzarch" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ +/* { dg-final { scan-assembler {\.LC0:\n\t\.long\t1074339512\n\t\.long\t1374389535\n} } } */ + +/* +** test_double_into_gpr: +** lgrl %r4,.LC0 +** foo %r4 +** br %r14 +*/ + +void +test_double_into_gpr (void) +{ + // This is the counterpart to + // register double x asm ("r4") = 3.14; + // asm ("foo %0" :: "r" (x)); + // where the bit-pattern of 3.14 is loaded into GPR. + asm ("foo %0" :: "{r4}" (3.14)); +} + +/* +** test_double: +** ( +** ldr %f4,%f0 +** ldr %f5,%f2 +** | +** ldr %f5,%f2 +** ldr %f4,%f0 +** ) +** adbr %f5,%f4 +** ldr %f0,%f5 +** br %r14 +*/ + +double +test_double (double x, double y) +{ + asm ("adbr %0,%1" : "+{f5}" (y) : "{f4}" (x)); + return y; +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-4.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-4.c new file mode 100644 index 0000000..29927ce --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-4.c @@ -0,0 +1,6 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2 -march=z13 -mzarch" } */ + +/* Test TARGET_MD_ASM_ADJUST for z13 and long double. */ + +#include "asm-hard-reg-longdouble.h" diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-5.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-5.c new file mode 100644 index 0000000..eaf34d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-5.c @@ -0,0 +1,6 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2 -march=z14 -mzarch" } */ + +/* Test TARGET_MD_ASM_ADJUST for z14 and long double. */ + +#include "asm-hard-reg-longdouble.h" diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-6.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-6.c new file mode 100644 index 0000000..d012966 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-6.c @@ -0,0 +1,152 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +test (void) +{ + // GPRs + { + int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p; + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14" + : "=r" (a), + "=r" (b), + "=r" (c), + "=r" (d), + "=r" (e), + "=r" (f), + "=r" (g), + "=r" (h), + "=r" (i), + "=r" (j), + "=r" (k), + "=r" (l), + "=r" (m), + "=r" (n), + "=r" (o)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14" + : "={r0}" (a), + "={r1}" (b), + "={r2}" (c), + "={r3}" (d), + "={r4}" (e), + "={r5}" (f), + "={r6}" (g), + "={r7}" (h), + "={r8}" (i), + "={r9}" (j), + "={r10}" (k), + "={r11}" (l), + "={r12}" (m), + "={r13}" (n), + "={r14}" (o)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15" /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + : "=r" (a), + "=r" (b), + "=r" (c), + "=r" (d), + "=r" (e), + "=r" (f), + "=r" (g), + "=r" (h), + "=r" (i), + "=r" (j), + "=r" (k), + "=r" (l), + "=r" (m), + "=r" (n), + "=r" (o), + "=r" (p)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15" /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + : "=r" (a), + "=r" (b), + "=r" (c), + "=r" (d), + "=r" (e), + "=r" (f), + "=r" (g), + "=r" (h), + "=r" (i), + "=r" (j), + "=r" (k), + "=r" (l), + "=r" (m), + "=r" (n), + "=r" (o), + "={r4}" (p)); + } + + // FPRs + { + float a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q; + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15" + : "=f" (a), + "=f" (b), + "=f" (c), + "=f" (d), + "=f" (e), + "=f" (f), + "=f" (g), + "=f" (h), + "=f" (i), + "=f" (j), + "=f" (k), + "=f" (l), + "=f" (m), + "=f" (n), + "=f" (o), + "=f" (p)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15" + : "={f0}" (a), + "={f1}" (b), + "={f2}" (c), + "={f3}" (d), + "={f4}" (e), + "={f5}" (f), + "={f6}" (g), + "={f7}" (h), + "={f8}" (i), + "={f9}" (j), + "={f10}" (k), + "={f11}" (l), + "={f12}" (m), + "={f13}" (n), + "={f14}" (o), + "={f15}" (p)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16" /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + : "=f" (a), + "=f" (b), + "=f" (c), + "=f" (d), + "=f" (e), + "=f" (f), + "=f" (g), + "=f" (h), + "=f" (i), + "=f" (j), + "=f" (k), + "=f" (l), + "=f" (m), + "=f" (n), + "=f" (o), + "=f" (p), + "=f" (q)); + __asm__ __volatile__ ("%0 %1 %2 %3 %4 %5 %6 %7 %8 %9 %10 %11 %12 %13 %14 %15 %16" /* { dg-error "'asm' operand has impossible constraints or there are not enough registers" } */ + : "=f" (a), + "=f" (b), + "=f" (c), + "=f" (d), + "=f" (e), + "=f" (f), + "=f" (g), + "=f" (h), + "=f" (i), + "=f" (j), + "=f" (k), + "=f" (l), + "=f" (m), + "=f" (n), + "=f" (o), + "=f" (p), + "={f4}" (q)); + } +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-7.c b/gcc/testsuite/gcc.target/s390/asm-hard-reg-7.c new file mode 100644 index 0000000..923c9d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-7.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-march=z13" } */ + +/* Test register pairs. */ + +void +test (void) +{ + register double f0 __asm__ ("f0"); + register double f2 __asm__ ("f2"); + register long double f0f2 __asm__ ("f0"); + double x; + long double y; + + /* Outputs */ + __asm__ __volatile__ ("" : "=r" (f0), "=r" (f0f2)); + __asm__ __volatile__ ("" : "=r" (f0f2), "={f0}" (y)); /* { dg-error "multiple outputs to hard register: %f0" } */ + __asm__ __volatile__ ("" : "={f0}" (x), "=r" (f0f2)); /* { dg-error "multiple outputs to hard register: %f0" } */ + + __asm__ __volatile__ ("" : "=r" (f2), "=r" (f0f2)); + __asm__ __volatile__ ("" : "={f2}" (x), "={f0}" (y)); /* { dg-error "multiple outputs to hard register: %f2" } */ + __asm__ __volatile__ ("" : "=r" (f2), "={f0}" (y)); /* { dg-error "multiple outputs to hard register: %f2" } */ + __asm__ __volatile__ ("" : "={f2}" (x), "=r" (f0f2)); /* { dg-error "multiple outputs to hard register: %f2" } */ + + /* Inputs */ + __asm__ __volatile__ ("" :: "r" (f0), "r" (f0f2)); + __asm__ __volatile__ ("" :: "r" (f0f2), "{f0}" (y)); /* { dg-error "multiple inputs to hard register: %f0" } */ + __asm__ __volatile__ ("" :: "{f0}" (x), "r" (f0f2)); /* { dg-error "multiple inputs to hard register: %f0" } */ + + __asm__ __volatile__ ("" :: "r" (f2), "r" (f0f2)); + __asm__ __volatile__ ("" :: "{f2}" (x), "{f0}" (y)); /* { dg-error "multiple inputs to hard register: %f2" } */ + __asm__ __volatile__ ("" :: "r" (f2), "{f0}" (y)); /* { dg-error "multiple inputs to hard register: %f2" } */ + __asm__ __volatile__ ("" :: "{f2}" (x), "r" (f0f2)); /* { dg-error "multiple inputs to hard register: %f2" } */ +} diff --git a/gcc/testsuite/gcc.target/s390/asm-hard-reg-longdouble.h b/gcc/testsuite/gcc.target/s390/asm-hard-reg-longdouble.h new file mode 100644 index 0000000..9f4adad --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/asm-hard-reg-longdouble.h @@ -0,0 +1,18 @@ +__attribute__ ((noipa)) +long double +test_longdouble (long double x) +{ + long double y; + asm ("sqxbr\t%0,%1" : "={f4}" (y) : "{f5}" (x)); + return y; +} + +int +main (void) +{ + long double x = test_longdouble (42.L); + long double y = 6.48074069840786023096596743608799656681773277430814773408787249757445105002862106857719481922686100006103515625L; + if (x != y) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c index 2ff5a37..e1c7806 100644 --- a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c +++ b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-2.c @@ -3,8 +3,10 @@ #include "isfinite-isinf-isnormal-signbit.h" -/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 1 } } SIGNBIT long double */ -/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 } } SIGNBIT _Decimal128 */ +/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 0 { target lp64 } } } SIGNBIT long double */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 0 { target lp64 } } } SIGNBIT _Decimal128 */ +/* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } SIGNBIT long double */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } SIGNBIT _Decimal128 */ /* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,4032} 1 } } ISFINITE long double */ /* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,4032} 1 } } ISFINITE _Decimal128 */ /* { dg-final { scan-assembler-times {tcxb\t%f[0-9]+,48} 1 } } ISINF long double */ diff --git a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c index 8f67553..5c9986d 100644 --- a/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c +++ b/gcc/testsuite/gcc.target/s390/isfinite-isinf-isnormal-signbit-3.c @@ -3,8 +3,10 @@ #include "isfinite-isinf-isnormal-signbit.h" -/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 1 } } */ -/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 } } */ +/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 0 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 0 { target lp64 } } } */ +/* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,1365} 1 { target { ! lp64 } } } } */ +/* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,1365} 1 { target { ! lp64 } } } } */ /* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,4032} 1 } } */ /* { dg-final { scan-assembler-times {tdcxt\t%f[0-9]+,4032} 1 } } */ /* { dg-final { scan-assembler-times {wftcixb\t%v[0-9]+,%v[0-9]+,48} 1 } } */ diff --git a/gcc/testsuite/gcc.target/s390/signbit-1.c b/gcc/testsuite/gcc.target/s390/signbit-1.c new file mode 100644 index 0000000..45f608a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-1.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -march=z900 -save-temps" } */ +/* { dg-final { scan-assembler-times {\ttceb\t} 2 } } */ +/* { dg-final { scan-assembler-times {\ttcdb\t} 2 } } */ +/* { dg-final { scan-assembler-times {\ttcxb\t} 2 } } */ + +/* Binary Floating-Point */ + +__attribute__ ((noipa)) +int signbit_float_reg (float x) { return __builtin_signbit (x); } +__attribute__ ((noipa)) +int signbit_float_mem (float *x) { return __builtin_signbit (*x); } +__attribute__ ((noipa)) +int signbit_double_reg (double x) { return __builtin_signbit (x); } +__attribute__ ((noipa)) +int signbit_double_mem (double *x) { return __builtin_signbit (*x); } + +__attribute__ ((noipa)) +int +signbit_longdouble_reg (long double x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +__attribute__ ((noipa)) +int signbit_longdouble_mem (long double *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (float, float, __builtin_inff(), __builtin_nanf("42"), 0.f, 42.f) +TEST (double, double, __builtin_inf(), __builtin_nan("42"), 0., 42.) +TEST (longdouble, long double, __builtin_infl(), __builtin_nanl("42"), 0.L, 42.L) + +int +main (void) +{ + test_float (); + test_double (); + test_longdouble (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit-2.c b/gcc/testsuite/gcc.target/s390/signbit-2.c new file mode 100644 index 0000000..488c477 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-2.c @@ -0,0 +1,40 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -march=z9-ec -mzarch -save-temps" } */ +/* { dg-final { scan-assembler-times {\ttdcet\t} 2 } } */ +/* { dg-final { scan-assembler-times {\ttdcdt\t} 2 } } */ +/* { dg-final { scan-assembler-times {\ttdcxt\t} 2 } } */ + +/* Decimal Floating-Point */ + +__attribute__ ((noipa)) +int signbit_dec32_reg (_Decimal32 x) { return __builtin_signbit (x); } +__attribute__ ((noipa)) +int signbit_dec32_mem (_Decimal32 *x) { return __builtin_signbit (*x); } +__attribute__ ((noipa)) +int signbit_dec64_reg (_Decimal64 x) { return __builtin_signbit (x); } +__attribute__ ((noipa)) +int signbit_dec64_mem (_Decimal64 *x) { return __builtin_signbit (*x); } + +__attribute__ ((noipa)) +int +signbit_dec128_reg (_Decimal128 x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +__attribute__ ((noipa)) +int signbit_dec128_mem (_Decimal128 *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (dec32, _Decimal32, __builtin_infd32(), __builtin_nand32("42"), 0.df, 42.df) +TEST (dec64, _Decimal64, __builtin_infd64(), __builtin_nand64("42"), 0.dd, 42.dd) +TEST (dec128, _Decimal128, __builtin_infd128(), __builtin_nand128("42"), 0.dl, 42.dl) + +int +main (void) +{ + test_dec32 (); + test_dec64 (); + test_dec128 (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit-3.c b/gcc/testsuite/gcc.target/s390/signbit-3.c new file mode 100644 index 0000000..2fad58b --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-3.c @@ -0,0 +1,152 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2 -march=z10 -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* Binary Floating-Point */ + +/* +** signbit_float_reg: +** lgdr (%r[0-9]+),%f0 +** srlg (%r[0-9]+),\1,63 +** lgfr %r2,\2 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_float_reg (float x) { return __builtin_signbit (x); } + +/* +** signbit_float_mem: +** l (%r[0-9]+),0\(%r2\) +** srl \1,31 +** lgfr %r2,\1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_float_mem (float *x) { return __builtin_signbit (*x); } + +/* +** signbit_double_reg: +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_double_reg (double x) { return __builtin_signbit (x); } + +/* +** signbit_double_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_double_mem (double *x) { return __builtin_signbit (*x); } + +/* +** signbit_longdouble_reg: +** ld %f0,0\(%r2\) +** ld %f2,8\(%r2\) +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int +signbit_longdouble_reg (long double x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +/* +** signbit_longdouble_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_longdouble_mem (long double *x) { return __builtin_signbit (*x); } + +/* Decimal Floating-Point */ + +/* +** signbit_dec32_reg: +** lgdr (%r[0-9]+),%f0 +** srlg (%r[0-9]+),\1,63 +** lgfr %r2,\2 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec32_reg (_Decimal32 x) { return __builtin_signbit (x); } + +/* +** signbit_dec32_mem: +** l (%r[0-9]+),0\(%r2\) +** srl \1,31 +** lgfr %r2,\1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec32_mem (_Decimal32 *x) { return __builtin_signbit (*x); } + +/* +** signbit_dec64_reg: +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec64_reg (_Decimal64 x) { return __builtin_signbit (x); } + +/* +** signbit_dec64_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec64_mem (_Decimal64 *x) { return __builtin_signbit (*x); } + +/* +** signbit_dec128_reg: +** ld %f0,0\(%r2\) +** ld %f2,8\(%r2\) +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int +signbit_dec128_reg (_Decimal128 x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +/* +** signbit_dec128_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec128_mem (_Decimal128 *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (float, float, __builtin_inff(), __builtin_nanf("42"), 0.f, 42.f) +TEST (double, double, __builtin_inf(), __builtin_nan("42"), 0., 42.) +TEST (longdouble, long double, __builtin_infl(), __builtin_nanl("42"), 0.L, 42.L) +TEST (dec32, _Decimal32, __builtin_infd32(), __builtin_nand32("42"), 0.df, 42.df) +TEST (dec64, _Decimal64, __builtin_infd64(), __builtin_nand64("42"), 0.dd, 42.dd) +TEST (dec128, _Decimal128, __builtin_infd128(), __builtin_nand128("42"), 0.dl, 42.dl) + +int +main (void) +{ + test_float (); + test_double (); + test_longdouble (); + test_dec32 (); + test_dec64 (); + test_dec128 (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit-4.c b/gcc/testsuite/gcc.target/s390/signbit-4.c new file mode 100644 index 0000000..2cb743e --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-4.c @@ -0,0 +1,55 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-require-effective-target s390_vx } */ +/* { dg-options "-O2 -march=z13 -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* Binary Floating-Point */ + +/* +** signbit_float_reg: +** vlgvf (%r[0-9]+),%v0,0 +** risbgn %r2,\1,64-1,128\+63,32\+1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_float_reg (float x) { return __builtin_signbit (x); } + +/* +** signbit_float_mem: +** l (%r[0-9]+),0\(%r2\) +** risbgn %r2,\1,64-1,128\+63,32\+1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_float_mem (float *x) { return __builtin_signbit (*x); } + +/* Decimal Floating-Point */ + +/* +** signbit_dec32_reg: +** vlgvf (%r[0-9]+),%v0,0 +** risbgn %r2,\1,64-1,128\+63,32\+1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec32_reg (_Decimal32 x) { return __builtin_signbit (x); } + +/* +** signbit_dec32_mem: +** l (%r[0-9]+),0\(%r2\) +** risbgn %r2,\1,64-1,128\+63,32\+1 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_dec32_mem (_Decimal32 *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (float, float, __builtin_inff(), __builtin_nanf("42"), 0.f, 42.f) +TEST (dec32, _Decimal32, __builtin_infd32(), __builtin_nand32("42"), 0.df, 42.df) + +int +main (void) +{ + test_float (); + test_dec32 (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit-5.c b/gcc/testsuite/gcc.target/s390/signbit-5.c new file mode 100644 index 0000000..6840327 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit-5.c @@ -0,0 +1,35 @@ +/* { dg-do run { target lp64 } } */ +/* { dg-options "-O2 -march=z14 -save-temps" } */ + +/* +** signbit_longdouble_reg: +** ld %f0,0(%r2);ld %f2,8+0(%r2) +** lgdr (%r[0-9]+),%f0 +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int +signbit_longdouble_reg (long double x) +{ + __asm__ ("" : "+f" (x)); + return __builtin_signbit (x); +} + +/* +** signbit_longdouble_mem: +** lg (%r[0-9]+),0\(%r2\) +** srlg %r2,\1,63 +** br %r14 +*/ +__attribute__ ((noipa)) +int signbit_longdouble_mem (long double *x) { return __builtin_signbit (*x); } + +#include "signbit.h" +TEST (longdouble, long double, __builtin_infl(), __builtin_nanl("42"), 0.L, 42.L) + +int +main (void) +{ + test_longdouble (); +} diff --git a/gcc/testsuite/gcc.target/s390/signbit.h b/gcc/testsuite/gcc.target/s390/signbit.h new file mode 100644 index 0000000..730e387 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/signbit.h @@ -0,0 +1,36 @@ +#define TEST(T, U, I, N, C0, C42) \ + void test_##T (void) \ + { \ + U tmp; \ + int x; \ + \ + x = signbit_##T##_reg(C42); \ + x += signbit_##T##_reg(C0); \ + x += signbit_##T##_reg(I); \ + x += signbit_##T##_reg(N); \ + tmp = C42; \ + x += signbit_##T##_mem(&tmp); \ + tmp = C0; \ + x += signbit_##T##_mem(&tmp); \ + tmp = I; \ + x += signbit_##T##_mem(&tmp); \ + tmp = N; \ + x += signbit_##T##_mem(&tmp); \ + if (x != 0) \ + __builtin_abort(); \ + \ + x = signbit_##T##_reg(-C42); \ + x += signbit_##T##_reg(-C0); \ + x += signbit_##T##_reg(-I); \ + x += signbit_##T##_reg(-N); \ + tmp = -C42; \ + x += signbit_##T##_mem(&tmp); \ + tmp = -C0; \ + x += signbit_##T##_mem(&tmp); \ + tmp = -I; \ + x += signbit_##T##_mem(&tmp); \ + tmp = -N; \ + x += signbit_##T##_mem(&tmp); \ + if (x != 8) \ + __builtin_abort(); \ + } diff --git a/gcc/testsuite/gcc.target/s390/spaceship-fp-1.c b/gcc/testsuite/gcc.target/s390/spaceship-fp-1.c new file mode 100644 index 0000000..56c3d77 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-fp-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 2\)} 3 optimized } } */ +/* { dg-final { scan-assembler-times {\tk[edx]br\t} 3 } } */ +/* { dg-final { scan-assembler-not {\tbrc} } } */ +/* { dg-final { scan-assembler-not {\tc[edx]br\t} } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else if (x > y) \ + return 1; \ + else \ + return 2; \ + } + +TEST (float, float) +TEST (double, double) +TEST (long double, longdouble) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-fp-2.c b/gcc/testsuite/gcc.target/s390/spaceship-fp-2.c new file mode 100644 index 0000000..0c6e6b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-fp-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -ffinite-math-only -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 2\)} 3 optimized } } */ +/* { dg-final { scan-assembler-times {\tc[edx]br\t} 3 } } */ +/* { dg-final { scan-assembler-not {\tbrc} } } */ +/* { dg-final { scan-assembler-not {\tk[edx]br\t} } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else if (x > y) \ + return 1; \ + else \ + return 2; \ + } + +TEST (float, float) +TEST (double, double) +TEST (long double, longdouble) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-fp-3.c b/gcc/testsuite/gcc.target/s390/spaceship-fp-3.c new file mode 100644 index 0000000..2f567d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-fp-3.c @@ -0,0 +1,23 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 42\)} 3 optimized } } */ +/* { dg-final { scan-assembler-times {\tk[edx]br\t} 3 } } */ +/* { dg-final { scan-assembler-not {\tbrc} } } */ +/* { dg-final { scan-assembler-not {\tc[edx]br\t} } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else if (x > y) \ + return 1; \ + else \ + return 42; \ + } + +TEST (float, float) +TEST (double, double) +TEST (long double, longdouble) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-fp-4.c b/gcc/testsuite/gcc.target/s390/spaceship-fp-4.c new file mode 100644 index 0000000..4531ecb --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-fp-4.c @@ -0,0 +1,53 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 0\)} 3 optimized } } */ +/* { dg-final { scan-assembler-times {\tk[edx]br\t} 3 } } */ +/* { dg-final { scan-assembler-not {\tloc} } } */ +/* { dg-final { scan-assembler-not {\tbrc} } } */ +/* { dg-final { scan-assembler-not {\tc[edx]br\t} } } */ + +/* By time of writing this we emit + + kebr %f0,%f2 + jo .L2 + je .L3 + jnh .L10 + jg f3@PLT +.L10: + jg f2@PLT +.L3: + jg f1@PLT +.L2: + jg f4@PLT + + which is not optimal. Instead we could fold the conditional branch with the + unconditional into something along the lines + + kebr %f0,%f2 + jo f4@PLT + je f1@PLT + jnh f2@PLT + jg f3@PLT +*/ + +void f1 (void); +void f2 (void); +void f3 (void); +void f4 (void); + +#define TEST(T, U) \ + void test_##U (T x, T y) \ + { \ + if (x == y) \ + f1 (); \ + else if (x < y) \ + f2 (); \ + else if (x > y) \ + f3 (); \ + else \ + f4 (); \ + } + +TEST (float, float) +TEST (double, double) +TEST (long double, longdouble) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-int-1.c b/gcc/testsuite/gcc.target/s390/spaceship-int-1.c new file mode 100644 index 0000000..8ca2677 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-int-1.c @@ -0,0 +1,30 @@ +/* { dg-do compile { target lp64 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, -1\)} 4 optimized } } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 1\)} 5 optimized } } */ +/* { dg-final { scan-assembler-times {\tlhi} 9 } } */ +/* { dg-final { scan-assembler-times {\tloc} 18 } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else \ + return 1; \ + } + +TEST(signed char, schar) +TEST(unsigned char, uchar) +TEST(char, char) + +TEST(short, sshort) +TEST(unsigned short, ushort) + +TEST(int, sint) +TEST(unsigned int, uint) + +TEST(long, slong) +TEST(unsigned long, ulong) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-int-2.c b/gcc/testsuite/gcc.target/s390/spaceship-int-2.c new file mode 100644 index 0000000..5f7975c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-int-2.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mzarch -march=z13 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, -1\)} 1 optimized } } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 1\)} 1 optimized } } */ +/* { dg-final { scan-assembler-times {\tvecg} 1 } } */ +/* { dg-final { scan-assembler-times {\tveclg} 1 } } */ +/* { dg-final { scan-assembler-times {\tvchlgs} 2 } } */ +/* { dg-final { scan-assembler-times {\tvceqgs} 2 } } */ +/* { dg-final { scan-assembler-times {\tlhi} 2 } } */ +/* { dg-final { scan-assembler-times {\tloc} 4 } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else \ + return 1; \ + } + +TEST(__int128, sint128) +TEST(unsigned __int128, uint128) diff --git a/gcc/testsuite/gcc.target/s390/spaceship-int-3.c b/gcc/testsuite/gcc.target/s390/spaceship-int-3.c new file mode 100644 index 0000000..46b0e4a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/spaceship-int-3.c @@ -0,0 +1,21 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -march=z17 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, -1\)} 1 optimized } } */ +/* { dg-final { scan-tree-dump-times {\.SPACESHIP \([^,]+, [^,]+, 1\)} 1 optimized } } */ +/* { dg-final { scan-assembler-times {\tvecq\t} 1 } } */ +/* { dg-final { scan-assembler-times {\tveclq\t} 1 } } */ +/* { dg-final { scan-assembler-times {\tloc} 4 } } */ + +#define TEST(T, U) \ + int test_##U (T x, T y) \ + { \ + if (x == y) \ + return 0; \ + else if (x < y) \ + return -1; \ + else \ + return 1; \ + } + +TEST(__int128, sint128) +TEST(unsigned __int128, uint128) diff --git a/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c new file mode 100644 index 0000000..11df6c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/vector/vlgv-zero-extend-1.c @@ -0,0 +1,71 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target s390_vx } */ +/* { dg-additional-options "-O2" } */ +/* { dg-final { scan-assembler-not {\tllg?[fhc]r\t} } } */ + +typedef unsigned char __attribute__ ((vector_size (1))) V1QI; +typedef unsigned char __attribute__ ((vector_size (2))) V2QI; +typedef unsigned char __attribute__ ((vector_size (4))) V4QI; +typedef unsigned char __attribute__ ((vector_size (8))) V8QI; +typedef unsigned char __attribute__ ((vector_size (16))) V16QI; + +typedef unsigned short __attribute__ ((vector_size (2))) V1HI; +typedef unsigned short __attribute__ ((vector_size (4))) V2HI; +typedef unsigned short __attribute__ ((vector_size (8))) V4HI; +typedef unsigned short __attribute__ ((vector_size (16))) V8HI; + +typedef unsigned int __attribute__ ((vector_size (4))) V1SI; +typedef unsigned int __attribute__ ((vector_size (8))) V2SI; +typedef unsigned int __attribute__ ((vector_size (16))) V4SI; + +unsigned short ushort; +unsigned int uint; + +#define TEST(T, U, I) \ + unsigned T test_ ## I ## _ ## U (U x) { return x[I]; } \ + void test_ ## I ## _ ## U ## _ushort (U x) { ushort = x[I]; } \ + void test_ ## I ## _ ## U ## _uint (U x) { uint = x[I]; } + +#define TEST1(T, U) \ + TEST(T, U, 0) + +#define TEST2(T, U) \ + TEST1 (T, U) \ + TEST(T, U, 1) + +#define TEST4(T, U) \ + TEST2 (T, U) \ + TEST(T, U, 2) \ + TEST(T, U, 3) + +#define TEST8(T, U) \ + TEST4 (T, U) \ + TEST(T, U, 4) \ + TEST(T, U, 5) \ + TEST(T, U, 6) \ + TEST(T, U, 7) + +#define TEST16(T, U) \ + TEST8 (T, U) \ + TEST(T, U, 9) \ + TEST(T, U, 10) \ + TEST(T, U, 11) \ + TEST(T, U, 12) \ + TEST(T, U, 13) \ + TEST(T, U, 14) \ + TEST(T, U, 15) + +TEST1 (char, V1QI) +TEST2 (char, V2QI) +TEST4 (char, V4QI) +TEST8 (char, V8QI) +TEST16 (char, V16QI) + +TEST1 (short, V1HI) +TEST2 (short, V2HI) +TEST4 (short, V4HI) +TEST8 (short, V8HI) + +TEST1 (int, V1SI) +TEST2 (int, V2SI) +TEST4 (int, V4SI) |