diff options
Diffstat (limited to 'gcc/testsuite/gcc.target/riscv')
1058 files changed, 18333 insertions, 7200 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c new file mode 100644 index 0000000..d3d84fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/amo/zabha-zacas-atomic-cas.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* PR target/120995 ICE unrecognized subword atomic cas */ +/* { dg-options "-O" } */ +/* { dg-add-options riscv_zacas } */ +/* { dg-add-options riscv_zabha } */ + +_Bool b; +void atomic_bool_cmpxchg() +{ + __sync_bool_compare_and_swap(&b, 1, 0); +} diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c index 4cf617d..0dfe816 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c +++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-rvwmo-amo-add-int.c @@ -9,7 +9,7 @@ /* ** atomic_add_fetch_int_relaxed: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -23,7 +23,7 @@ void atomic_add_fetch_int_relaxed (int* bar, int baz) /* ** atomic_add_fetch_int_acquire: -** 1: +**... ** lr.w.aq\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -37,7 +37,7 @@ void atomic_add_fetch_int_acquire (int* bar, int baz) /* ** atomic_add_fetch_int_release: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -51,7 +51,7 @@ void atomic_add_fetch_int_release (int* bar, int baz) /* ** atomic_add_fetch_int_acq_rel: -** 1: +**... ** lr.w.aq\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -65,7 +65,7 @@ void atomic_add_fetch_int_acq_rel (int* bar, int baz) /* ** atomic_add_fetch_int_seq_cst: -** 1: +**... ** lr.w.aqrl\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) diff --git a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c index 3fb16c0..658b040 100644 --- a/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c +++ b/gcc/testsuite/gcc.target/riscv/amo/zalrsc-ztso-amo-add-int.c @@ -9,7 +9,7 @@ /* ** atomic_add_fetch_int_relaxed: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -23,7 +23,7 @@ void atomic_add_fetch_int_relaxed (int* bar, int baz) /* ** atomic_add_fetch_int_acquire: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -37,7 +37,7 @@ void atomic_add_fetch_int_acquire (int* bar, int baz) /* ** atomic_add_fetch_int_release: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -51,7 +51,7 @@ void atomic_add_fetch_int_release (int* bar, int baz) /* ** atomic_add_fetch_int_acq_rel: -** 1: +**... ** lr.w\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) @@ -65,7 +65,7 @@ void atomic_add_fetch_int_acq_rel (int* bar, int baz) /* ** atomic_add_fetch_int_seq_cst: -** 1: +**... ** lr.w.aqrl\t[atx][0-9]+, 0\(a0\) ** add\t[atx][0-9]+, [atx][0-9]+, a1 ** sc.w.rl\t[atx][0-9]+, [atx][0-9]+, 0\(a0\) diff --git a/gcc/testsuite/gcc.target/riscv/arch-25.c b/gcc/testsuite/gcc.target/riscv/arch-25.c index 3be4ade..9201883 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-25.c +++ b/gcc/testsuite/gcc.target/riscv/arch-25.c @@ -2,4 +2,4 @@ /* { dg-options "-march=rv64i_zcf -mabi=lp64" } */ int foo() {} /* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64ic_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-45.c b/gcc/testsuite/gcc.target/riscv/arch-45.c new file mode 100644 index 0000000..afffb99 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-45.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_svadu -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-46.c b/gcc/testsuite/gcc.target/riscv/arch-46.c new file mode 100644 index 0000000..2a06217 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-46.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_svade -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-47.c b/gcc/testsuite/gcc.target/riscv/arch-47.c new file mode 100644 index 0000000..06bc80f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-47.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_sdtrig_ssstrict -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-48.c b/gcc/testsuite/gcc.target/riscv/arch-48.c new file mode 100644 index 0000000..58a558e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-48.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zama16b -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-49.c b/gcc/testsuite/gcc.target/riscv/arch-49.c new file mode 100644 index 0000000..6b86ae9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-49.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rvi20u64 -mabi=lp64" } */ +int +foo () +{} diff --git a/gcc/testsuite/gcc.target/riscv/arch-50.c b/gcc/testsuite/gcc.target/riscv/arch-50.c new file mode 100644 index 0000000..072180d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-50.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rvi20u64_mafdc -mabi=lp64d" } */ +#if !(defined __riscv_mul) || \ + !(defined __riscv_atomic) || \ + !(defined __riscv_flen) || \ + !(defined __riscv_div) || \ + !(defined __riscv_compressed) +#error "Feature macros not defined" +#endif +int +foo () +{} diff --git a/gcc/testsuite/gcc.target/riscv/arch-51.c b/gcc/testsuite/gcc.target/riscv/arch-51.c new file mode 100644 index 0000000..5af983c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-51.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rva20u64 -mabi=lp64d" } */ +#if !(defined __riscv_mul) || \ + !(defined __riscv_atomic) || \ + !(defined __riscv_flen) || \ + !(defined __riscv_div) || \ + !(defined __riscv_compressed) +#error "Feature macros not defined" +#endif +int +foo () +{} diff --git a/gcc/testsuite/gcc.target/riscv/arch-52.c b/gcc/testsuite/gcc.target/riscv/arch-52.c new file mode 100644 index 0000000..6133370 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-52.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rva22u64v -mabi=lp64" } */ +/* { dg-warning "Should use \"_\" to contact Profiles with other extensions" "" { target *-*-* } 0 } */ +int +foo () +{} diff --git a/gcc/testsuite/gcc.target/riscv/arch-53.c b/gcc/testsuite/gcc.target/riscv/arch-53.c new file mode 100644 index 0000000..43ab23a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-53.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rva23u64 -mabi=lp64d" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0" +_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0" +_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" +_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0" +_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-54.c b/gcc/testsuite/gcc.target/riscv/arch-54.c new file mode 100644 index 0000000..6d242df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-54.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rvb23u64 -mabi=lp64d" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0" +"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0" +"_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0" +"_zbb1p0_zbs1p0_zkt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-55.c b/gcc/testsuite/gcc.target/riscv/arch-55.c new file mode 100644 index 0000000..0e8a294 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-55.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g_sha -mabi=lp64d" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2" +"_d2p2_h1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_sha1p0" +"_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0" +"_ssstateen1p0\"" } } */
\ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/arch-56.c b/gcc/testsuite/gcc.target/riscv/arch-56.c new file mode 100644 index 0000000..e075f96 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-56.c @@ -0,0 +1,13 @@ +/* Check whether the second -march overrides the first. */ +/* { dg-do compile { target rv64 } } */ +/* { dg-options "-O3 -march=rv64gc -march=sifive-p670" } */ + +void +foo (char *a, char *b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = b[i] + 1; +} + +/* { dg-final { scan-assembler "vset" } } */ +/* { dg-final { scan-assembler "zvl128b" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-57.c b/gcc/testsuite/gcc.target/riscv/arch-57.c new file mode 100644 index 0000000..08d3761 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-57.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_smdbltrp -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicsr2p0_smdbltrp1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-58.c b/gcc/testsuite/gcc.target/riscv/arch-58.c new file mode 100644 index 0000000..1481da5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-58.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_ssdbltrp -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicsr2p0_ssdbltrp1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-59.c b/gcc/testsuite/gcc.target/riscv/arch-59.c new file mode 100644 index 0000000..511cf22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-59.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_smcntrpmf -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-60.c b/gcc/testsuite/gcc.target/riscv/arch-60.c new file mode 100644 index 0000000..ea599f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-60.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_svbare -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-rva23s.c b/gcc/testsuite/gcc.target/riscv/arch-rva23s.c new file mode 100644 index 0000000..215249d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-rva23s.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rva23s64 -mabi=lp64d" } */ + +void foo(){} + +/* { dg-final { scan-assembler-times ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +"_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0" +"_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0" +"_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" +"_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0" +"_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_sha1p0_shcounterenw1p0" +"_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0" +"_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_supm1p0" +"_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0\" 1} } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-rvb23s.c b/gcc/testsuite/gcc.target/riscv/arch-rvb23s.c new file mode 100644 index 0000000..aa71f7d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-rvb23s.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rvb23s64 -mabi=lp64d" } */ + +void foo(){} + +/* { dg-final { scan-assembler-times ".attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0" +"_b1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0" +"_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0" +"_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0" +"_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0" +"_zvl32b1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0" +"_ssu64xl1p0_supm1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0\" 1} } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-shlocofideleg.c b/gcc/testsuite/gcc.target/riscv/arch-shlocofideleg.c new file mode 100644 index 0000000..de9f9fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-shlocofideleg.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_shlcofideleg -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-smcsrind.c b/gcc/testsuite/gcc.target/riscv/arch-smcsrind.c new file mode 100644 index 0000000..4d1c104 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-smcsrind.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_smcsrind -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-smrnmi.c b/gcc/testsuite/gcc.target/riscv/arch-smrnmi.c new file mode 100644 index 0000000..8e62540 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-smrnmi.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_smrnmi -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-ss-1.c b/gcc/testsuite/gcc.target/riscv/arch-ss-1.c new file mode 100644 index 0000000..8f95737 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-ss-1.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_ssnpm_smnpm_smmpm_sspm_supm -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-ss-2.c b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c new file mode 100644 index 0000000..f1d7724 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-ss-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm -mabi=ilp32d" } */ +int foo() +{ +} +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32gc_ssnpm_smnpm_smmpm_sspm_supm': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': ssnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': smnpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': smmpm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': sspm extension supports in rv64 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv32imafdc_zicsr_zifencei_zmmul_zaamo_zalrsc_zca_zcd_zcf_smmpm_smnpm_ssnpm_sspm_supm': supm extension supports in rv64 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-ssccptr.c b/gcc/testsuite/gcc.target/riscv/arch-ssccptr.c new file mode 100644 index 0000000..902155a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-ssccptr.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_ssccptr -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c b/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c new file mode 100644 index 0000000..901b6bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-sscounterenw.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_sscounterenw -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-sstvala.c b/gcc/testsuite/gcc.target/riscv/arch-sstvala.c new file mode 100644 index 0000000..21ea8a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-sstvala.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_sstvala -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-sstvecd.c b/gcc/testsuite/gcc.target/riscv/arch-sstvecd.c new file mode 100644 index 0000000..e76f7881 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-sstvecd.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_sstvecd -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c b/gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c new file mode 100644 index 0000000..6e151c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-ssu64xl.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i_ssu64xl -mabi=lp64" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-1.c b/gcc/testsuite/gcc.target/riscv/arch-unset-1.c new file mode 100644 index 0000000..971b936 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-1.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-2.c b/gcc/testsuite/gcc.target/riscv/arch-unset-2.c new file mode 100644 index 0000000..9840658 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -march=rv64i -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-3.c b/gcc/testsuite/gcc.target/riscv/arch-unset-3.c new file mode 100644 index 0000000..5ddc224 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-3.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -march=rv64i -march=unset -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zfh1p0_zfhmin1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfh1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl512b1p0_zvl64b1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-4.c b/gcc/testsuite/gcc.target/riscv/arch-unset-4.c new file mode 100644 index 0000000..c16821d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-4.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mcpu=sifive-x280 -march=unset -march=rv64i -march=unset -march=rv64i -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-final { scan-assembler "\.attribute arch, \"rv64i2p1\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-unset-5.c b/gcc/testsuite/gcc.target/riscv/arch-unset-5.c new file mode 100644 index 0000000..368c129 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-unset-5.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64i -march=unset -mabi=lp64 -misa-spec=20191213" } */ +int foo() +{ +} + +/* { dg-error "At least one valid -mcpu option must be given after -march=unset" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-1.c b/gcc/testsuite/gcc.target/riscv/arch-zilsd-1.c new file mode 100644 index 0000000..452c04e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-1.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zilsd_zclsd -mabi=ilp32d" } */ +int foo() +{ +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c b/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c new file mode 100644 index 0000000..5d6185d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-2.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zilsd -mabi=ilp32d" } */ +int foo() +{ +} +/* { dg-error "'-march=rv64gc_zilsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c b/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c new file mode 100644 index 0000000..3cda120 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/arch-zilsd-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zclsd -mabi=ilp32d" } */ +int foo() +{ +} +/* { dg-error "'-march=rv64gc_zclsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64gc_zclsd': zclsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd_zclsd': zilsd extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64imafdc_zicsr_zifencei_zilsd_zmmul_zaamo_zalrsc_zca_zcd_zclsd': zclsd extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-1.c b/gcc/testsuite/gcc.target/riscv/attribute-c-1.c new file mode 100644 index 0000000..5627e16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32i_zca -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_c2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-2.c b/gcc/testsuite/gcc.target/riscv/attribute-c-2.c new file mode 100644 index 0000000..4c7d5f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32if_zca -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_zicsr2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-3.c b/gcc/testsuite/gcc.target/riscv/attribute-c-3.c new file mode 100644 index 0000000..7ff68f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32if_zca_zcf -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-4.c b/gcc/testsuite/gcc.target/riscv/attribute-c-4.c new file mode 100644 index 0000000..ef59b65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32ifd_zca_zcf -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-5.c b/gcc/testsuite/gcc.target/riscv/attribute-c-5.c new file mode 100644 index 0000000..14e9551 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32ifd_zca_zcf_zcd -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-6.c b/gcc/testsuite/gcc.target/riscv/attribute-c-6.c new file mode 100644 index 0000000..30cda55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-6.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64i_zca -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_c2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-7.c b/gcc/testsuite/gcc.target/riscv/attribute-c-7.c new file mode 100644 index 0000000..b06388b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-7.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64ifd_zca -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_d2p2_zicsr2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-8.c b/gcc/testsuite/gcc.target/riscv/attribute-c-8.c new file mode 100644 index 0000000..fa76050 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-8.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64ifd_zca_zcd -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c index e477414..fc86dbe 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c index 7008eb5..4504158 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c index 89ebaaf..4ffc051 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c index cacbcaa..7ee8de2 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c new file mode 100644 index 0000000..479246b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/constraint-cR-pair.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +void foo(int a0, int a1, int a2, int a3, int a4, int a5, int a6, int a7, int m0, int m1) { +/* +** foo: +** ... +** addi\s*t0,\s*(a[024]|s0),\s*(a[024]|s0) +** ... +*/ + __asm__ volatile("addi t0, %0, %0" : : "cR" (m0) : "memory"); +} diff --git a/gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c b/gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c index 4a8477e..3d46306 100644 --- a/gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c +++ b/gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c @@ -1,5 +1,5 @@ /* { dg-do compile { target { ! riscv_abi_e } } } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ /* { dg-options "-march=rv32gc -mtune=sifive-7-series -mbranch-cost=1 -fno-ssa-phiopt -fdump-rtl-ce1" { target { rv32 } } } */ /* { dg-options "-march=rv64gc -mtune=sifive-7-series -mbranch-cost=1 -fno-ssa-phiopt -fdump-rtl-ce1" { target { rv64 } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c b/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c index 81ebf5f..15cc3ee 100644 --- a/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c +++ b/gcc/testsuite/gcc.target/riscv/interrupt-conflict-mode.c @@ -1,7 +1,7 @@ /* Verify proper errors are generated for conflicted interrupt type. */ /* { dg-do compile } */ /* { dg-options "" } */ -void __attribute__ ((interrupt ("user"))) +void __attribute__ ((interrupt ("supervisor"))) foo(void); void __attribute__ ((interrupt ("machine"))) diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-rnmi.c b/gcc/testsuite/gcc.target/riscv/interrupt-rnmi.c new file mode 100644 index 0000000..f340108 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/interrupt-rnmi.c @@ -0,0 +1,11 @@ +/* Verify the return instruction is mnret. */ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_smrnmi" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_smrnmi" { target { rv64 } } } */ + +void __attribute__ ((interrupt ("rnmi"))) +foo (void) +{ +} + +/* { dg-final { scan-assembler {\mmnret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-umode.c b/gcc/testsuite/gcc.target/riscv/interrupt-umode.c deleted file mode 100644 index 042abf0..0000000 --- a/gcc/testsuite/gcc.target/riscv/interrupt-umode.c +++ /dev/null @@ -1,8 +0,0 @@ -/* Verify the return instruction is mret. */ -/* { dg-do compile } */ -/* { dg-options "" } */ -void __attribute__ ((interrupt ("user"))) -foo (void) -{ -} -/* { dg-final { scan-assembler {\muret} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/ior-synthesis-1.c b/gcc/testsuite/gcc.target/riscv/ior-synthesis-1.c new file mode 100644 index 0000000..04644cd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/ior-synthesis-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gb -mabi=lp64d" } */ + +unsigned long foo(unsigned long src) { return src | 0x8c00000000000001; } + +/* { dg-final { scan-assembler-times "\\srori\t" 2 } } */ +/* { dg-final { scan-assembler-times "\\sori\t" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/ior-synthesis-2.c b/gcc/testsuite/gcc.target/riscv/ior-synthesis-2.c new file mode 100644 index 0000000..f28fe5e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/ior-synthesis-2.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gb -mabi=lp64d" } */ + +unsigned long foo(unsigned long src) { return src | 0x8800000000000007; } + +/* { dg-final { scan-assembler-times "\\sbseti\t" 2 } } */ +/* { dg-final { scan-assembler-times "\\sori\t" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c b/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c index 1ee7f6c..ab97b0f 100644 --- a/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c +++ b/gcc/testsuite/gcc.target/riscv/jump-table-large-code-model.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=large" } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -mcmodel=large -fno-pie" } */ int foo(int x, int y) { diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-kunminghu.c b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-kunminghu.c new file mode 100644 index 0000000..e3ae65c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xiangshan-kunminghu.c @@ -0,0 +1,95 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=xiangshan-kunminghu" } */ +/* XiangShan Kunminghu => rv64imafdcbvh_sdtrig_sha_shcounterenw_shgatpa + _shlcofideleg_shtvala_shvsatpa_shvstvala_shvstvecd + _smaia_smcsrind_smdbltrp_smmpm_smnpm_smrnmi_smstateen + _ssaia_ssccptr_sscofpmf_sscounterenw_sscsrind_ssdbltrp + _ssnpm_sspm_ssstateen_ssstrict_sstc_sstvala_sstvecd + _ssu64xl_supm_svade_svbare_svinval_svnapot_svpbmt + _za64rs_zacas_zawrs_zba_zbb_zbc_zbkb_zbkc_zbkx_zbs_zcb + _zcmop_zfa_zfh_zfhmin_zic64b_zicbom_zicbop_zicboz_ziccif + _zicclsm_ziccrse_zicntr_zicond_zicsr_zifencei_zihintpause + _zihpm_zimop_zkn_zknd_zkne_zknh_zksed_zksh_zkt_zvbb + _zvfh_zvfhmin_zvkt_zvl128b_zvl32b_zvl64b */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_v) \ + && defined(__riscv_zic64b) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_ziccif) \ + && defined(__riscv_zicclsm) \ + && defined(__riscv_ziccrse) \ + && defined(__riscv_zicntr) \ + && defined(__riscv_zicond) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zimop) \ + && defined(__riscv_za64rs) \ + && defined(__riscv_zacas) \ + && defined(__riscv_zawrs) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbc) \ + && defined(__riscv_zbs) \ + && defined(__riscv_zbkb) \ + && defined(__riscv_zbkc) \ + && defined(__riscv_zbkx) \ + && defined(__riscv_zcb) \ + && defined(__riscv_zcmop) \ + && defined(__riscv_zfa) \ + && defined(__riscv_zfh) \ + && defined(__riscv_zknd) \ + && defined(__riscv_zkne) \ + && defined(__riscv_zknh) \ + && defined(__riscv_zksed) \ + && defined(__riscv_zksh) \ + && defined(__riscv_zkt) \ + && defined(__riscv_zvbb) \ + && defined(__riscv_zvfh) \ + && defined(__riscv_zvkt) \ + && defined(__riscv_sdtrig) \ + && defined(__riscv_sha) \ + && defined(__riscv_shlcofideleg) \ + && defined(__riscv_smaia) \ + && defined(__riscv_smcsrind) \ + && defined(__riscv_smdbltrp) \ + && defined(__riscv_smmpm) \ + && defined(__riscv_smnpm) \ + && defined(__riscv_smrnmi) \ + && defined(__riscv_smstateen) \ + && defined(__riscv_ssaia) \ + && defined(__riscv_ssccptr) \ + && defined(__riscv_sscofpmf) \ + && defined(__riscv_sscounterenw) \ + && defined(__riscv_sscsrind) \ + && defined(__riscv_ssdbltrp) \ + && defined(__riscv_ssnpm) \ + && defined(__riscv_sspm) \ + && defined(__riscv_ssstrict) \ + && defined(__riscv_sstc) \ + && defined(__riscv_sstvala) \ + && defined(__riscv_sstvecd) \ + && defined(__riscv_ssu64xl) \ + && defined(__riscv_supm) \ + && defined(__riscv_svade) \ + && defined(__riscv_svbare) \ + && defined(__riscv_svinval) \ + && defined(__riscv_svnapot) \ + && defined(__riscv_svpbmt)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c index cb28baf..4ad82a8 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c908" { target { rv64 } } } */ /* XuanTie C908 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c index 1b1ee18..bb9e310 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c908v.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c908v" { target { rv64 } } } */ /* XuanTie C908v => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c index 1e27665..397e7b1 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c910" { target { rv64 } } } */ /* XuanTie C910 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_xtheadba_ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c index 6a54f09..9e39c9f 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c910v2.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c910v2" { target { rv64 } } } */ /* XuanTie C910v2 => rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c index 6bcd687..4cce90a 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c920" { target { rv64 } } } */ /* XuanTie c920 => rv64imafdc_zicntr_zicsr_zifencei_zihpm_zfh_"xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadmac_xtheadmemidx_xtheadmempair_xtheadsync_xtheadvector */ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c index 36a6267..1f21d07 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-xt-c920v2.c @@ -1,4 +1,4 @@ -/* { dg-do compile } */ +/* { dg-do compile { target { ! riscv_abi_e } } } */ /* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ /* { dg-options "-mcpu=xt-c920v2" { target { rv64 } } } */ /* XuanTie C920v2 => rv64imafdcv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zifencei _zihintntl_zihintpause_zihpm_zawrs_zfa_zfbfmin_zfh_zca_zcb_zcd_zba_zbb_zbc_zbs_zvfbfmin_zvfbfwma_zvfh_sscofpmf_sstc_svinval_svnapot_svpbmt_xtheadba_xtheadbb_xtheadbs_xtheadcmo_xtheadcondmov_xtheadfmemidx_xtheadsync_xtheadvdot */ diff --git a/gcc/testsuite/gcc.target/riscv/mipscondmov.c b/gcc/testsuite/gcc.target/riscv/mipscondmov.c new file mode 100644 index 0000000..5485133 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mipscondmov.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32imafd_xmipscmov" { target { rv32 } } } */ +/* { dg-options "-march=rv64imafd_xmipscmov -mabi=lp64d" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +#define MYTEST(name, mytype) \ +mytype test1_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a == b) ? c : d; } \ +mytype test2_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a != b) ? c : d; } \ +mytype test3_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a > b) ? c : d; } \ +mytype test4_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a >= b) ? c : d; } \ +mytype test5_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a < b) ? c : d; } \ +mytype test6_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a <= b) ? c : d; } \ +mytype test7_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a == 1) ? c : d; } \ +mytype test8_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a != 1) ? c : d; } \ +mytype test9_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a > 1) ? c : d; } \ +mytype test10_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a >= 1) ? c : d; } \ +mytype test11_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a < 1) ? c : d; } \ +mytype test12_ ## name (mytype a, mytype b, mytype c, mytype d) { return (a <= 1) ? c : d; } + +MYTEST(1, long) +MYTEST(2, unsigned long) +MYTEST(3, int) +MYTEST(4, unsigned int) +MYTEST(5, short) +MYTEST(6, unsigned short) +MYTEST(7, signed char) +MYTEST(8, unsigned char) + +/* { dg-final { scan-assembler-times "mips.ccmov" 96 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/modifier-H-error-1.c b/gcc/testsuite/gcc.target/riscv/modifier-H-error-1.c new file mode 100644 index 0000000..43ecff6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/modifier-H-error-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -O0" } */ + +float foo () +{ + float ret; + asm ("fld\t%H0,(a0)\n\t":"=f"(ret)); + + return ret; +} + +/* { dg-error "modifier 'H' is for integer registers only" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/modifier-H-error-2.c b/gcc/testsuite/gcc.target/riscv/modifier-H-error-2.c new file mode 100644 index 0000000..db478b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/modifier-H-error-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -O0 " } */ + +void foo () +{ + register int x31 __asm__ ("x31"); + asm ("li\t%H0,1\n\t":"=r"(x31)); +} + +/* { dg-error "modifier 'H' cannot be applied to R31" "" { target { "riscv*-*-*" } } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/modifier-H.c b/gcc/testsuite/gcc.target/riscv/modifier-H.c new file mode 100644 index 0000000..3571ea9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/modifier-H.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-flto" } { "" } } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -O0" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +typedef long long __int64; + +__int64 foo () +{ +/* +** foo: +** ... +** li\t[atx][0-9]+,1 +** li\t[atx][0-9]+,1 +** ... +*/ + __int64 ret; + asm ("li\t%0,1\n\tli\t%H0,1\n\t":"=r"(ret)); + + return ret; +} + diff --git a/gcc/testsuite/gcc.target/riscv/nozicond-1.c b/gcc/testsuite/gcc.target/riscv/nozicond-1.c new file mode 100644 index 0000000..35ab6fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/nozicond-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-additional-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ + + +long foo1 (long c) { return c >= 0 ? 1 : -1; } +long foo2 (long c) { return c < 0 ? -1 : 1; } + +/* { dg-final { scan-assembler-times {srai\t} 2 } } */ +/* { dg-final { scan-assembler-times {ori\t} 2 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/nozicond-2.c b/gcc/testsuite/gcc.target/riscv/nozicond-2.c new file mode 100644 index 0000000..f705253 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/nozicond-2.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-additional-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ + + +long foo1 (long c) { return c < 0 ? 1 : -1; } +long foo2 (long c) { return c >= 0 ? -1 : 1; } + +/* We don't support 4->3 splitters, so this fails. We could perhaps + try to catch it in the expander as a special case rather than waiting + for combine. */ +/* { dg-final { scan-assembler-times {srai\t} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {ori\t} 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {not\t} 2 { xfail *-*-* } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/nozicond-3.c b/gcc/testsuite/gcc.target/riscv/nozicond-3.c new file mode 100644 index 0000000..5116742 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/nozicond-3.c @@ -0,0 +1,11 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-additional-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" } } */ + +long foo1 (long n) { return n / 4096; } + +/* { dg-final { scan-assembler-times {srai\t} 2 } } */ +/* { dg-final { scan-assembler-times {srli\t} 1 } } */ +/* { dg-final { scan-assembler-times {add\t} 1 } } */ +/* { dg-final { scan-assembler-not {czero} } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr114512.c b/gcc/testsuite/gcc.target/riscv/pr114512.c new file mode 100644 index 0000000..70146f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr114512.c @@ -0,0 +1,79 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcb -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gcb -mabi=ilp32" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +/* We need to adjust the constant so this works for rv32 and rv64. */ +#if __riscv_xlen == 32 +#define ONE 1U +#define MASK 0x1f +typedef unsigned int utype; +#else +#define ONE 1ULL +#define MASK 0x3f +typedef unsigned long utype; +#endif + + +_Bool my_isxdigit_1(unsigned char ch) { + utype mask1 = 0x03FF007E; + if (!((mask1 >> (ch & MASK)) & 1)) + return 0; + + return 1; +} + +_Bool my_isxdigit_1a(unsigned char ch) { + utype mask2 = 0x58; + if (!((mask2 >> (ch >> 4)) & 1)) + return 0; + + return 1; +} + +_Bool my_isxdigit_2(unsigned char ch) { + utype mask1 = 0x03FF007E; + if (!(mask1 & (ONE << (ch & MASK)))) + return 0; + + return 1; +} + +_Bool my_isxdigit_2a(unsigned char ch) { + utype mask2 = 0x58; + if (!(mask2 & (ONE << (ch >> 4)))) + return 0; + + return 1; +} + +_Bool my_isxdigit_1_parm(unsigned char ch, utype mask1) { + if (!((mask1 >> (ch & MASK)) & 1)) + return 0; + + return 1; +} + +_Bool my_isxdigit_1a_parm(unsigned char ch, utype mask2) { + if (!((mask2 >> (ch >> 4)) & 1)) + return 0; + + return 1; +} + +_Bool my_isxdigit_2_parm(unsigned char ch, utype mask1) { + if (!(mask1 & (ONE << (ch & MASK)))) + return 0; + + return 1; +} + +_Bool my_isxdigit_2a_parm(unsigned char ch, utype mask2) { + if (!(mask2 & (ONE << (ch >> 4)))) + return 0; + + return 1; +} + +/* Each test should generate a single bext. */ +/* { dg-final { scan-assembler-times "bext\t" 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr118241-b.cc b/gcc/testsuite/gcc.target/riscv/pr118241-b.cc new file mode 100644 index 0000000..b2cc73f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr118241-b.cc @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64imafdc_zba_zbb_zbs_zicbom_zicbop -mabi=lp64d" } */ + +/* Reduced from libsanitizer::asan_allocator. */ + +enum a { c }; +class d; +struct e { + long count; + void *batch[]; +}; +template <typename> class f { +public: + void g() { + if (e *b = h->i()) + for (; b->count;) + if (6 < b->count) + __builtin_prefetch(b->batch[6]); + } + d *h; +}; +class d { +public: + e *i(); +}; +struct j { + f<int> k; + j(a); + void l() { k.g(); } +} a(c); +void m() { a.l(); } + +/* { dg-final { scan-assembler-times "prefetch.r\t0\\(\[a-x0-9\]+\\)" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/pr118241.c b/gcc/testsuite/gcc.target/riscv/pr118241.c new file mode 100644 index 0000000..768ea05 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr118241.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! riscv_abi_e } } } */ +/* { dg-options "-march=rv64gc_zicbop" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicbop" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +void test1() { __builtin_prefetch((int *)2047); } +void test2() { __builtin_prefetch((int *)1024); } +void test3(char *x) { __builtin_prefetch(&x); } +void test4(char *x) { __builtin_prefetch(&x[2]); } +void test5(char *x) { __builtin_prefetch(&x[1024]); } + +/* So we expect test1, test3 and test4 to be a prefetch + with zero offset. test2 and test5 will have a 1k offset. */ +/* { dg-final { scan-assembler-times "prefetch.r\t0\\(\[a-x0-9\]+\\)" 3 } } */ +/* { dg-final { scan-assembler-times "prefetch.r\t1024" 2 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/pr119830.c b/gcc/testsuite/gcc.target/riscv/pr119830.c new file mode 100644 index 0000000..8c7cf3b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr119830.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb_zbs -mabi=lp64d" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zbb_zbs -mabi=ilp32" { target { rv32 } } } */ + +#include <stdint.h> +void test(int32_t N, int16_t* A, int16_t val) { + int32_t i, j; + for (i = 0; i < N; i++) { + for (j = 0; j < N; j++) { + A[i * N + j] += val; + } + } +} diff --git a/gcc/testsuite/gcc.target/riscv/pr119971.c b/gcc/testsuite/gcc.target/riscv/pr119971.c new file mode 100644 index 0000000..0d73d4c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr119971.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target rv64 } } */ +/* { dg-options "-march=rv64gcb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Oz" "-Os" } } */ + +__attribute__ ((noipa)) unsigned +foo (unsigned b, unsigned e, unsigned i) +{ + e >>= b; + i >>= e & 31; + return i & 1; +} + +int main() +{ + if (foo (0x18, 0xfe000000, 0x40000000) != 1) + __builtin_abort (); + return 0; +} + +/* { dg-final { scan-assembler-times "andi\t" 1 } } */ +/* { dg-final { scan-assembler-times "srlw\t" 2 } } */ +/* { dg-final { scan-assembler-not "bext\t" } } */ + + diff --git a/gcc/testsuite/gcc.target/riscv/pr120137.c b/gcc/testsuite/gcc.target/riscv/pr120137.c new file mode 100644 index 0000000..c55a1c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120137.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mrvv-vector-bits=zvl -mabi=lp64" } */ + +char b[13][13]; +void c() { + for (int d = 0; d < 13; ++d) + for (int e = 0; e < 13; ++e) + b[d][e] = e == 0 ? -98 : 38; +} + + + diff --git a/gcc/testsuite/gcc.target/riscv/pr120154.c b/gcc/testsuite/gcc.target/riscv/pr120154.c new file mode 100644 index 0000000..fd849ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120154.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gv -mabi=lp64" } */ + + + +typedef __attribute__((__vector_size__(4))) char V; + +V g; + +V +bar(V a, V b) +{ + V s = a + b + g; + return s; +} + +V +foo() +{ + return bar((V){20}, (V){23, 150}); +} + diff --git a/gcc/testsuite/gcc.target/riscv/pr120223.c b/gcc/testsuite/gcc.target/riscv/pr120223.c new file mode 100644 index 0000000..d6afd86 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120223.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target { ! riscv_abi_e } } } */ +/* { dg-options "-mcpu=thead-c906" } */ +long foo(long x) { return x ^ 0x80000000; } + diff --git a/gcc/testsuite/gcc.target/riscv/pr120333.c b/gcc/testsuite/gcc.target/riscv/pr120333.c new file mode 100644 index 0000000..17b376f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120333.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-march=rv64gcb -std=gnu23" } */ + +__attribute__ ((noipa)) _Bool +foo (unsigned char ch, unsigned long mask) { + return (mask << (0x3f - (ch & 0x3f))) >> 0x3f; +} + +int main() +{ + if (!foo (0x3f, 0x8000000000000000ul)) + __builtin_abort (); + return 0; +} + diff --git a/gcc/testsuite/gcc.target/riscv/pr120368.c b/gcc/testsuite/gcc.target/riscv/pr120368.c new file mode 100644 index 0000000..4fea8e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120368.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ + +int g; + +int +foo (int s, int v) +{ + __builtin_memset (&g, v >> (s & 31), sizeof(g)); + return g; +} + +int +main () +{ + int x = foo (-16, 0xdffff); + if (x != 0x0d0d0d0d) + __builtin_abort(); + __builtin_exit (0); +} diff --git a/gcc/testsuite/gcc.target/riscv/pr120659.c b/gcc/testsuite/gcc.target/riscv/pr120659.c new file mode 100644 index 0000000..91e6e42 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120659.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=sifive-x280 -mabi=lp64" } */ + +_Float16 f; +void foo() { f /= 3; } diff --git a/gcc/testsuite/gcc.target/riscv/pr120714.c b/gcc/testsuite/gcc.target/riscv/pr120714.c new file mode 100644 index 0000000..dd71a3e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr120714.c @@ -0,0 +1,40 @@ +/* Test checking that the backtrace on large frame size with additional + SP shift in the prologue won't broken when compiled with the + -fstack-clash-protection option. */ +/* { dg-do run { target { *-*-linux* } } } */ +/* -O0 does not have enough optimizations. + -O2/-O3 does inline and reduces number of addresses in the backtrace. */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O2" "-O3" } } */ +/* { dg-options "-g -fstack-clash-protection" } */ + +#include <execinfo.h> + +#define MAX 4000 + +void goo () +{ + int addresses; + void *buffer[10]; + + addresses = backtrace (buffer, 10); + if (addresses != 6) + __builtin_abort (); +} + +int foo (int a) +{ + long long A[MAX]; + for (int i = 0; i < MAX; i++) + A[i] = i; + + goo (); + + return A[a % MAX]; +} + +int main () +{ + if (foo (20) != 20) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/predef-19.c b/gcc/testsuite/gcc.target/riscv/predef-19.c index 2b90702..f2b4d9b 100644 --- a/gcc/testsuite/gcc.target/riscv/predef-19.c +++ b/gcc/testsuite/gcc.target/riscv/predef-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O2 -march=rv64gc_zve32x -mabi=lp64d -mcmodel=medlow -misa-spec=2.2" } */ +/* { dg-options "-O2 -march=rv64im_zve32x -mabi=lp64 -mcmodel=medlow -misa-spec=2.2" } */ int main () { @@ -15,50 +15,26 @@ int main () { #error "__riscv_i" #endif -#if !defined(__riscv_c) -#error "__riscv_c" -#endif - #if defined(__riscv_e) #error "__riscv_e" #endif -#if !defined(__riscv_a) -#error "__riscv_a" -#endif - #if !defined(__riscv_m) #error "__riscv_m" #endif -#if !defined(__riscv_f) -#error "__riscv_f" -#endif - -#if !defined(__riscv_d) -#error "__riscv_d" -#endif - -#if defined(__riscv_v) -#error "__riscv_v" +#if !defined(__riscv_zicsr) +#error "__riscv_zicsr" #endif -#if defined(__riscv_zvl128b) -#error "__riscv_zvl128b" -#endif - -#if defined(__riscv_zvl64b) -#error "__riscv_zvl64b" +#if !defined(__riscv_zve32x) +#error "__riscv_zve32x" #endif #if !defined(__riscv_zvl32b) #error "__riscv_zvl32b" #endif -#if !defined(__riscv_zve32x) -#error "__riscv_zve32x" -#endif - #if !defined(__riscv_vector) #error "__riscv_vector" #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h new file mode 100644 index 0000000..2de7d7c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg.h @@ -0,0 +1,45 @@ +#ifndef HAVE_DEFINED_AVG_H +#define HAVE_DEFINED_AVG_H + +#include <stdint.h> + +#if __riscv_xlen == 64 +typedef unsigned __int128 uint128_t; +typedef signed __int128 int128_t; +#endif + +#define DEF_AVG_0(NT, WT, NAME) \ +__attribute__((noinline)) \ +void \ +test_##NAME##_##WT##_##NT##_0(NT * restrict a, NT * restrict b, \ + NT * restrict out, int n) \ +{ \ + for (int i = 0; i < n; i++) { \ + out[i] = (NT)(((WT)a[i] + (WT)b[i]) >> 1); \ + } \ +} +#define DEF_AVG_0_WRAP(NT, WT, NAME) DEF_AVG_0(NT, WT, NAME) + +#define RUN_AVG_0(NT, WT, NAME, a, b, out, n) \ + test_##NAME##_##WT##_##NT##_0(a, b, out, n) +#define RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) \ + RUN_AVG_0(NT, WT, NAME, a, b, out, n) + +#define DEF_AVG_1(NT, WT, NAME) \ +__attribute__((noinline)) \ +void \ +test_##NAME##_##WT##_##NT##_1(NT * restrict a, NT * restrict b, \ + NT * restrict out, int n) \ +{ \ + for (int i = 0; i < n; i++) { \ + out[i] = (NT)(((WT)a[i] + (WT)b[i] + 1) >> 1); \ + } \ +} +#define DEF_AVG_1_WRAP(NT, WT, NAME) DEF_AVG_1(NT, WT, NAME) + +#define RUN_AVG_1(NT, WT, NAME, a, b, out, n) \ + test_##NAME##_##WT##_##NT##_1(a, b, out, n) +#define RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) \ + RUN_AVG_1(NT, WT, NAME, a, b, out, n) + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c new file mode 100644 index 0000000..31d3b43 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int16_t +#define WT int32_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c new file mode 100644 index 0000000..7f30b9e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i16-from-i64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int16_t +#define WT int64_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c new file mode 100644 index 0000000..2e06d0a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i32-from-i64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int32_t +#define WT int64_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c new file mode 100644 index 0000000..ca23066 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i64-from-i128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int64_t +#define WT int128_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c new file mode 100644 index 0000000..dda84a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i16.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int8_t +#define WT int16_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c new file mode 100644 index 0000000..dfd2bb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int8_t +#define WT int32_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c new file mode 100644 index 0000000..d1060cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-1-i8-from-i64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int8_t +#define WT int64_t + +DEF_AVG_1_WRAP(NT, WT, avg_ceil) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c new file mode 100644 index 0000000..3d872a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int32_t +#define NT int16_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c new file mode 100644 index 0000000..eda9736 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i16-from-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int64_t +#define NT int16_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c new file mode 100644 index 0000000..21cbb94 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i32-from-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int64_t +#define NT int32_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c new file mode 100644 index 0000000..ee5330c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i64-from-i128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int128_t +#define NT int64_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c new file mode 100644 index 0000000..fd91b6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int16_t +#define NT int8_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c new file mode 100644 index 0000000..38f4920 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int32_t +#define NT int8_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c new file mode 100644 index 0000000..f65ee15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_ceil-run-1-i8-from-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int64_t +#define NT int8_t +#define NAME avg_ceil + +DEF_AVG_1_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_1_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h new file mode 100644 index 0000000..49103f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_data.h @@ -0,0 +1,361 @@ +#ifndef HAVE_DEFINED_AVG_DATA_H +#define HAVE_DEFINED_AVG_DATA_H + +#define N 16 + +#define TEST_AVG_DATA(T, NAME) test_##T##_##NAME##_data +#define TEST_AVG_DATA_WRAP(T, NAME) TEST_AVG_DATA(T, NAME) + +int8_t TEST_AVG_DATA(int8_t, avg_floor)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 4, 4, 4, 4, + }, + }, + { + { + 127, 127, 127, 127, + 127, 127, 127, 127, + -128, -128, -128, -128, + -128, -128, -128, -128, + }, + { + 126, 126, 126, 126, + -2, -2, -2, -2, + 127, 127, 127, 127, + -127, -127, -127, -127, + }, + { + 126, 126, 126, 126, + 62, 62, 62, 62, + -1, -1, -1, -1, + -128, -128, -128, -128, + }, + }, +}; + +int16_t TEST_AVG_DATA(int16_t, avg_floor)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 4, 4, 4, 4, + }, + }, + { + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + }, + { + 32766, 32766, 32766, 32766, + -2, -2, -2, -2, + 32767, 32767, 32767, 32767, + -32767, -32767, -32767, -32767, + }, + { + 32766, 32766, 32766, 32766, + 16382, 16382, 16382, 16382, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + }, + }, +}; + +int32_t TEST_AVG_DATA(int32_t, avg_floor)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 4, 4, 4, 4, + }, + }, + { + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 2147483646, 2147483646, 2147483646, 2147483646, + -2, -2, -2, -2, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483647, -2147483647, -2147483647, -2147483647, + }, + { + 2147483646, 2147483646, 2147483646, 2147483646, + 1073741822, 1073741822, 1073741822, 1073741822, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + }, +}; + +int64_t TEST_AVG_DATA(int64_t, avg_floor)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 4, 4, 4, 4, + }, + }, + { + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + -2ull, -2ull, -2ull, -2ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + }, + { + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + 4611686018427387902ull, 4611686018427387902ull, 4611686018427387902ull, 4611686018427387902ull, + -1ull, -1ull, -1ull, -1ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + }, +}; + +int8_t TEST_AVG_DATA(int8_t, avg_ceil)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 5, 5, 5, 5, + }, + }, + { + { + 127, 127, 127, 127, + 127, 127, 127, 127, + -128, -128, -128, -128, + -128, -128, -128, -128, + }, + { + 126, 126, 126, 126, + -2, -2, -2, -2, + 127, 127, 127, 127, + -127, -127, -127, -127, + }, + { + 127, 127, 127, 127, + 63, 63, 63, 63, + 0, 0, 0, 0, + -127, -127, -127, -127, + }, + }, +}; + +int16_t TEST_AVG_DATA(int16_t, avg_ceil)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 5, 5, 5, 5, + }, + }, + { + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + }, + { + 32766, 32766, 32766, 32766, + -2, -2, -2, -2, + 32767, 32767, 32767, 32767, + -32767, -32767, -32767, -32767, + }, + { + 32767, 32767, 32767, 32767, + 16383, 16383, 16383, 16383, + 0, 0, 0, 0, + -32767, -32767, -32767, -32767, + }, + }, +}; + +int32_t TEST_AVG_DATA(int32_t, avg_ceil)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 5, 5, 5, 5, + }, + }, + { + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + { + 2147483646, 2147483646, 2147483646, 2147483646, + -2, -2, -2, -2, + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483647, -2147483647, -2147483647, -2147483647, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 1073741823, 1073741823, 1073741823, 1073741823, + 0, 0, 0, 0, + -2147483647, -2147483647, -2147483647, -2147483647, + }, + }, +}; + +int64_t TEST_AVG_DATA(int64_t, avg_ceil)[][3][N] = +{ + { + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 8, 8, 8, 8, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -2, -2, -2, -2, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 5, 5, 5, 5, + }, + }, + { + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + { + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + -2ull, -2ull, -2ull, -2ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 4611686018427387903ull, 4611686018427387903ull, 4611686018427387903ull, 4611686018427387903ull, + 0ull, 0ull, 0ull, 0ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + }, + }, +}; + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c new file mode 100644 index 0000000..fc7943c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int16_t +#define WT int32_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c new file mode 100644 index 0000000..e02e5df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i16-from-i64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int16_t +#define WT int64_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c new file mode 100644 index 0000000..e36e424 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i32-from-i64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int32_t +#define WT int64_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c new file mode 100644 index 0000000..3e2d97d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i64-from-i128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int64_t +#define WT int128_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c new file mode 100644 index 0000000..cdbb299 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i16.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int8_t +#define WT int16_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c new file mode 100644 index 0000000..53508b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i32.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int8_t +#define WT int32_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c new file mode 100644 index 0000000..9a6d1a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-1-i8-from-i64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d" } */ + +#include "avg.h" + +#define NT int8_t +#define WT int64_t + +DEF_AVG_0_WRAP(NT, WT, avg_floor) + +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i32.c new file mode 100644 index 0000000..92239a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int32_t +#define NT int16_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i64.c new file mode 100644 index 0000000..5716c29 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i16-from-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int64_t +#define NT int16_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i32-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i32-from-i64.c new file mode 100644 index 0000000..705e091 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i32-from-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int64_t +#define NT int32_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i64-from-i128.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i64-from-i128.c new file mode 100644 index 0000000..91e9809 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i64-from-i128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int128_t +#define NT int64_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i16.c new file mode 100644 index 0000000..abe5c5b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int16_t +#define NT int8_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i32.c new file mode 100644 index 0000000..355b90f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int32_t +#define NT int8_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i64.c new file mode 100644 index 0000000..a9ae96f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_floor-run-1-i8-from-i64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -Wno-pedantic" } */ + +#include "avg.h" +#include "avg_data.h" + +#define WT int64_t +#define NT int8_t +#define NAME avg_floor + +DEF_AVG_0_WRAP(NT, WT, NAME) + +#define TEST_DATA TEST_AVG_DATA_WRAP(NT, NAME) +#define TEST_RUN(NT, WT, NAME, a, b, out, n) RUN_AVG_0_WRAP(NT, WT, NAME, a, b, out, n) + +#include "avg_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_run.h new file mode 100644 index 0000000..a6bbee9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/avg_run.h @@ -0,0 +1,26 @@ +#ifndef HAVE_DEFINED_AVG_RUN_H +#define HAVE_DEFINED_AVG_RUN_H + +int +main () +{ + unsigned i, k; + NT out[N]; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + NT *a = TEST_DATA[i][0]; + NT *b = TEST_DATA[i][1]; + NT *expect = TEST_DATA[i][2]; + + TEST_RUN (NT, WT, NAME, a, b, out, N); + + for (k = 0; k < N; k++) + if (out[k] != expect[k]) + __builtin_abort (); + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c index 667f457..fab8e79 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c index 1d8a19c..80bdb68 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie" } */ #include "vadd-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c index 0750d8e..a8be5ed 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c @@ -3,13 +3,13 @@ #include "vdiv-template.h" -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvdiv\.vx} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c index 31b2284..7feee0e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c @@ -3,10 +3,10 @@ #include "vdiv-template.h" -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvdiv\.vx} 3 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vx} 3 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */ /* Division by constant is done by calculating a reciprocal and then multiplying. Hence we do not expect 6 vfdivs. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c index 6015af9..766b17f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv-nofm.c @@ -3,13 +3,13 @@ #include "vdiv-template.h" -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdiv\.vx} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 3 } } */ -/* { dg-final { scan-assembler-times {\tvfdiv\.vf} 3 } } */ +/* { dg-final { scan-assembler-times {\tvfdiv\.vv} 6 } } */ +/* { dg-final { scan-assembler-not {\tvfdiv\.vf} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_DIV" 16 "optimized" } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_RDIV" 6 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c index ccaa2f8..c59c664 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c @@ -3,10 +3,10 @@ #include "vdiv-template.h" -/* { dg-final { scan-assembler-times {\tvdiv\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdiv\.vx} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvdivu\.vx} 4 } } */ +/* { dg-final { scan-assembler-times {\tvdiv\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdiv\.vx} } } */ +/* { dg-final { scan-assembler-times {\tvdivu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvdivu\.vx} } } */ /* Division by constant is done by calculating a reciprocal and then multiplying. Hence we do not expect 6 vfdivs. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c index a87a6c7..10de7c2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c @@ -2,10 +2,10 @@ #include "vrem-template.h" -/* { dg-final { scan-assembler-times {\tvrem\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvrem\.vx} 3 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 5 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vx} 3 } } */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvrem\.vx} } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvremu\.vx} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 16 "optimized" } } */ /* { dg-final { scan-assembler-not {\tvmv1r\.v} } } */ /* { dg-final { scan-assembler-not {\tvmv2r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c index 9381695..cf187a2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c @@ -3,10 +3,10 @@ #include "vrem-template.h" -/* { dg-final { scan-assembler-times {\tvrem\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvrem\.vx} 4 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vv} 4 } } */ -/* { dg-final { scan-assembler-times {\tvremu\.vx} 4 } } */ +/* { dg-final { scan-assembler-times {\tvrem\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvrem\.vx} } } */ +/* { dg-final { scan-assembler-times {\tvremu\.vv} 8 } } */ +/* { dg-final { scan-assembler-not {\tvremu\.vx} } } */ /* { dg-final { scan-tree-dump-times "\.COND_LEN_MOD" 16 "optimized" } } */ /* { dg-final { scan-assembler-not {\tvmv1r\.v} } } */ /* { dg-final { scan-assembler-not {\tvmv2r\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c index 1b6d50e..28b9235 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv32gcv_zvfh -mabi=ilp32d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c index 0b22e9a..b048949 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv-nofm.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details" } */ +/* { dg-additional-options "-std=c99 -fno-vect-cost-model -march=rv64gcv_zvfh -mabi=lp64d -mrvv-vector-bits=scalable -fdump-tree-optimized-details -fno-pie" } */ #include "vsub-template.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/param-autovec-mode.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/param-autovec-mode.c new file mode 100644 index 0000000..1ee7eb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/param-autovec-mode.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=rv64gcv -mabi=lp64d --param=riscv-autovec-mode=V4QI -fdump-tree-vect-details" } */ + +/* By default we will use RVVM1SI mode for vectorization because N is not + known. Check that we use V4QI and create an epilogue when the autovec-mode + param is specified. */ + +void +foo (int *a, int *b, int n) +{ + for (int i = 0; i < n; i++) + a[i] = b[i] + 1; +} + +/* { dg-final { scan-tree-dump "Choosing vector mode V4QI" "vect" } } */ +/* { dg-final { scan-tree-dump "Choosing epilogue vector mode RVVM1SI" "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c new file mode 100644 index 0000000..2913f04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-require-effective-target rvv_zvl256b_ok } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -O2" } */ + +unsigned char a = 5; +long long c[18]; + +static void d () +{ + for (short i = 0; i < 60; i += 65413) + for (char j = 0; j < 18; j++) + { + for (char k = 0; k < 18; k++) + a *= 143; + for (char k = 0; k < 6; k++) + for (char l = 0; l < 18; l++) + c[l] = 0; + } +} + +int main () +{ + d (); + if (a + c[0] != 69) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-1.c new file mode 100644 index 0000000..260e4c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-1.c @@ -0,0 +1,5 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvl256b -mabi=lp64d -O3" } */ + +#include "pr120652.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-2.c new file mode 100644 index 0000000..6f85942 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-2.c @@ -0,0 +1,5 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvl512b -mabi=lp64d -O3" } */ + +#include "pr120652.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-3.c new file mode 100644 index 0000000..9852b5d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652-3.c @@ -0,0 +1,5 @@ +/* Test that we do not have ice when compile */ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zvl1024b -mabi=lp64d -O3" } */ + +#include "pr120652.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652.h new file mode 100644 index 0000000..75f2716 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120652.h @@ -0,0 +1,31 @@ +#ifndef HAVE_DEFINED_PR120652_H +#define HAVE_DEFINED_PR120652_H + +unsigned n; +char ab[6]; +unsigned ac; +unsigned ae; + +int ak(int bb) { +bd: + for (ac = -17; ac != 16; ac++) { + unsigned be = 95; + if (be <= n) { + char *bg = &ab[1]; + *bg ^= bb; + } else { + ae--; + for (n = 8; 0;) + goto bd; + } + } + return 0; +} + +int main() { + ak(7); + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h index 7db892c..93c29f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h @@ -123,6 +123,22 @@ vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ } \ } +#define DEF_VEC_SAT_U_ADD_FMT_9(WT, T) \ +void __attribute__((noinline)) \ +vec_sat_u_add_##WT##_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + T max = -1; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + WT val = (WT)x + (WT)y; \ + out[i] = val > max ? max : (T)val; \ + } \ +} +#define DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) DEF_VEC_SAT_U_ADD_FMT_9(WT, T) + #define RUN_VEC_SAT_U_ADD_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_add_##T##_fmt_1(out, op_1, op_2, N) @@ -147,6 +163,21 @@ vec_sat_u_add_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_ADD_FMT_8(T, out, op_1, op_2, N) \ vec_sat_u_add_##T##_fmt_8(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16(T, out, op_1, op_2, N) \ + vec_sat_u_add_uint16_t_##T##_fmt_9(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16(T, out, op_1, op_2, N) + +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32(T, out, op_1, op_2, N) \ + vec_sat_u_add_uint32_t_##T##_fmt_9(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32(T, out, op_1, op_2, N) + +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64(T, out, op_1, op_2, N) \ + vec_sat_u_add_uint64_t_##T##_fmt_9(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64(T, out, op_1, op_2, N) + #define DEF_VEC_SAT_U_ADD_IMM_FMT_1(T, IMM) \ T __attribute__((noinline)) \ vec_sat_u_add_imm##IMM##_##T##_fmt_1 (T *out, T *in, unsigned limit) \ @@ -314,6 +345,31 @@ vec_sat_s_add_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_S_ADD_FMT_4_WRAP(T, out, op_1, op_2, N) \ RUN_VEC_SAT_S_ADD_FMT_4(T, out, op_1, op_2, N) +#define DEF_VEC_SAT_S_ADD_IMM_FMT_1(INDEX, T, UT, IMM, MIN, MAX) \ +void __attribute__((noinline)) \ +vec_sat_s_add_imm_##T##_fmt_1##_##INDEX (T *out, T *op_1, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T sum = (UT)x + (UT)IMM; \ + out[i] = (x ^ IMM) < 0 \ + ? sum \ + : (sum ^ x) >= 0 \ + ? sum \ + : x < 0 ? MIN : MAX; \ + } \ +} +#define DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(INDEX, T, UT, IMM, MIN, MAX) \ + DEF_VEC_SAT_S_ADD_IMM_FMT_1(INDEX, T, UT, IMM, MIN, MAX) + +#define RUN_VEC_SAT_S_ADD_IMM_FMT_1(INDEX, T, out, in, expect, IMM, N) \ + vec_sat_s_add_imm_##T##_fmt_1##_##INDEX (out, in, N); \ + VALIDATE_RESULT (out, expect, N) +#define RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(INDEX, T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_S_ADD_IMM_FMT_1(INDEX, T, out, in, expect, IMM, N) + /******************************************************************************/ /* Saturation Sub (Unsigned and Signed) */ /******************************************************************************/ @@ -329,6 +385,8 @@ vec_sat_u_sub_##T##_fmt_1 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = (x - y) & (-(T)(x >= y)); \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_1(T) #define DEF_VEC_SAT_U_SUB_FMT_2(T) \ void __attribute__((noinline)) \ @@ -342,6 +400,8 @@ vec_sat_u_sub_##T##_fmt_2 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = (x - y) & (-(T)(x > y)); \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_2(T) #define DEF_VEC_SAT_U_SUB_FMT_3(T) \ void __attribute__((noinline)) \ @@ -355,6 +415,8 @@ vec_sat_u_sub_##T##_fmt_3 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = x > y ? x - y : 0; \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_3(T) #define DEF_VEC_SAT_U_SUB_FMT_4(T) \ void __attribute__((noinline)) \ @@ -368,6 +430,8 @@ vec_sat_u_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = x >= y ? x - y : 0; \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_4(T) #define DEF_VEC_SAT_U_SUB_FMT_5(T) \ void __attribute__((noinline)) \ @@ -381,6 +445,8 @@ vec_sat_u_sub_##T##_fmt_5 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = x < y ? 0 : x - y; \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_5(T) #define DEF_VEC_SAT_U_SUB_FMT_6(T) \ void __attribute__((noinline)) \ @@ -394,6 +460,8 @@ vec_sat_u_sub_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = x <= y ? 0 : x - y; \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_6(T) #define DEF_VEC_SAT_U_SUB_FMT_7(T) \ void __attribute__((noinline)) \ @@ -409,6 +477,8 @@ vec_sat_u_sub_##T##_fmt_7 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = ret & (T)(overflow - 1); \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_7(T) #define DEF_VEC_SAT_U_SUB_FMT_8(T) \ void __attribute__((noinline)) \ @@ -424,6 +494,8 @@ vec_sat_u_sub_##T##_fmt_8 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = ret & (T)-(!overflow); \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_8(T) #define DEF_VEC_SAT_U_SUB_FMT_9(T) \ void __attribute__((noinline)) \ @@ -439,6 +511,8 @@ vec_sat_u_sub_##T##_fmt_9 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = overflow ? 0 : ret; \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_9(T) #define DEF_VEC_SAT_U_SUB_FMT_10(T) \ void __attribute__((noinline)) \ @@ -454,6 +528,42 @@ vec_sat_u_sub_##T##_fmt_10 (T *out, T *op_1, T *op_2, unsigned limit) \ out[i] = !overflow ? ret : 0; \ } \ } +#define DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_10(T) + +#define DEF_VEC_SAT_U_SUB_FMT_11(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_11 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + T ret; \ + T overflow = __builtin_sub_overflow (x, y, &ret); \ + out[i] = overflow ? 0 : ret; \ + } \ +} +#define DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_11(T) + +#define DEF_VEC_SAT_U_SUB_FMT_12(T) \ +void __attribute__((noinline)) \ +vec_sat_u_sub_##T##_fmt_12 (T *out, T *op_1, T *op_2, unsigned limit) \ +{ \ + unsigned i; \ + for (i = 0; i < limit; i++) \ + { \ + T x = op_1[i]; \ + T y = op_2[i]; \ + T ret; \ + T overflow = __builtin_sub_overflow (x, y, &ret); \ + out[i] = !overflow ? ret : 0; \ + } \ +} +#define DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) \ + DEF_VEC_SAT_U_SUB_FMT_12(T) #define DEF_VEC_SAT_U_SUB_ZIP(T1, T2) \ void __attribute__((noinline)) \ @@ -613,33 +723,63 @@ vec_sat_s_sub_##T##_fmt_4 (T *out, T *op_1, T *op_2, unsigned limit) \ #define RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_1(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_1(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_2(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_2(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_2(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_3(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_3(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_3(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_4(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_4(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_4(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_5(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_5(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_5(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_6(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_6(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_6(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_7(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_7(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_7(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_8(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_8(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_8(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_9(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_9(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_9(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) \ vec_sat_u_sub_##T##_fmt_10(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_10(T, out, op_1, op_2, N) + +#define RUN_VEC_SAT_U_SUB_FMT_11(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_11(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11(T, out, op_1, op_2, N) + +#define RUN_VEC_SAT_U_SUB_FMT_12(T, out, op_1, op_2, N) \ + vec_sat_u_sub_##T##_fmt_12(out, op_1, op_2, N) +#define RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12(T, out, op_1, op_2, N) #define RUN_VEC_SAT_U_SUB_FMT_ZIP(T1, T2, x, b, N) \ vec_sat_u_sub_##T1##_##T2##_fmt_zip(x, b, N) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h index ec4d64c..7647439 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h @@ -744,6 +744,498 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_sub_imm)[][2][N] = }, }; +uint8_t TEST_UNARY_DATA(uint8_t, ussub)[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + 0, 255, 255, 255, + }, + { + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + 1, 255, 254, 251, + }, + { + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + 0, 0, 1, 4, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 255, + 5, 254, 255, 9, + }, + { + 0, 1, 0, 254, + 254, 254, 254, 255, + 255, 255, 0, 252, + 255, 255, 255, 1, + }, + { + 0, 0, 1, 0, + 0, 0, 0, 0, + 0, 0, 3, 3, + 0, 0, 0, 8, + }, + }, +}; + +uint16_t TEST_UNARY_DATA(uint16_t, ussub)[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + 55535, 45535, 35535, 25535, + }, + { + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + 10000, 20000, 30000, 40000, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 65535, 3, 65535, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 1, 65535, + 0, 65535, 65535, 0, + 65535, 65535, 1, 2, + }, + { + 0, 0, 0, 0, + 0, 0, 2, 0, + 1, 0, 0, 65535, + 0, 0, 65534, 7, + }, + }, +}; + +uint32_t TEST_UNARY_DATA(uint32_t, ussub)[][3][N] = { + { + { + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + 0, 0, 4, 0, + }, /* arg_0 */ + { + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + 0, 1, 2, 3, + }, /* arg_1 */ + { + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + 0, 0, 2, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + 1294967295, 2294967295, 3294967295, 4294967295, + }, + { + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + 3000000000, 2000000000, 1000000000, 0, + }, + }, + { + { + 0, 0, 9, 0, + 1, 4294967295, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 4294967295, + }, + { + 0, 1, 1, 4294967294, + 1, 2, 4294967294, 4294967295, + 1, 4294967295, 4294967295, 1, + 1, 4294967295, 4294967290, 9, + }, + { + 0, 0, 8, 0, + 0, 4294967293, 0, 0, + 0, 0, 0, 3, + 4, 0, 5, 4294967286, + }, + }, +}; + +uint64_t TEST_UNARY_DATA(uint64_t, ussub)[][3][N] = { + { + { + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + 0, 9, 0, 0, + }, /* arg_0 */ + { + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + 0, 2, 3, 1, + }, /* arg_1 */ + { + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + 0, 7, 0, 0, + }, /* expect */ + }, + { + { + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + }, + { + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, + }, + { + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, + }, + }, + { + { + 0, 18446744073709551615u, 1, 0, + 1, 18446744073709551615u, 3, 0, + 1, 18446744073709551614u, 3, 4, + 5, 18446744073709551614u, 18446744073709551615u, 9, + }, + { + 0, 1, 1, 18446744073709551614u, + 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, + 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, + }, + { + 0, 18446744073709551614u, 0, 0, + 0, 1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 8, + }, + }, +}; + +int8_t TEST_UNARY_DATA(int8_t, sat_s_add_imm)[][2][N] = +{ + { /* For add imm -128 */ + { + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + }, + { + -128, -128, -28, -1, + -128, -128, -28, -1, + -128, -128, -28, -1, + -128, -128, -28, -1, + }, + }, + { /* For add imm 0 */ + { + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + }, + { + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + }, + }, + { /* For add imm 1 */ + { + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + }, + { + -127, 1, 101, 127, + -127, 1, 101, 127, + -127, 1, 101, 127, + -127, 1, 101, 127, + }, + }, + { /* For add imm 127 */ + { + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + -128, 0, 100, 127, + }, + { + -1, 127, 127, 127, + -1, 127, 127, 127, + -1, 127, 127, 127, + -1, 127, 127, 127, + }, + }, +}; + +int16_t TEST_UNARY_DATA(int16_t, sat_s_add_imm)[][2][N] = +{ + { /* For add imm -32768 */ + { + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + }, + { + -32768, -32768, -32668, -1, + -32768, -32768, -32668, -1, + -32768, -32768, -32668, -1, + -32768, -32768, -32668, -1, + }, + }, + { /* For add imm 0 */ + { + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + }, + { + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + }, + }, + { /* For add imm 1 */ + { + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + }, + { + -32767, 1, 101, 32767, + -32767, 1, 101, 32767, + -32767, 1, 101, 32767, + -32767, 1, 101, 32767, + }, + }, + { /* For add imm 32767 */ + { + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + -32768, 0, 100, 32767, + }, + { + -1, 32767, 32767, 32767, + -1, 32767, 32767, 32767, + -1, 32767, 32767, 32767, + -1, 32767, 32767, 32767, + }, + }, +}; + +int32_t TEST_UNARY_DATA(int32_t, sat_s_add_imm)[][2][N] = +{ + { /* For add imm -2147483648 */ + { + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + }, + { + -2147483648, -2147483648, -2147483548, -1, + -2147483648, -2147483648, -2147483548, -1, + -2147483648, -2147483648, -2147483548, -1, + -2147483648, -2147483648, -2147483548, -1, + }, + }, + { /* For add imm 0 */ + { + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + }, + { + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + }, + }, + { /* For add imm 1 */ + { + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + }, + { + -2147483647, 1, 101, 2147483647, + -2147483647, 1, 101, 2147483647, + -2147483647, 1, 101, 2147483647, + -2147483647, 1, 101, 2147483647, + }, + }, + { /* For add imm 2147483647 */ + { + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + -2147483648, 0, 100, 2147483647, + }, + { + -1, 2147483647, 2147483647, 2147483647, + -1, 2147483647, 2147483647, 2147483647, + -1, 2147483647, 2147483647, 2147483647, + -1, 2147483647, 2147483647, 2147483647, + }, + }, +}; + +int64_t TEST_UNARY_DATA(int64_t, sat_s_add_imm)[][2][N] = +{ + { /* For add imm -9223372036854775808ll */ + { + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + }, + { + INT64_MIN, INT64_MIN, -9223372036854775708ll, -1, + INT64_MIN, INT64_MIN, -9223372036854775708ll, -1, + INT64_MIN, INT64_MIN, -9223372036854775708ll, -1, + INT64_MIN, INT64_MIN, -9223372036854775708ll, -1, + }, + }, + { /* For add imm 0 */ + { + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + }, + { + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + }, + }, + { /* For add imm 1 */ + { + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + }, + { + -INT64_MAX, 1, 101, INT64_MAX, + -INT64_MAX, 1, 101, INT64_MAX, + -INT64_MAX, 1, 101, INT64_MAX, + -INT64_MAX, 1, 101, INT64_MAX, + }, + }, + { /* For add imm 9223372036854775807ll */ + { + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + INT64_MIN, 0, 100, INT64_MAX, + }, + { + -1, INT64_MAX, INT64_MAX, INT64_MAX, + -1, INT64_MAX, INT64_MAX, INT64_MAX, + -1, INT64_MAX, INT64_MAX, INT64_MAX, + -1, INT64_MAX, INT64_MAX, INT64_MAX, + }, + }, +}; + #define TEST_BINARY_DATA_NAME(T1, T2, NAME) test_bin_##T1##_##T2##_##NAME##_data #define TEST_BINARY_DATA_NAME_WRAP(T1, T2, NAME) \ TEST_BINARY_DATA_NAME(T1, T2, NAME) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c new file mode 100644 index 0000000..396c741 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, 9, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c new file mode 100644 index 0000000..da9e538 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, 9, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c new file mode 100644 index 0000000..e9af1a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int64_t, uint64_t, 9, INT64_MIN, INT64_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c new file mode 100644 index 0000000..66b9d7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, 9, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target { no-opts "-O2" } } } } */ +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target { no-opts "-O3" } } } } */ +/* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i16.c new file mode 100644 index 0000000..fbfa4e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i16.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T int16_t +#define RUN(INDEX, T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP (INDEX, T, out, in, expect, IMM, N) + +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(0, int16_t, uint16_t, -32768, INT16_MIN, INT16_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(1, int16_t, uint16_t, 0, INT16_MIN, INT16_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(2, int16_t, uint16_t, 1, INT16_MIN, INT16_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(3, int16_t, uint16_t, 32767, INT16_MIN, INT16_MAX) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_s_add_imm); + + RUN (0, T, out, d[0][0], d[0][1], -32768, N); + RUN (1, T, out, d[1][0], d[1][1], 0, N); + RUN (2, T, out, d[2][0], d[2][1], 1, N); + RUN (3, T, out, d[3][0], d[3][1], 32767, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i32.c new file mode 100644 index 0000000..5f1763c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i32.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T int32_t +#define RUN(INDEX, T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP (INDEX, T, out, in, expect, IMM, N) + +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(0, int32_t, uint32_t, -2147483648, INT32_MIN, INT32_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(1, int32_t, uint32_t, 0, INT32_MIN, INT32_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(2, int32_t, uint32_t, 1, INT32_MIN, INT32_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(3, int32_t, uint32_t, 2147483647, INT32_MIN, INT32_MAX) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_s_add_imm); + + RUN (0, T, out, d[0][0], d[0][1], -2147483648, N); + RUN (1, T, out, d[1][0], d[1][1], 0, N); + RUN (2, T, out, d[2][0], d[2][1], 1, N); + RUN (3, T, out, d[3][0], d[3][1], 2147483647, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i64.c new file mode 100644 index 0000000..435eb1b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i64.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T int64_t +#define RUN(INDEX, T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP (INDEX, T, out, in, expect, IMM, N) + +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(0, int64_t, uint64_t, INT64_MIN, INT64_MIN, INT64_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(1, int64_t, uint64_t, 0, INT64_MIN, INT64_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(2, int64_t, uint64_t, 1, INT64_MIN, INT64_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(3, int64_t, uint64_t, INT64_MAX, INT64_MIN, INT64_MAX) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_s_add_imm); + + RUN (0, T, out, d[0][0], d[0][1], INT64_MIN, N); + RUN (1, T, out, d[1][0], d[1][1], 0, N); + RUN (2, T, out, d[2][0], d[2][1], 1, N); + RUN (3, T, out, d[3][0], d[3][1], INT64_MAX, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i8.c new file mode 100644 index 0000000..535e873 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i8.c @@ -0,0 +1,28 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T int8_t +#define RUN(INDEX, T, out, in, expect, IMM, N) \ + RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP (INDEX, T, out, in, expect, IMM, N) + +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(0, int8_t, uint8_t, -128, INT8_MIN, INT8_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(1, int8_t, uint8_t, 0, INT8_MIN, INT8_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(2, int8_t, uint8_t, 1, INT8_MIN, INT8_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(3, int8_t, uint8_t, 127, INT8_MIN, INT8_MAX) + +int +main () +{ + T out[N]; + T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_s_add_imm); + + RUN (0, T, out, d[0][0], d[0][1], -128, N); + RUN (1, T, out, d[1][0], d[1][1], 0, N); + RUN (2, T, out, d[2][0], d[2][1], 1, N); + RUN (3, T, out, d[3][0], d[3][1], 127, N); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i16.c new file mode 100644 index 0000000..26e96fc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, -32769, INT16_MIN, INT16_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1(1, int16_t, uint16_t, 32768, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i32.c new file mode 100644 index 0000000..519e72c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, -2147483649, INT32_MIN, INT32_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1(1, int32_t, uint32_t, 2147483648, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i8.c new file mode 100644 index 0000000..2b0af52 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i8.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, 200, INT8_MIN, INT8_MAX) +DEF_VEC_SAT_S_ADD_IMM_FMT_1(1, int8_t, uint8_t, -300, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c new file mode 100644 index 0000000..6e9cbd2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint32_t, uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c new file mode 100644 index 0000000..3ab4641 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint64_t, uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c new file mode 100644 index 0000000..57aa772 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint64_t, uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c new file mode 100644 index 0000000..d14fe00 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint16_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c new file mode 100644 index 0000000..240af94 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint32_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c new file mode 100644 index 0000000..706d4f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_ADD_FMT_9(uint64_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c new file mode 100644 index 0000000..06d3ba0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define WT uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 65534, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 9, + }, + { + 0, 1, 2, 65534, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c new file mode 100644 index 0000000..64dbde7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint16_t +#define WT uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 65534, 65535, 9, + }, + { + 0, 1, 1, 65534, + 65534, 65534, 65534, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 9, + }, + { + 0, 1, 2, 65534, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c new file mode 100644 index 0000000..2523126 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint32_t +#define WT uint64_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U64_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 4294967294, 4294967295, 9, + }, + { + 0, 1, 1, 4294967294, + 4294967294, 4294967294, 4294967294, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 9, + }, + { + 0, 1, 2, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c new file mode 100644 index 0000000..4cd4817 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define WT uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 254, 255, 9, + }, + { + 0, 1, 1, 254, + 254, 254, 254, 255, + 255, 255, 255, 255, + 255, 255, 255, 9, + }, + { + 0, 1, 2, 254, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c new file mode 100644 index 0000000..6b46465 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define WT uint32_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U32_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 254, 255, 9, + }, + { + 0, 1, 1, 254, + 254, 254, 254, 255, + 255, 255, 255, 255, + 255, 255, 255, 9, + }, + { + 0, 1, 2, 254, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c new file mode 100644 index 0000000..4cd4817 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c @@ -0,0 +1,76 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" + +#define T uint8_t +#define WT uint16_t +#define N 16 +#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_ADD_FMT_9_FROM_U16_WRAP + +DEF_VEC_SAT_U_ADD_FMT_9_WRAP(WT, T) + +T test_data[][3][N] = { + { + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_0 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* arg_1 */ + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, /* expect */ + }, + { + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + }, + { + { + 0, 0, 1, 0, + 1, 2, 3, 0, + 1, 2, 3, 4, + 5, 254, 255, 9, + }, + { + 0, 1, 1, 254, + 254, 254, 254, 255, + 255, 255, 255, 255, + 255, 255, 255, 9, + }, + { + 0, 1, 2, 254, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 18, + }, + }, +}; + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c new file mode 100644 index 0000000..57da9e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c new file mode 100644 index 0000000..b5264a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c new file mode 100644 index 0000000..1a68b5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c new file mode 100644 index 0000000..a1c5c19 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-11-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_11(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c new file mode 100644 index 0000000..fd987e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c new file mode 100644 index 0000000..bc380fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c new file mode 100644 index 0000000..c03163f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c new file mode 100644 index 0000000..91e1909 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-12-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-tree-optimized" } */ + +#include "vec_sat_arith.h" + +DEF_VEC_SAT_U_SUB_FMT_12(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_SUB " 2 "optimized" } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c index 97e5040..5878c5b6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 -DEF_VEC_SAT_U_SUB_FMT_1(T) +DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c index a5428c4..f74979f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 -DEF_VEC_SAT_U_SUB_FMT_1(T) +DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c index bdb65d9..1250e5b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 -DEF_VEC_SAT_U_SUB_FMT_1(T) +DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c index 3fe5fe3..a2a77dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-1-u8.c @@ -2,74 +2,15 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_1 -DEF_VEC_SAT_U_SUB_FMT_1(T) +DEF_VEC_SAT_U_SUB_FMT_1_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_1_WRAP(T, out, op_1, op_2, N) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c index 0f4129c..19c8fa0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 -DEF_VEC_SAT_U_SUB_FMT_10(T) +DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c index 8b995eb..ada136f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 -DEF_VEC_SAT_U_SUB_FMT_10(T) +DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c index d12d981..488c158 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 -DEF_VEC_SAT_U_SUB_FMT_10(T) +DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c index 384ef3e..127c27a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-10-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_10 -DEF_VEC_SAT_U_SUB_FMT_10(T) +DEF_VEC_SAT_U_SUB_FMT_10_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_10_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c new file mode 100644 index 0000000..4b49467 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint16_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c new file mode 100644 index 0000000..80b55ea --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint32_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c new file mode 100644 index 0000000..6a89d0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint64_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c new file mode 100644 index 0000000..974493e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-11-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint8_t + +DEF_VEC_SAT_U_SUB_FMT_11_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_11_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c new file mode 100644 index 0000000..28778b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint16_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c new file mode 100644 index 0000000..936a39a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint32_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c new file mode 100644 index 0000000..b8fa65b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint64_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c new file mode 100644 index 0000000..6bff1e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-12-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "vec_sat_arith.h" +#include "vec_sat_data.h" + +#define T uint8_t + +DEF_VEC_SAT_U_SUB_FMT_12_WRAP(T) + +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_12_WRAP(T, out, op_1, op_2, N) + +#include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c index 5cf08ac..45bef88 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 -DEF_VEC_SAT_U_SUB_FMT_2(T) +DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c index 85c8454..6d8a653 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 -DEF_VEC_SAT_U_SUB_FMT_2(T) +DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c index 67d5ac5..0132d46 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 -DEF_VEC_SAT_U_SUB_FMT_2(T) +DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c index 809f07f..425f86f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-2-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_2 -DEF_VEC_SAT_U_SUB_FMT_2(T) +DEF_VEC_SAT_U_SUB_FMT_2_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_2_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c index 57839a9..97a8e08 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 -DEF_VEC_SAT_U_SUB_FMT_3(T) +DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c index ffb0dcc..9124899 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 -DEF_VEC_SAT_U_SUB_FMT_3(T) +DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c index 3966677..1e54ede 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 -DEF_VEC_SAT_U_SUB_FMT_3(T) +DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c index e795f62..d8d53b7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-3-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_3 -DEF_VEC_SAT_U_SUB_FMT_3(T) +DEF_VEC_SAT_U_SUB_FMT_3_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_3_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c index 0eecf82..b293823 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 -DEF_VEC_SAT_U_SUB_FMT_4(T) +DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c index 1d0d16b..f0f1c4f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 -DEF_VEC_SAT_U_SUB_FMT_4(T) +DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c index 98fdfa2..27c28e2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 -DEF_VEC_SAT_U_SUB_FMT_4(T) +DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c index 18a887d..7911825 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-4-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_4 -DEF_VEC_SAT_U_SUB_FMT_4(T) +DEF_VEC_SAT_U_SUB_FMT_4_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_4_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c index ce44c04..6ae7b36 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 -DEF_VEC_SAT_U_SUB_FMT_5(T) +DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c index 36ae7b3..4e6b9e6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 -DEF_VEC_SAT_U_SUB_FMT_5(T) +DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c index 7b40ffd..6b26913 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 -DEF_VEC_SAT_U_SUB_FMT_5(T) +DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c index 3b0807f..2bd28cd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-5-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_5 -DEF_VEC_SAT_U_SUB_FMT_5(T) +DEF_VEC_SAT_U_SUB_FMT_5_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_5_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c index e972078..69b0be9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 -DEF_VEC_SAT_U_SUB_FMT_6(T) +DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c index 54e2848..2450586 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 -DEF_VEC_SAT_U_SUB_FMT_6(T) +DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c index 33f3be0..0b97910 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 -DEF_VEC_SAT_U_SUB_FMT_6(T) +DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c index 1376038..afb23f6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-6-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_6 -DEF_VEC_SAT_U_SUB_FMT_6(T) +DEF_VEC_SAT_U_SUB_FMT_6_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_6_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c index 83241ef..0466d4c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 -DEF_VEC_SAT_U_SUB_FMT_7(T) +DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c index f20bb21..14b8701 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 -DEF_VEC_SAT_U_SUB_FMT_7(T) +DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c index 4ad0afd..7e0afd8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 -DEF_VEC_SAT_U_SUB_FMT_7(T) +DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c index 3b33b13..40b1a6a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-7-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_7 -DEF_VEC_SAT_U_SUB_FMT_7(T) +DEF_VEC_SAT_U_SUB_FMT_7_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_7_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c index b212550..bd33048 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 -DEF_VEC_SAT_U_SUB_FMT_8(T) +DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c index 1fb707c..36f78f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 -DEF_VEC_SAT_U_SUB_FMT_8(T) +DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c index da8c09c..3bc5d5d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 -DEF_VEC_SAT_U_SUB_FMT_8(T) +DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c index 647607f..3964d1b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-8-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_8 -DEF_VEC_SAT_U_SUB_FMT_8(T) +DEF_VEC_SAT_U_SUB_FMT_8_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_8_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c index 9bb0664..4c0809a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u16.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint16_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 -DEF_VEC_SAT_U_SUB_FMT_9(T) +DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - 65535, 65535, 65535, 65535, - }, - { - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - 55535, 45535, 35535, 25535, - }, - { - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - 10000, 20000, 30000, 40000, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 65535, 3, 65535, - 5, 65534, 65535, 9, - }, - { - 0, 1, 1, 65534, - 65534, 65534, 1, 65535, - 0, 65535, 65535, 0, - 65535, 65535, 1, 2, - }, - { - 0, 0, 0, 0, - 0, 0, 2, 0, - 1, 0, 0, 65535, - 0, 0, 65534, 7, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c index f142b8b..3e700bd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u32.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint32_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 -DEF_VEC_SAT_U_SUB_FMT_9(T) +DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - 0, 0, 4, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - 0, 0, 2, 0, - }, /* expect */ - }, - { - { - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - 4294967295, 4294967295, 4294967295, 4294967295, - }, - { - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - 1294967295, 2294967295, 3294967295, 4294967295, - }, - { - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - 3000000000, 2000000000, 1000000000, 0, - }, - }, - { - { - 0, 0, 9, 0, - 1, 4294967295, 3, 0, - 1, 2, 3, 4, - 5, 4294967294, 4294967295, 4294967295, - }, - { - 0, 1, 1, 4294967294, - 1, 2, 4294967294, 4294967295, - 1, 4294967295, 4294967295, 1, - 1, 4294967295, 4294967290, 9, - }, - { - 0, 0, 8, 0, - 0, 4294967293, 0, 0, - 0, 0, 0, 3, - 4, 0, 5, 4294967286, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c index 574b91a..81b8dc8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u64.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint64_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 -DEF_VEC_SAT_U_SUB_FMT_9(T) +DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - 0, 9, 0, 0, - }, /* arg_0 */ - { - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - 0, 2, 3, 1, - }, /* arg_1 */ - { - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - 0, 7, 0, 0, - }, /* expect */ - }, - { - { - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - }, - { - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - 10446744073709551615u, 11446744073709551615u, 12446744073709551615u, 18446744073709551615u, - }, - { - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - 8000000000000000000u, 7000000000000000000u, 6000000000000000000u, 0u, - }, - }, - { - { - 0, 18446744073709551615u, 1, 0, - 1, 18446744073709551615u, 3, 0, - 1, 18446744073709551614u, 3, 4, - 5, 18446744073709551614u, 18446744073709551615u, 9, - }, - { - 0, 1, 1, 18446744073709551614u, - 18446744073709551614u, 18446744073709551614u, 18446744073709551614u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, - 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, 1, - }, - { - 0, 18446744073709551614u, 0, 0, - 0, 1, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c index 2c8ee42..8bc52ae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub-run-9-u8.c @@ -2,74 +2,14 @@ /* { dg-additional-options "-std=c99" } */ #include "vec_sat_arith.h" +#include "vec_sat_data.h" #define T uint8_t -#define N 16 -#define RUN_VEC_SAT_BINARY RUN_VEC_SAT_U_SUB_FMT_9 -DEF_VEC_SAT_U_SUB_FMT_9(T) +DEF_VEC_SAT_U_SUB_FMT_9_WRAP(T) -T test_data[][3][N] = { - { - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* arg_0 */ - { - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - 0, 1, 2, 3, - }, /* arg_1 */ - { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - }, /* expect */ - }, - { - { - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - 0, 255, 255, 255, - }, - { - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - 1, 255, 254, 251, - }, - { - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - 0, 0, 1, 4, - }, - }, - { - { - 0, 0, 1, 0, - 1, 2, 3, 0, - 1, 2, 3, 255, - 5, 254, 255, 9, - }, - { - 0, 1, 0, 254, - 254, 254, 254, 255, - 255, 255, 0, 252, - 255, 255, 255, 1, - }, - { - 0, 0, 1, 0, - 0, 0, 0, 0, - 0, 0, 3, 3, - 0, 0, 0, 8, - }, - }, -}; +#define test_data TEST_UNARY_DATA_WRAP(T, ussub) +#define RUN_VEC_SAT_BINARY(T, out, op_1, op_2, N) \ + RUN_VEC_SAT_U_SUB_FMT_9_WRAP(T, out, op_1, op_2, N) #include "vec_sat_binary_vvv_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c index 2261872..b32907a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u16.c @@ -6,5 +6,5 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint16_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ /* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c index 4250567..344080c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u32.c @@ -6,5 +6,5 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint32_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ /* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c index 656aad7..492c316 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_sub_trunc-1-u8.c @@ -6,5 +6,5 @@ DEF_VEC_SAT_U_SUB_TRUNC_FMT_1(uint8_t, uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ -/* { dg-final { scan-assembler-times {vssubu\.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv} 1 } } */ /* { dg-final { scan-assembler-times {vnsrl\.wi} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c index 4dc5703..0fa1ea0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c @@ -72,7 +72,7 @@ f_vnx128qi (int8_t *out) *(vnx128qi *) out = v; } -/* { dg-final { scan-assembler-times {vmv.v.x\tv[0-9]+,\s*[a-x0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {vmv.v.x\tv[0-9]+,\s*[a-x0-9]+} 7 } } */ /* { dg-final { scan-assembler-times {slli\t[a-x0-9]+,\s*[a-x0-9]+,\s*8} 6 } } */ /* { dg-final { scan-assembler-times {or\t[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+} 6 } } */ /* { dg-final { scan-assembler-times {vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c index 30e60d5..4920fa6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-1.c @@ -25,9 +25,8 @@ DEF_AVG_FLOOR (uint8_t, uint16_t, 512) DEF_AVG_FLOOR (uint8_t, uint16_t, 1024) DEF_AVG_FLOOR (uint8_t, uint16_t, 2048) -/* { dg-final { scan-assembler-times {vwadd\.vv} 10 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 10 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 10 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 20 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 10 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 10 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c index 33df429..c6a120b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-2.c @@ -23,9 +23,8 @@ DEF_AVG_FLOOR (uint16_t, uint32_t, 256) DEF_AVG_FLOOR (uint16_t, uint32_t, 512) DEF_AVG_FLOOR (uint16_t, uint32_t, 1024) -/* { dg-final { scan-assembler-times {vwadd\.vv} 9 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 9 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 9 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 18 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 9 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 9 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c index 9058905..2838c1e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-3.c @@ -21,9 +21,8 @@ DEF_AVG_FLOOR (uint32_t, uint64_t, 128) DEF_AVG_FLOOR (uint32_t, uint64_t, 256) DEF_AVG_FLOOR (uint32_t, uint64_t, 512) -/* { dg-final { scan-assembler-times {vwadd\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 8 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 8 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 16 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 8 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 8 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c index 8d106aa..986a0ff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-4.c @@ -25,11 +25,9 @@ DEF_AVG_CEIL (uint8_t, uint16_t, 512) DEF_AVG_CEIL (uint8_t, uint16_t, 1024) DEF_AVG_CEIL (uint8_t, uint16_t, 2048) -/* { dg-final { scan-assembler-times {vwadd\.vv} 10 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 10 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 10 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 20 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 10 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 10 } } */ -/* { dg-final { scan-assembler-times {vadd\.vi} 10 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c index 981abd5..c450f80 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-5.c @@ -23,11 +23,9 @@ DEF_AVG_CEIL (uint16_t, uint32_t, 256) DEF_AVG_CEIL (uint16_t, uint32_t, 512) DEF_AVG_CEIL (uint16_t, uint32_t, 1024) -/* { dg-final { scan-assembler-times {vwadd\.vv} 9 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 9 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 9 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 18 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 9 } } */ -/* { dg-final { scan-assembler-times {vadd\.vi} 9 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 9 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c index bfe4ba3..3473e19 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/avg-6.c @@ -21,11 +21,9 @@ DEF_AVG_CEIL (uint16_t, uint32_t, 128) DEF_AVG_CEIL (uint16_t, uint32_t, 256) DEF_AVG_CEIL (uint16_t, uint32_t, 512) -/* { dg-final { scan-assembler-times {vwadd\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 8 } } */ -/* { dg-final { scan-assembler-times {vnsra\.wi} 8 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 16 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {vadd\.vi} 8 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 8 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ /* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ /* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c new file mode 100644 index 0000000..811f26c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_0 (_Float16, +, +, add) +DEF_VF_MULOP_CASE_0 (_Float16, -, +, sub) +DEF_VF_MULOP_CASE_0 (_Float16, +, -, nadd) +DEF_VF_MULOP_CASE_0 (_Float16, -, -, nsub) +DEF_VF_MULOP_ACC_CASE_0 (_Float16, +, +, acc) +DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, +, sac) +DEF_VF_MULOP_ACC_CASE_0 (_Float16, +, -, nacc) +DEF_VF_MULOP_ACC_CASE_0 (_Float16, -, -, nsac) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac) + +/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmsub.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c new file mode 100644 index 0000000..ca82ead --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_0 (float, +, +, add) +DEF_VF_MULOP_CASE_0 (float, -, +, sub) +DEF_VF_MULOP_CASE_0 (float, +, -, nadd) +DEF_VF_MULOP_CASE_0 (float, -, -, nsub) +DEF_VF_MULOP_ACC_CASE_0 (float, +, +, acc) +DEF_VF_MULOP_ACC_CASE_0 (float, -, +, sac) +DEF_VF_MULOP_ACC_CASE_0 (float, +, -, nacc) +DEF_VF_MULOP_ACC_CASE_0 (float, -, -, nsac) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac) + +/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmsub.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c new file mode 100644 index 0000000..4de038c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_0 (double, +, +, add) +DEF_VF_MULOP_CASE_0 (double, -, +, sub) +DEF_VF_MULOP_CASE_0 (double, +, -, nadd) +DEF_VF_MULOP_CASE_0 (double, -, -, nsub) +DEF_VF_MULOP_ACC_CASE_0 (double, +, +, acc) +DEF_VF_MULOP_ACC_CASE_0 (double, -, +, sac) +DEF_VF_MULOP_ACC_CASE_0 (double, +, -, nacc) +DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac) + +/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmadd.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmsub.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfmsac.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmacc.vf} 1 } } */ +/* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c new file mode 100644 index 0000000..3a39303 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=1" } */ + +#include "vf-1-f16.c" + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-times {fcvt.s.h} 4 } } */ +/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c new file mode 100644 index 0000000..b4618bae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=1" } */ + +#include "vf-1-f32.c" + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler-times {fcvt.d.s} 4 } } */ +/* { dg-final { scan-assembler-times {vfmv.v.f} 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c new file mode 100644 index 0000000..a2ac67e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=1" } */ + +#include "vf-1-f64.c" + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c new file mode 100644 index 0000000..58afaa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_1 (_Float16, +, +, add, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (_Float16, -, +, sub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (_Float16, +, -, nadd, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (_Float16, -, -, nsub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, +, acc, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, +, sac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (_Float16, +, -, nacc, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (_Float16, -, -, nsac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac) + +/* { dg-final { scan-assembler {vfmadd.vf} } } */ +/* { dg-final { scan-assembler {vfmsub.vf} } } */ +/* { dg-final { scan-assembler {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler {vfmacc.vf} } } */ +/* { dg-final { scan-assembler {vfmsac.vf} } } */ +/* { dg-final { scan-assembler {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c new file mode 100644 index 0000000..0e95774 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_1 (float, +, +, add, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (float, -, +, sub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (float, +, -, nadd, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (float, -, -, nsub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_ACC_CASE_1 (float, +, +, acc, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (float, -, +, sac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (float, +, -, nacc, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (float, -, -, nsac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, +, acc) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, +, sac) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, -, nacc) +DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac) + +/* { dg-final { scan-assembler {vfmadd.vf} } } */ +/* { dg-final { scan-assembler {vfmsub.vf} } } */ +/* { dg-final { scan-assembler {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler {vfmacc.vf} } } */ +/* { dg-final { scan-assembler {vfmsac.vf} } } */ +/* { dg-final { scan-assembler {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfwnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c new file mode 100644 index 0000000..71bd7e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +DEF_VF_MULOP_CASE_1 (double, +, +, add, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (double, -, +, sub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (double, +, -, nadd, VF_MULOP_BODY_X16) +DEF_VF_MULOP_CASE_1 (double, -, -, nsub, VF_MULOP_BODY_X16) +DEF_VF_MULOP_ACC_CASE_1 (double, +, +, acc, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (double, -, +, sac, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (double, +, -, nacc, VF_MULOP_ACC_BODY_X128) +DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac, VF_MULOP_ACC_BODY_X128) + +/* { dg-final { scan-assembler {vfmadd.vf} } } */ +/* { dg-final { scan-assembler {vfmsub.vf} } } */ +/* { dg-final { scan-assembler {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler {vfmacc.vf} } } */ +/* { dg-final { scan-assembler {vfmsac.vf} } } */ +/* { dg-final { scan-assembler {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler {vfnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c new file mode 100644 index 0000000..559df6c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf-3-f16.c" + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler {fcvt.s.h} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c new file mode 100644 index 0000000..03f9c5a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf-3-f32.c" + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */ +/* { dg-final { scan-assembler {fcvt.d.s} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c new file mode 100644 index 0000000..d71bdde --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=fpr2vr-cost=4" } */ + +#include "vf-3-f64.c" + +/* { dg-final { scan-assembler-not {vfmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmadd.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsub.vf} } } */ +/* { dg-final { scan-assembler-not {vfmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfmsac.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmacc.vf} } } */ +/* { dg-final { scan-assembler-not {vfnmsac.vf} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h new file mode 100644 index 0000000..b1a324f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop.h @@ -0,0 +1,162 @@ +#ifndef HAVE_DEFINED_VF_MULOP_H +#define HAVE_DEFINED_VF_MULOP_H + +#include <stdint.h> + +#define DEF_VF_MULOP_CASE_0(T, OP, NEG, NAME) \ + void test_vf_mulop_##NAME##_##T##_case_0 (T *restrict out, T *restrict in, \ + T f, unsigned n) \ + { \ + for (unsigned i = 0; i < n; i++) \ + out[i] = NEG (f * out[i] OP in[i]); \ + } +#define DEF_VF_MULOP_CASE_0_WRAP(T, OP, NEG, NAME) \ + DEF_VF_MULOP_CASE_0 (T, OP, NEG, NAME) +#define RUN_VF_MULOP_CASE_0(T, NAME, out, in, x, n) \ + test_vf_mulop_##NAME##_##T##_case_0(out, in, x, n) +#define RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) \ + RUN_VF_MULOP_CASE_0(T, NAME, out, in, x, n) + +#define DEF_VF_MULOP_ACC_CASE_0(T, OP, NEG, NAME) \ + T test_vf_mulop_acc_##NAME##_##T##_case_0 (T *restrict out, T *restrict in, \ + T f, unsigned n) \ + { \ + unsigned i; \ + for (i = 0; i < n; i++) \ + out[i] = NEG (f * in[i] OP out[i]); \ + /* Ensure that we get acc rather than add by reusing the multiplicand. */ \ + return in[i - 1]; \ + } +#define DEF_VF_MULOP_ACC_CASE_0_WRAP(T, OP, NEG, NAME) \ + DEF_VF_MULOP_ACC_CASE_0 (T, OP, NEG, NAME) +#define RUN_VF_MULOP_ACC_CASE_0(T, NAME, out, in, x, n) \ + test_vf_mulop_acc_##NAME##_##T##_case_0 (out, in, x, n) +#define RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, out, in, x, n) \ + RUN_VF_MULOP_ACC_CASE_0 (T, NAME, out, in, x, n) + +#define DEF_VF_MULOP_WIDEN_CASE_0(T1, T2, OP, NEG, NAME) \ + void test_vf_mulop_widen_##NAME##_##T1##_case_0 (T2 *restrict out, \ + T1 *restrict in, \ + T1 *restrict f, unsigned n) \ + { \ + for (unsigned i = 0; i < n; i++) \ + out[i] = NEG ((T2) * f * (T2) in[i] OP out[i]); \ + } +#define DEF_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, OP, NEG, NAME) \ + DEF_VF_MULOP_WIDEN_CASE_0 (T1, T2, OP, NEG, NAME) +#define RUN_VF_MULOP_WIDEN_CASE_0(T1, T2, NAME, out, in, x, n) \ + test_vf_mulop_widen_##NAME##_##T1##_case_0 (out, in, x, n) +#define RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, x, n) \ + RUN_VF_MULOP_WIDEN_CASE_0 (T1, T2, NAME, out, in, x, n) + +#define VF_MULOP_BODY(op, neg) \ + out[k + 0] = neg (tmp * out[k + 0] op in[k + 0]); \ + out[k + 1] = neg (tmp * out[k + 1] op in[k + 1]); \ + k += 2; + +#define VF_MULOP_BODY_X4(op, neg) \ + VF_MULOP_BODY (op, neg) \ + VF_MULOP_BODY (op, neg) + +#define VF_MULOP_BODY_X8(op, neg) \ + VF_MULOP_BODY_X4 (op, neg) \ + VF_MULOP_BODY_X4 (op, neg) + +#define VF_MULOP_BODY_X16(op, neg) \ + VF_MULOP_BODY_X8 (op, neg) \ + VF_MULOP_BODY_X8 (op, neg) + +#define VF_MULOP_BODY_X32(op, neg) \ + VF_MULOP_BODY_X16 (op, neg) \ + VF_MULOP_BODY_X16 (op, neg) + +#define VF_MULOP_BODY_X64(op, neg) \ + VF_MULOP_BODY_X32 (op, neg) \ + VF_MULOP_BODY_X32 (op, neg) + +#define VF_MULOP_BODY_X128(op, neg) \ + VF_MULOP_BODY_X64 (op, neg) \ + VF_MULOP_BODY_X64 (op, neg) + +#define DEF_VF_MULOP_CASE_1(T, OP, NEG, NAME, BODY) \ + void test_vf_mulop_##NAME##_##T##_case_1 (T *restrict out, T *restrict in, \ + T x, unsigned n) \ + { \ + unsigned k = 0; \ + T tmp = x + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp * 0x3f; \ + BODY (OP, NEG) \ + } \ + } +#define DEF_VF_MULOP_CASE_1_WRAP(T, OP, NEG, NAME, BODY) \ + DEF_VF_MULOP_CASE_1 (T, OP, NEG, NAME, BODY) + +#define VF_MULOP_ACC_BODY(op, neg) \ + out[k + 0] = neg (tmp * in[k + 0] op out[k + 1]); \ + out[k + 1] = neg (tmp * in[k + 1] op out[k + 1]); \ + k += 2; + +#define VF_MULOP_ACC_BODY_X4(op, neg) \ + VF_MULOP_ACC_BODY (op, neg) \ + VF_MULOP_ACC_BODY (op, neg) + +#define VF_MULOP_ACC_BODY_X8(op, neg) \ + VF_MULOP_ACC_BODY_X4 (op, neg) \ + VF_MULOP_ACC_BODY_X4 (op, neg) + +#define VF_MULOP_ACC_BODY_X16(op, neg) \ + VF_MULOP_ACC_BODY_X8 (op, neg) \ + VF_MULOP_ACC_BODY_X8 (op, neg) + +#define VF_MULOP_ACC_BODY_X32(op, neg) \ + VF_MULOP_ACC_BODY_X16 (op, neg) \ + VF_MULOP_ACC_BODY_X16 (op, neg) + +#define VF_MULOP_ACC_BODY_X64(op, neg) \ + VF_MULOP_ACC_BODY_X32 (op, neg) \ + VF_MULOP_ACC_BODY_X32 (op, neg) + +#define VF_MULOP_ACC_BODY_X128(op, neg) \ + VF_MULOP_ACC_BODY_X64 (op, neg) \ + VF_MULOP_ACC_BODY_X64 (op, neg) + +#define VF_MULOP_ACC_BODY_X256(op, neg) \ + VF_MULOP_ACC_BODY_X128 (op, neg) \ + VF_MULOP_ACC_BODY_X128 (op, neg) + +#define DEF_VF_MULOP_ACC_CASE_1(T, OP, NEG, NAME, BODY) \ + void test_vf_mulop_acc_##NAME##_##T##_case_1 (T *restrict out, \ + T *restrict in, T x, \ + unsigned n) \ + { \ + unsigned k = 0; \ + T tmp = x + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp * 0x3f; \ + BODY (OP, NEG) \ + } \ + } +#define DEF_VF_MULOP_ACC_CASE_1_WRAP(T, OP, NEG, NAME, BODY) \ + DEF_VF_MULOP_ACC_CASE_1 (T, OP, NEG, NAME, BODY) + +#define DEF_VF_MULOP_WIDEN_CASE_1(TYPE1, TYPE2, OP, NEG, NAME) \ + void test_vf_mulop_widen_##NAME##_##TYPE1##_##TYPE2##_case_1 ( \ + TYPE2 *__restrict dst, TYPE2 *__restrict dst2, TYPE2 *__restrict dst3, \ + TYPE2 *__restrict dst4, TYPE1 *__restrict a, TYPE1 *__restrict b, \ + TYPE1 *__restrict a2, TYPE1 *__restrict b2, int n) \ + { \ + for (int i = 0; i < n; i++) \ + { \ + dst[i] = NEG ((TYPE2) * a * (TYPE2) b[i] OP dst[i]); \ + dst2[i] = NEG ((TYPE2) * a2 * (TYPE2) b[i] OP dst2[i]); \ + dst3[i] = NEG ((TYPE2) * a2 * (TYPE2) a[i] OP dst3[i]); \ + dst4[i] = NEG ((TYPE2) * a * (TYPE2) b2[i] OP dst4[i]); \ + } \ + } + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_data.h new file mode 100644 index 0000000..ffa3d28 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_data.h @@ -0,0 +1,815 @@ +#ifndef HAVE_DEFINED_VF_MULOP_DATA_H +#define HAVE_DEFINED_VF_MULOP_DATA_H + +#define N 16 + +#define TEST_MULOP_DATA(T, NAME) test_##T##_##NAME##_data +#define TEST_MULOP_DATA_WRAP(T, NAME) TEST_MULOP_DATA(T, NAME) + + +_Float16 TEST_MULOP_DATA(_Float16, add)[][4][N] = +{ + { + { 0.30f16 }, + { + 1.48f16, 1.48f16, 1.48f16, 1.48f16, + 0.80f16, 0.80f16, 0.80f16, 0.80f16, + 0.62f16, 0.62f16, 0.62f16, 0.62f16, + 1.18f16, 1.18f16, 1.18f16, 1.18f16, + }, + { + 1.25f16, 1.25f16, 1.25f16, 1.25f16, + 1.89f16, 1.89f16, 1.89f16, 1.89f16, + 1.57f16, 1.57f16, 1.57f16, 1.57f16, + 1.21f16, 1.21f16, 1.21f16, 1.21f16, + }, + { + 1.85f16, 1.85f16, 1.85f16, 1.85f16, + 1.37f16, 1.37f16, 1.37f16, 1.37f16, + 1.09f16, 1.09f16, 1.09f16, 1.09f16, + 1.54f16, 1.54f16, 1.54f16, 1.54f16, + } + }, + { + { -0.505f16 }, + { + -2.38f16, -2.38f16, -2.38f16, -2.38f16, + -2.06f16, -2.06f16, -2.06f16, -2.06f16, + -1.69f16, -1.69f16, -1.69f16, -1.69f16, + -1.1f16, -1.1f16, -1.1f16, -1.1f16, + }, + { + -1.77f16, -1.77f16, -1.77f16, -1.77f16, + -1.6f16, -1.6f16, -1.6f16, -1.6f16, + -1.f16, -1.f16, -1.f16, -1.f16, + -1.23f16, -1.23f16, -1.23f16, -1.23f16, + }, + { + -1.49f16, -1.49f16, -1.49f16, -1.49f16, + -1.25f16, -1.25f16, -1.25f16, -1.25f16, + -1.18f16, -1.18f16, -1.18f16, -1.18f16, + -0.479f16, -0.479f16, -0.479f16, -0.479f16, + } + }, + { + { 4.95e-04f16 }, + { + 1.4266e-05f16, 1.4266e-05f16, 1.4266e-05f16, 1.4266e-05f16, + 1.8129e-05f16, 1.8129e-05f16, 1.8129e-05f16, 1.8129e-05f16, + -8.4710e-06f16, -8.4710e-06f16, -8.4710e-06f16, -8.4710e-06f16, + 3.7876e-05f16, 3.7876e-05f16, 3.7876e-05f16, 3.7876e-05f16, + }, + { + 2.2808e-02f16, 2.2808e-02f16, 2.2808e-02f16, 2.2808e-02f16, + 3.9633e-02f16, 3.9633e-02f16, 3.9633e-02f16, 3.9633e-02f16, + 9.9657e-02f16, 9.9657e-02f16, 9.9657e-02f16, 9.9657e-02f16, + 7.7189e-02f16, 7.7189e-02f16, 7.7189e-02f16, 7.7189e-02f16, + }, + { + 2.5547e-05f16, 2.5547e-05f16, 2.5547e-05f16, 2.5547e-05f16, + 3.7732e-05f16, 3.7732e-05f16, 3.7732e-05f16, 3.7732e-05f16, + 4.0820e-05f16, 4.0820e-05f16, 4.0820e-05f16, 4.0820e-05f16, + 7.6054e-05f16, 7.6054e-05f16, 7.6054e-05f16, 7.6054e-05f16, + } + }, +}; + +float TEST_MULOP_DATA(float, add)[][4][N] = +{ + { + { 43.71f }, + { + -410.28f, -410.28f, -410.28f, -410.28f, + -276.91f, -276.91f, -276.91f, -276.91f, + -103.38f, -103.38f, -103.38f, -103.38f, + -378.24f, -378.24f, -378.24f, -378.24f, + }, + { + 9.56f, 9.56f, 9.56f, 9.56f, + 6.39f, 6.39f, 6.39f, 6.39f, + 2.40f, 2.40f, 2.40f, 2.40f, + 8.80f, 8.80f, 8.80f, 8.80f, + }, + { + 7.59f, 7.59f, 7.59f, 7.59f, + 2.40f, 2.40f, 2.40f, 2.40f, + 1.52f, 1.52f, 1.52f, 1.52f, + 6.41f, 6.41f, 6.41f, 6.41f, + } + }, + { + { 2.04f }, + { + -110.22f, -110.22f, -110.22f, -110.22f, + -25.13f, -25.13f, -25.13f, -25.13f, + -108.18f, -108.18f, -108.18f, -108.18f, + -107.14f, -107.14f, -107.14f, -107.14f, + }, + { + 64.82f, 64.82f, 64.82f, 64.82f, + 31.65f, 31.65f, 31.65f, 31.65f, + 87.32f, 87.32f, 87.32f, 87.32f, + 58.70f, 58.70f, 58.70f, 58.70f, + }, + { + 22.01f, 22.01f, 22.01f, 22.01f, + 39.44f, 39.44f, 39.44f, 39.44f, + 69.95f, 69.95f, 69.95f, 69.95f, + 12.61f, 12.61f, 12.61f, 12.61f, + } + }, + { + { 20.35f }, + { + 881.43f, 881.43f, 881.43f, 881.43f, + 3300.17f, 3300.17f, 3300.17f, 3300.17f, + 5217.85f, 5217.85f, 5217.85f, 5217.85f, + 66.57f, 66.57f, 66.57f, 66.57f, + }, + { + 64.82f, 64.82f, 64.82f, 64.82f, + 31.65f, 31.65f, 31.65f, 31.65f, + 87.32f, 87.32f, 87.32f, 87.32f, + 58.70f, 58.70f, 58.70f, 58.70f, + }, + { + 2200.52f, 2200.52f, 2200.52f, 2200.52f, + 3944.25f, 3944.25f, 3944.25f, 3944.25f, + 6994.81f, 6994.81f, 6994.81f, 6994.81f, + 1261.12f, 1261.12f, 1261.12f, 1261.12f, + } + }, +}; + +double TEST_MULOP_DATA(double, add)[][4][N] = +{ + { + { 1.16e+12 }, + { + 1.8757e+45, 1.8757e+45, 1.8757e+45, 1.8757e+45, + 7.5140e+45, 7.5140e+45, 7.5140e+45, 7.5140e+45, + 8.2069e+45, 8.2069e+45, 8.2069e+45, 8.2069e+45, + 4.9456e+45, 4.9456e+45, 4.9456e+45, 4.9456e+45, + }, + { + 9.0242e+32, 9.0242e+32, 9.0242e+32, 9.0242e+32, + 3.6908e+32, 3.6908e+32, 3.6908e+32, 3.6908e+32, + 3.9202e+32, 3.9202e+32, 3.9202e+32, 3.9202e+32, + 5.0276e+32, 5.0276e+32, 5.0276e+32, 5.0276e+32, + }, + { + 2.9201e+45, 2.9201e+45, 2.9201e+45, 2.9201e+45, + 7.9411e+45, 7.9411e+45, 7.9411e+45, 7.9411e+45, + 8.6606e+45, 8.6606e+45, 8.6606e+45, 8.6606e+45, + 5.5275e+45, 5.5275e+45, 5.5275e+45, 5.5275e+45, + } + }, + { + { -7.29e+23 }, + { + -6.4993e+65, -6.4993e+65, -6.4993e+65, -6.4993e+65, + -4.6760e+65, -4.6760e+65, -4.6760e+65, -4.6760e+65, + -8.1564e+65, -8.1564e+65, -8.1564e+65, -8.1564e+65, + -8.2899e+65, -8.2899e+65, -8.2899e+65, -8.2899e+65, + }, + { + -7.7764e+41, -7.7764e+41, -7.7764e+41, -7.7764e+41, + -1.9756e+41, -1.9756e+41, -1.9756e+41, -1.9756e+41, + -4.8980e+41, -4.8980e+41, -4.8980e+41, -4.8980e+41, + -8.1062e+41, -8.1062e+41, -8.1062e+41, -8.1062e+41, + }, + { + -8.2928e+64, -8.2928e+64, -8.2928e+64, -8.2928e+64, + -3.2356e+65, -3.2356e+65, -3.2356e+65, -3.2356e+65, + -4.5850e+65, -4.5850e+65, -4.5850e+65, -4.5850e+65, + -2.3794e+65, -2.3794e+65, -2.3794e+65, -2.3794e+65, + } + }, + { + { 2.02e-03 }, + { + -1.2191e-35, -1.2191e-35, -1.2191e-35, -1.2191e-35, + -1.0471e-36, -1.0471e-36, -1.0471e-36, -1.0471e-36, + -9.7582e-36, -9.7582e-36, -9.7582e-36, -9.7582e-36, + -2.2097e-36, -2.2097e-36, -2.2097e-36, -2.2097e-36, + }, + { + 9.7703e-33, 9.7703e-33, 9.7703e-33, 9.7703e-33, + 4.1632e-33, 4.1632e-33, 4.1632e-33, 4.1632e-33, + 8.1964e-33, 8.1964e-33, 8.1964e-33, 8.1964e-33, + 4.7314e-33, 4.7314e-33, 4.7314e-33, 4.7314e-33, + }, + { + 7.5586e-36, 7.5586e-36, 7.5586e-36, 7.5586e-36, + 7.3684e-36, 7.3684e-36, 7.3684e-36, 7.3684e-36, + 6.8101e-36, 6.8101e-36, 6.8101e-36, 6.8101e-36, + 7.3543e-36, 7.3543e-36, 7.3543e-36, 7.3543e-36, + } + }, +}; + +_Float16 TEST_MULOP_DATA(_Float16, sub)[][4][N] = +{ + { + { 5.94f16 }, + { + -20.1f16, -20.1f16, -20.1f16, -20.1f16, + -13.1f16, -13.1f16, -13.1f16, -13.1f16, + -8.92f16, -8.92f16, -8.92f16, -8.92f16, + -43.1f16, -43.1f16, -43.1f16, -43.1f16, + }, + { + 7.44f16, 7.44f16, 7.44f16, 7.44f16, + 5.9f16, 5.9f16, 5.9f16, 5.9f16, + 6.81f16, 6.81f16, 6.81f16, 6.81f16, + 9.03f16, 9.03f16, 9.03f16, 9.03f16, + }, + { + 64.2f16, 64.2f16, 64.2f16, 64.2f16, + 48.1f16, 48.1f16, 48.1f16, 48.1f16, + 49.4f16, 49.4f16, 49.4f16, 49.4f16, + 96.7f16, 96.7f16, 96.7f16, 96.7f16, + } + }, + { + { 0.0475f16 }, + { + -0.0965f16, -0.0965f16, -0.0965f16, -0.0965f16, + -0.23f16, -0.23f16, -0.23f16, -0.23f16, + -0.267f16, -0.267f16, -0.267f16, -0.267f16, + -0.455f16, -0.455f16, -0.455f16, -0.455f16, + }, + { + 0.0748f16, 0.0748f16, 0.0748f16, 0.0748f16, + 0.0372f16, 0.0372f16, 0.0372f16, 0.0372f16, + 0.0183f16, 0.0183f16, 0.0183f16, 0.0183f16, + 0.0411f16, 0.0411f16, 0.0411f16, 0.0411f16, + }, + { + 0.1f16, 0.1f16, 0.1f16, 0.1f16, + 0.232f16, 0.232f16, 0.232f16, 0.232f16, + 0.268f16, 0.268f16, 0.268f16, 0.268f16, + 0.457f16, 0.457f16, 0.457f16, 0.457f16, + } + }, + { + { 2.46e+01f16 }, + { + -1.46e+02f16, -1.46e+02f16, -1.46e+02f16, -1.46e+02f16, + 3.66e+02f16, 3.66e+02f16, 3.66e+02f16, 3.66e+02f16, + 3.47e+02f16, 3.47e+02f16, 3.47e+02f16, 3.47e+02f16, + 6.24e+02f16, 6.24e+02f16, 6.24e+02f16, 6.24e+02f16, + }, + { + 6.17e+00f16, 6.17e+00f16, 6.17e+00f16, 6.17e+00f16, + 2.46e+01f16, 2.46e+01f16, 2.46e+01f16, 2.46e+01f16, + 1.99e+01f16, 1.99e+01f16, 1.99e+01f16, 1.99e+01f16, + 3.29e+01f16, 3.29e+01f16, 3.29e+01f16, 3.29e+01f16, + }, + { + 2.97e+02f16, 2.97e+02f16, 2.97e+02f16, 2.97e+02f16, + 2.39e+02f16, 2.39e+02f16, 2.39e+02f16, 2.39e+02f16, + 1.42e+02f16, 1.42e+02f16, 1.42e+02f16, 1.42e+02f16, + 1.85e+02f16, 1.85e+02f16, 1.85e+02f16, 1.85e+02f16, + } + }, +}; + +float TEST_MULOP_DATA(float, sub)[][4][N] = +{ + { + { 5.96f }, + { + 7.74f, 7.74f, 7.74f, 7.74f, + -57.f, -57.f, -57.f, -57.f, + 32.7f, 32.7f, 32.7f, 32.7f, + 2.44f, 2.44f, 2.44f, 2.44f, + }, + { + 7.37f, 7.37f, 7.37f, 7.37f, + 5.6f, 5.6f, 5.6f, 5.6f, + 9.07f, 9.07f, 9.07f, 9.07f, + 2.87f, 2.87f, 2.87f, 2.87f, + }, + { + 36.2f, 36.2f, 36.2f, 36.2f, + 90.4f, 90.4f, 90.4f, 90.4f, + 21.3f, 21.3f, 21.3f, 21.3f, + 14.6f, 14.6f, 14.6f, 14.6f, + } + }, + { + { 3.00e-02f }, + { + -2.83e-01f, -2.83e-01f, -2.83e-01f, -2.83e-01f, + -5.37e-01f, -5.37e-01f, -5.37e-01f, -5.37e-01f, + -7.87e-01f, -7.87e-01f, -7.87e-01f, -7.87e-01f, + -3.65e-01f, -3.65e-01f, -3.65e-01f, -3.65e-01f, + }, + { + 8.84e-02f, 8.84e-02f, 8.84e-02f, 8.84e-02f, + 9.27e-02f, 9.27e-02f, 9.27e-02f, 9.27e-02f, + 6.51e-02f, 6.51e-02f, 6.51e-02f, 6.51e-02f, + 5.67e-02f, 5.67e-02f, 5.67e-02f, 5.67e-02f, + }, + { + 2.86e-01f, 2.86e-01f, 2.86e-01f, 2.86e-01f, + 5.40e-01f, 5.40e-01f, 5.40e-01f, 5.40e-01f, + 7.89e-01f, 7.89e-01f, 7.89e-01f, 7.89e-01f, + 3.67e-01f, 3.67e-01f, 3.67e-01f, 3.67e-01f, + } + }, + { + { 9.04e+01f }, + { + 2.76e+03f, 2.76e+03f, 2.76e+03f, 2.76e+03f, + 1.05e+03f, 1.05e+03f, 1.05e+03f, 1.05e+03f, + 5.17e+03f, 5.17e+03f, 5.17e+03f, 5.17e+03f, + 3.91e+03f, 3.91e+03f, 3.91e+03f, 3.91e+03f, + }, + { + 3.99e+01f, 3.99e+01f, 3.99e+01f, 3.99e+01f, + 1.38e+01f, 1.38e+01f, 1.38e+01f, 1.38e+01f, + 6.36e+01f, 6.36e+01f, 6.36e+01f, 6.36e+01f, + 4.77e+01f, 4.77e+01f, 4.77e+01f, 4.77e+01f, + }, + { + 8.39e+02f, 8.39e+02f, 8.39e+02f, 8.39e+02f, + 1.97e+02f, 1.97e+02f, 1.97e+02f, 1.97e+02f, + 5.77e+02f, 5.77e+02f, 5.77e+02f, 5.77e+02f, + 4.02e+02f, 4.02e+02f, 4.02e+02f, 4.02e+02f, + } + }, +}; + +double TEST_MULOP_DATA(double, sub)[][4][N] = +{ + { + { 1.69e+01 }, + { + 8.58e+02, 8.58e+02, 8.58e+02, 8.58e+02, + 2.87e+02, 2.87e+02, 2.87e+02, 2.87e+02, + 4.35e+02, 4.35e+02, 4.35e+02, 4.35e+02, + -6.35e+01, -6.35e+01, -6.35e+01, -6.35e+01, + }, + { + 8.02e+01, 8.02e+01, 8.02e+01, 8.02e+01, + 7.51e+01, 7.51e+01, 7.51e+01, 7.51e+01, + 5.85e+01, 5.85e+01, 5.85e+01, 5.85e+01, + 1.65e+01, 1.65e+01, 1.65e+01, 1.65e+01, + }, + { + 4.95e+02, 4.95e+02, 4.95e+02, 4.95e+02, + 9.80e+02, 9.80e+02, 9.80e+02, 9.80e+02, + 5.51e+02, 5.51e+02, 5.51e+02, 5.51e+02, + 3.42e+02, 3.42e+02, 3.42e+02, 3.42e+02, + } + }, + { + { 8.86e-10 }, + { + -8.82e-09, -8.82e-09, -8.82e-09, -8.82e-09, + -3.09e-09, -3.09e-09, -3.09e-09, -3.09e-09, + -4.87e-09, -4.87e-09, -4.87e-09, -4.87e-09, + -5.70e-09, -5.70e-09, -5.70e-09, -5.70e-09, + }, + { + 9.72e-10, 9.72e-10, 9.72e-10, 9.72e-10, + 5.78e-10, 5.78e-10, 5.78e-10, 5.78e-10, + 1.10e-10, 1.10e-10, 1.10e-10, 1.10e-10, + 4.62e-10, 4.62e-10, 4.62e-10, 4.62e-10, + }, + { + 8.82e-09, 8.82e-09, 8.82e-09, 8.82e-09, + 3.09e-09, 3.09e-09, 3.09e-09, 3.09e-09, + 4.87e-09, 4.87e-09, 4.87e-09, 4.87e-09, + 5.70e-09, 5.70e-09, 5.70e-09, 5.70e-09, + } + }, + { + { 1.09e-20 }, + { + -5.46e-19, -5.46e-19, -5.46e-19, -5.46e-19, + -2.28e-19, -2.28e-19, -2.28e-19, -2.28e-19, + -4.77e-19, -4.77e-19, -4.77e-19, -4.77e-19, + -1.76e-19, -1.76e-19, -1.76e-19, -1.76e-19, + }, + { + 5.52e-20, 5.52e-20, 5.52e-20, 5.52e-20, + 2.20e-20, 2.20e-20, 2.20e-20, 2.20e-20, + 2.97e-20, 2.97e-20, 2.97e-20, 2.97e-20, + 3.23e-20, 3.23e-20, 3.23e-20, 3.23e-20, + }, + { + 5.46e-19, 5.46e-19, 5.46e-19, 5.46e-19, + 2.28e-19, 2.28e-19, 2.28e-19, 2.28e-19, + 4.77e-19, 4.77e-19, 4.77e-19, 4.77e-19, + 1.76e-19, 1.76e-19, 1.76e-19, 1.76e-19, + } + }, +}; + +_Float16 TEST_MULOP_DATA(_Float16, nadd)[][4][N] = +{ + { + { 1.09f16 }, + { + -60.7f16, -60.7f16, -60.7f16, -60.7f16, + -25.2f16, -25.2f16, -25.2f16, -25.2f16, + -50.9f16, -50.9f16, -50.9f16, -50.9f16, + -21.1f16, -21.1f16, -21.1f16, -21.1f16, + }, + { + 5.52f16, 5.52f16, 5.52f16, 5.52f16, + 2.2f16, 2.2f16, 2.2f16, 2.2f16, + 2.97f16, 2.97f16, 2.97f16, 2.97f16, + 3.23f16, 3.23f16, 3.23f16, 3.23f16, + }, + { + 54.6f16, 54.6f16, 54.6f16, 54.6f16, + 22.8f16, 22.8f16, 22.8f16, 22.8f16, + 47.7f16, 47.7f16, 47.7f16, 47.7f16, + 17.6f16, 17.6f16, 17.6f16, 17.6f16, + } + }, + { + { 0.794f16 }, + { + -6.8f16, -6.8f16, -6.8f16, -6.8f16, + -6.1f16, -6.1f16, -6.1f16, -6.1f16, + -3.02f16, -3.02f16, -3.02f16, -3.02f16, + -3.15f16, -3.15f16, -3.15f16, -3.15f16, + }, + { + 0.119f16, 0.119f16, 0.119f16, 0.119f16, + 0.774f16, 0.774f16, 0.774f16, 0.774f16, + 0.302f16, 0.302f16, 0.302f16, 0.302f16, + 0.784f16, 0.784f16, 0.784f16, 0.784f16, + }, + { + 6.7f16, 6.7f16, 6.7f16, 6.7f16, + 5.49f16, 5.49f16, 5.49f16, 5.49f16, + 2.78f16, 2.78f16, 2.78f16, 2.78f16, + 2.52f16, 2.52f16, 2.52f16, 2.52f16, + } + }, + { + { -2.62f16 }, + { + 48.6f16, 48.6f16, 48.6f16, 48.6f16, + 28.1f16, 28.1f16, 28.1f16, 28.1f16, + -2.93f16, -2.93f16, -2.93f16, -2.93f16, + 80.6f16, 80.6f16, 80.6f16, 80.6f16, + }, + { + -1.18f16, -1.18f16, -1.18f16, -1.18f16, + -7.52f16, -7.52f16, -7.52f16, -7.52f16, + -5.37f16, -5.37f16, -5.37f16, -5.37f16, + -5.39f16, -5.39f16, -5.39f16, -5.39f16, + }, + { + -51.7f16, -51.7f16, -51.7f16, -51.7f16, + -47.8f16, -47.8f16, -47.8f16, -47.8f16, + -11.2f16, -11.2f16, -11.2f16, -11.2f16, + -94.8f16, -94.8f16, -94.8f16, -94.8f16, + } + }, +}; + +float TEST_MULOP_DATA(float, nadd)[][4][N] = +{ + { + { 1.19f }, + { + -21.4f, -21.4f, -21.4f, -21.4f, + -9.12f, -9.12f, -9.12f, -9.12f, + -51.1f, -51.1f, -51.1f, -51.1f, + -48.8f, -48.8f, -48.8f, -48.8f, + }, + { + 3.83f, 3.83f, 3.83f, 3.83f, + 2.9f, 2.9f, 2.9f, 2.9f, + 4.63f, 4.63f, 4.63f, 4.63f, + 0.65f, 0.65f, 0.65f, 0.65f, + }, + { + 16.8f, 16.8f, 16.8f, 16.8f, + 5.66f, 5.66f, 5.66f, 5.66f, + 45.5f, 45.5f, 45.5f, 45.5f, + 48.1f, 48.1f, 48.1f, 48.1f, + } + }, + { + { 1.60e+01f }, + { + -2.69e+02f, -2.69e+02f, -2.69e+02f, -2.69e+02f, + -5.05e+02f, -5.05e+02f, -5.05e+02f, -5.05e+02f, + -2.92e+02f, -2.92e+02f, -2.92e+02f, -2.92e+02f, + -3.91e+02f, -3.91e+02f, -3.91e+02f, -3.91e+02f, + }, + { + 6.28e+00f, 6.28e+00f, 6.28e+00f, 6.28e+00f, + 1.94e+01f, 1.94e+01f, 1.94e+01f, 1.94e+01f, + 1.02e+01f, 1.02e+01f, 1.02e+01f, 1.02e+01f, + 1.60e+01f, 1.60e+01f, 1.60e+01f, 1.60e+01f, + }, + { + 1.68e+02f, 1.68e+02f, 1.68e+02f, 1.68e+02f, + 1.95e+02f, 1.95e+02f, 1.95e+02f, 1.95e+02f, + 1.30e+02f, 1.30e+02f, 1.30e+02f, 1.30e+02f, + 1.35e+02f, 1.35e+02f, 1.35e+02f, 1.35e+02f, + } + }, + { + { -5.63e+01f }, + { + -3.59e+03f, -3.59e+03f, -3.59e+03f, -3.59e+03f, + -2.25e+02f, -2.25e+02f, -2.25e+02f, -2.25e+02f, + -4.85e+03f, -4.85e+03f, -4.85e+03f, -4.85e+03f, + -1.59e+03f, -1.59e+03f, -1.59e+03f, -1.59e+03f, + }, + { + -7.96e+01f, -7.96e+01f, -7.96e+01f, -7.96e+01f, + -1.07e+01f, -1.07e+01f, -1.07e+01f, -1.07e+01f, + -9.62e+01f, -9.62e+01f, -9.62e+01f, -9.62e+01f, + -3.86e+01f, -3.86e+01f, -3.86e+01f, -3.86e+01f, + }, + { + -8.83e+02f, -8.83e+02f, -8.83e+02f, -8.83e+02f, + -3.79e+02f, -3.79e+02f, -3.79e+02f, -3.79e+02f, + -5.62e+02f, -5.62e+02f, -5.62e+02f, -5.62e+02f, + -5.85e+02f, -5.85e+02f, -5.85e+02f, -5.85e+02f, + } + }, +}; + +double TEST_MULOP_DATA(double, nadd)[][4][N] = +{ + { + { 8.64e+20 }, + { + -2.89e+41, -2.89e+41, -2.89e+41, -2.89e+41, + -6.50e+41, -6.50e+41, -6.50e+41, -6.50e+41, + -8.11e+41, -8.11e+41, -8.11e+41, -8.11e+41, + -4.44e+41, -4.44e+41, -4.44e+41, -4.44e+41, + }, + { + 2.61e+20, 2.61e+20, 2.61e+20, 2.61e+20, + 4.25e+20, 4.25e+20, 4.25e+20, 4.25e+20, + 5.77e+20, 5.77e+20, 5.77e+20, 5.77e+20, + 3.74e+20, 3.74e+20, 3.74e+20, 3.74e+20, + }, + { + 6.38e+40, 6.38e+40, 6.38e+40, 6.38e+40, + 2.83e+41, 2.83e+41, 2.83e+41, 2.83e+41, + 3.13e+41, 3.13e+41, 3.13e+41, 3.13e+41, + 1.21e+41, 1.21e+41, 1.21e+41, 1.21e+41, + } + }, + { + { -3.01e+40 }, + { + -7.27e+81, -7.27e+81, -7.27e+81, -7.27e+81, + -4.10e+81, -4.10e+81, -4.10e+81, -4.10e+81, + -7.82e+81, -7.82e+81, -7.82e+81, -7.82e+81, + -1.54e+81, -1.54e+81, -1.54e+81, -1.54e+81, + }, + { + -5.71e+40, -5.71e+40, -5.71e+40, -5.71e+40, + -1.41e+40, -1.41e+40, -1.41e+40, -1.41e+40, + -3.01e+40, -3.01e+40, -3.01e+40, -3.01e+40, + -2.47e+40, -2.47e+40, -2.47e+40, -2.47e+40, + }, + { + 5.55e+81, 5.55e+81, 5.55e+81, 5.55e+81, + 3.67e+81, 3.67e+81, 3.67e+81, 3.67e+81, + 6.92e+81, 6.92e+81, 6.92e+81, 6.92e+81, + 7.96e+80, 7.96e+80, 7.96e+80, 7.96e+80, + } + }, + { + { 3.65e-20 }, + { + -4.11e-39, -4.11e-39, -4.11e-39, -4.11e-39, + -8.48e-39, -8.48e-39, -8.48e-39, -8.48e-39, + -8.93e-39, -8.93e-39, -8.93e-39, -8.93e-39, + -2.74e-39, -2.74e-39, -2.74e-39, -2.74e-39, + }, + { + 5.78e-20, 5.78e-20, 5.78e-20, 5.78e-20, + 1.61e-20, 1.61e-20, 1.61e-20, 1.61e-20, + 6.91e-20, 6.91e-20, 6.91e-20, 6.91e-20, + 6.18e-20, 6.18e-20, 6.18e-20, 6.18e-20, + }, + { + 2.00e-39, 2.00e-39, 2.00e-39, 2.00e-39, + 7.89e-39, 7.89e-39, 7.89e-39, 7.89e-39, + 6.41e-39, 6.41e-39, 6.41e-39, 6.41e-39, + 4.87e-40, 4.87e-40, 4.87e-40, 4.87e-40, + } + }, +}; + +_Float16 TEST_MULOP_DATA(_Float16, nsub)[][4][N] = +{ + { + { 0.676f16 }, + { + 1.39f16, 1.39f16, 1.39f16, 1.39f16, + 1.68f16, 1.68f16, 1.68f16, 1.68f16, + 1.63f16, 1.63f16, 1.63f16, 1.63f16, + 2.12f16, 2.12f16, 2.12f16, 2.12f16, + }, + { + 1.04f16, 1.04f16, 1.04f16, 1.04f16, + 1.64f16, 1.64f16, 1.64f16, 1.64f16, + 1.95f16, 1.95f16, 1.95f16, 1.95f16, + 1.39f16, 1.39f16, 1.39f16, 1.39f16, + }, + { + 0.687f16, 0.687f16, 0.687f16, 0.687f16, + 0.568f16, 0.568f16, 0.568f16, 0.568f16, + 0.315f16, 0.315f16, 0.315f16, 0.315f16, + 1.18f16, 1.18f16, 1.18f16, 1.18f16, + } +}, + { + { -0.324f16 }, + { + -0.679f16, -0.679f16, -0.679f16, -0.679f16, + -0.992f16, -0.992f16, -0.992f16, -0.992f16, + -1.34f16, -1.34f16, -1.34f16, -1.34f16, + -0.297f16, -0.297f16, -0.297f16, -0.297f16, + }, + { + -1.96f16, -1.96f16, -1.96f16, -1.96f16, + -1.36f16, -1.36f16, -1.36f16, -1.36f16, + -1.05f16, -1.05f16, -1.05f16, -1.05f16, + -1.61f16, -1.61f16, -1.61f16, -1.61f16, + }, + { + -1.31f16, -1.31f16, -1.31f16, -1.31f16, + -1.43f16, -1.43f16, -1.43f16, -1.43f16, + -1.68f16, -1.68f16, -1.68f16, -1.68f16, + -0.82f16, -0.82f16, -0.82f16, -0.82f16, + } + }, + { + { 7.08e+01f16 }, + { + 4.49e+03f16, 4.49e+03f16, 4.49e+03f16, 4.49e+03f16, + 7.73e+03f16, 7.73e+03f16, 7.73e+03f16, 7.73e+03f16, + 8.42e+03f16, 8.42e+03f16, 8.42e+03f16, 8.42e+03f16, + 9.12e+03f16, 9.12e+03f16, 9.12e+03f16, 9.12e+03f16, + }, + { + 1.40e+01f16, 1.40e+01f16, 1.40e+01f16, 1.40e+01f16, + 6.80e+01f16, 6.80e+01f16, 6.80e+01f16, 6.80e+01f16, + 9.54e+01f16, 9.54e+01f16, 9.54e+01f16, 9.54e+01f16, + 4.49e+01f16, 4.49e+01f16, 4.49e+01f16, 4.49e+01f16, + }, + { + 3.50e+03f16, 3.50e+03f16, 3.50e+03f16, 3.50e+03f16, + 2.91e+03f16, 2.91e+03f16, 2.91e+03f16, 2.91e+03f16, + 1.66e+03f16, 1.66e+03f16, 1.66e+03f16, 1.66e+03f16, + 5.94e+03f16, 5.94e+03f16, 5.94e+03f16, 5.94e+03f16, + } + }, +}; + +float TEST_MULOP_DATA(float, nsub)[][4][N] = +{ + { + {8.51f }, + { + 24.21f, 24.21f, 24.21f, 24.21f, + 40.31f, 40.31f, 40.31f, 40.31f, + 59.68f, 59.68f, 59.68f, 59.68f, + 45.42f, 45.42f, 45.42f, 45.42f, + }, + { + 1.94f, 1.94f, 1.94f, 1.94f, + 4.24f, 4.24f, 4.24f, 4.24f, + 6.48f, 6.48f, 6.48f, 6.48f, + 4.68f, 4.68f, 4.68f, 4.68f, + }, + { + 7.70f, 7.70f, 7.70f, 7.70f, + 4.23f, 4.23f, 4.23f, 4.23f, + 4.54f, 4.54f, 4.54f, 4.54f, + 5.59f, 5.59f, 5.59f, 5.59f, + }, +}, + { + { 85.14f }, + { + 1731.29f, 1731.29f, 1731.29f, 1731.29f, + 3656.53f, 3656.53f, 3656.53f, 3656.53f, + 5565.07f, 5565.07f, 5565.07f, 5565.07f, + 4042.14f, 4042.14f, 4042.14f, 4042.14f, + }, + { + 19.43f, 19.43f, 19.43f, 19.43f, + 42.45f, 42.45f, 42.45f, 42.45f, + 64.83f, 64.83f, 64.83f, 64.83f, + 46.82f, 46.82f, 46.82f, 46.82f, + }, + { + 77.02f, 77.02f, 77.02f, 77.02f, + 42.34f, 42.34f, 42.34f, 42.34f, + 45.44f, 45.44f, 45.44f, 45.44f, + 55.89f, 55.89f, 55.89f, 55.89f, + } + }, + { + { 99.01f }, + { + 6240.43f, 6240.43f, 6240.43f, 6240.43f, + 2179.23f, 2179.23f, 2179.23f, 2179.23f, + 5346.65f, 5346.65f, 5346.65f, 5346.65f, + 2649.91f, 2649.91f, 2649.91f, 2649.91f, + }, + { + 59.46f, 59.46f, 59.46f, 59.46f, + 16.96f, 16.96f, 16.96f, 16.96f, + 52.55f, 52.55f, 52.55f, 52.55f, + 24.70f, 24.70f, 24.70f, 24.70f, + }, + { + 353.30f, 353.30f, 353.30f, 353.30f, + 500.02f, 500.02f, 500.02f, 500.02f, + 143.67f, 143.67f, 143.67f, 143.67f, + 204.36f, 204.36f, 204.36f, 204.36f, + } + }, +}; + +double TEST_MULOP_DATA(double, nsub)[][4][N] = +{ + { + { 80.54 }, + { + 5731.60, 5731.60, 5731.60, 5731.60, + 6682.41, 6682.41, 6682.41, 6682.41, + 7737.53, 7737.53, 7737.53, 7737.53, + 4922.68, 4922.68, 4922.68, 4922.68, + }, + { + 67.14, 67.14, 67.14, 67.14, + 78.23, 78.23, 78.23, 78.23, + 94.35, 94.35, 94.35, 94.35, + 49.68, 49.68, 49.68, 49.68, + }, + { + 324.14, 324.14, 324.14, 324.14, + 381.77, 381.77, 381.77, 381.77, + 138.58, 138.58, 138.58, 138.58, + 921.45, 921.45, 921.45, 921.45, + } + }, + { + { 8.05e+01 }, + { + 8.65e+27, 8.65e+27, 8.65e+27, 8.65e+27, + 1.01e+28, 1.01e+28, 1.01e+28, 1.01e+28, + 8.99e+27, 8.99e+27, 8.99e+27, 8.99e+27, + 1.32e+28, 1.32e+28, 1.32e+28, 1.32e+28, + }, + { + 6.71e+25, 6.71e+25, 6.71e+25, 6.71e+25, + 7.82e+25, 7.82e+25, 7.82e+25, 7.82e+25, + 9.44e+25, 9.44e+25, 9.44e+25, 9.44e+25, + 4.97e+25, 4.97e+25, 4.97e+25, 4.97e+25, + }, + { + 3.24e+27, 3.24e+27, 3.24e+27, 3.24e+27, + 3.82e+27, 3.82e+27, 3.82e+27, 3.82e+27, + 1.39e+27, 1.39e+27, 1.39e+27, 1.39e+27, + 9.21e+27, 9.21e+27, 9.21e+27, 9.21e+27, + } + }, + { + { 2.02e-03 }, + { + 2.7308e-35, 2.7308e-35, 2.7308e-35, 2.7308e-35, + 1.5784e-35, 1.5784e-35, 1.5784e-35, 1.5784e-35, + 2.3378e-35, 2.3378e-35, 2.3378e-35, 2.3378e-35, + 1.6918e-35, 1.6918e-35, 1.6918e-35, 1.6918e-35, + }, + { + 9.7703e-33, 9.7703e-33, 9.7703e-33, 9.7703e-33, + 4.1632e-33, 4.1632e-33, 4.1632e-33, 4.1632e-33, + 8.1964e-33, 8.1964e-33, 8.1964e-33, 8.1964e-33, + 4.7314e-33, 4.7314e-33, 4.7314e-33, 4.7314e-33, + }, + { + 7.5586e-36, 7.5586e-36, 7.5586e-36, 7.5586e-36, + 7.3684e-36, 7.3684e-36, 7.3684e-36, 7.3684e-36, + 6.8101e-36, 6.8101e-36, 6.8101e-36, 6.8101e-36, + 7.3543e-36, 7.3543e-36, 7.3543e-36, 7.3543e-36, + } + }, +}; + + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h new file mode 100644 index 0000000..3dadfab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_run.h @@ -0,0 +1,39 @@ +#ifndef HAVE_DEFINED_VF_MULOP_RUN_H +#define HAVE_DEFINED_VF_MULOP_RUN_H + +#include <math.h> + +#define TYPE_FABS(x, T) \ + (__builtin_types_compatible_p (T, double) ? fabs (x) : fabsf (x)) + +#define MAX_RELATIVE_DIFF(T) \ + (__builtin_types_compatible_p (T, _Float16) ? 0.1f : \ + (__builtin_types_compatible_p (T, float) ? 0.01f : 0.01)) + +int +main () +{ + unsigned i, k; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + T f = TEST_DATA[i][0][0]; + T *b = TEST_DATA[i][1]; + T *c = TEST_DATA[i][2]; + T *expect = TEST_DATA[i][3]; + + TEST_RUN (T, NAME, c, b, f, N); + + for (k = 0; k < N; k++) + { + T diff = expect[k] - TEST_OUT[k]; + if (TYPE_FABS (diff, T) + > MAX_RELATIVE_DIFF (T) * TYPE_FABS (expect[k], T)) + __builtin_abort (); + } + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h new file mode 100644 index 0000000..9f95fbb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_mulop_widen_run.h @@ -0,0 +1,32 @@ +#ifndef HAVE_DEFINED_VF_MULOP_WIDEN_RUN_H +#define HAVE_DEFINED_VF_MULOP_WIDEN_RUN_H + +#include <assert.h> + +#define N 512 + +int main () +{ + T1 f[N]; + T1 in[N]; + T2 out[N]; + T2 out2[N]; + + for (int i = 0; i < N; i++) + { + f[i] = LIMIT + i % 8723; + in[i] = LIMIT + i & 1964; + out[i] = LIMIT + i & 628; + out2[i] = LIMIT + i & 628; + asm volatile ("" ::: "memory"); + } + + TEST_RUN (T1, T2, NAME, out, in, f, N); + + for (int i = 0; i < N; i++) + assert (out[i] == NEG(((T2) *f * (T2) in[i]) OP out2[i])); + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c new file mode 100644 index 0000000..fd8aa30 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME add + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f32.c new file mode 100644 index 0000000..357c4ff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME add + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f64.c new file mode 100644 index 0000000..0da46be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME add + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c new file mode 100644 index 0000000..8fd8552 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME add + +DEF_VF_MULOP_CASE_0_WRAP (T, +, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c new file mode 100644 index 0000000..ed9bd36 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME add + +DEF_VF_MULOP_CASE_0_WRAP (T, +, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c new file mode 100644 index 0000000..b0883df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME add + +DEF_VF_MULOP_CASE_0_WRAP (T, +, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c new file mode 100644 index 0000000..e91fd15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME sub + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f32.c new file mode 100644 index 0000000..3f03e11 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME sub + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f64.c new file mode 100644 index 0000000..0df8d3a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME sub + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c new file mode 100644 index 0000000..ca7e0db --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME sub + +DEF_VF_MULOP_CASE_0_WRAP (T, -, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c new file mode 100644 index 0000000..d3cd3c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME sub + +DEF_VF_MULOP_CASE_0_WRAP (T, -, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c new file mode 100644 index 0000000..0d615da --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME sub + +DEF_VF_MULOP_CASE_0_WRAP (T, -, +, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c new file mode 100644 index 0000000..b38e800 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME nadd + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f32.c new file mode 100644 index 0000000..b97cdc2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME nadd + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f64.c new file mode 100644 index 0000000..8da279f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME nadd + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, +, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c new file mode 100644 index 0000000..fef5d77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME nadd + +DEF_VF_MULOP_CASE_0_WRAP(T, +, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f32.c new file mode 100644 index 0000000..38d4f7d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME nadd + +DEF_VF_MULOP_CASE_0_WRAP (T, +, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f64.c new file mode 100644 index 0000000..dc9d3a05 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME nadd + +DEF_VF_MULOP_CASE_0_WRAP (T, +, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c new file mode 100644 index 0000000..7951d40 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME nsub + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f32.c new file mode 100644 index 0000000..be1084a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME nsub + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f64.c new file mode 100644 index 0000000..73b5a6e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME nsub + +DEF_VF_MULOP_ACC_CASE_0_WRAP (T, -, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, c, b, x, n) RUN_VF_MULOP_ACC_CASE_0_WRAP(T, NAME, b, c, x, n) +#define TEST_OUT b + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c new file mode 100644 index 0000000..d0def86 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c @@ -0,0 +1,20 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T _Float16 +#define NAME nsub + +DEF_VF_MULOP_CASE_0_WRAP (T, -, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f32.c new file mode 100644 index 0000000..3cbeea9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T float +#define NAME nsub + +DEF_VF_MULOP_CASE_0_WRAP (T, -, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f64.c new file mode 100644 index 0000000..00ead93 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" +#include "vf_mulop_data.h" + +#define T double +#define NAME nsub + +DEF_VF_MULOP_CASE_0_WRAP (T, -, -, NAME) + +#define TEST_DATA TEST_MULOP_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VF_MULOP_CASE_0_WRAP(T, NAME, out, in, x, n) +#define TEST_OUT c + +#include "vf_mulop_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c new file mode 100644 index 0000000..d4c527a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c @@ -0,0 +1,21 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME acc +#define OP + +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c new file mode 100644 index 0000000..1af5240 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME acc +#define OP + +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c new file mode 100644 index 0000000..abce2f2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c @@ -0,0 +1,21 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME sac +#define OP - +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c new file mode 100644 index 0000000..13617a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME sac +#define OP - +#define NEG + + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c new file mode 100644 index 0000000..ddf49d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c @@ -0,0 +1,21 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME nacc +#define OP + +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c new file mode 100644 index 0000000..851c335 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME nacc +#define OP + +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c new file mode 100644 index 0000000..a874991 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c @@ -0,0 +1,21 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-require-effective-target riscv_zvfh } */ +/* { dg-add-options "riscv_v" } */ +/* { dg-add-options "riscv_zvfh" } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 _Float16 +#define T2 float +#define NAME nsac +#define OP - +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -32768 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c new file mode 100644 index 0000000..9eacace --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "--param=fpr2vr-cost=0" } */ + +#include "vf_mulop.h" + +#define T1 float +#define T2 double +#define NAME nsac +#define OP - +#define NEG - + +DEF_VF_MULOP_WIDEN_CASE_0_WRAP (T1, T2, OP, NEG, NAME) + +#define TEST_RUN(T1, T2, NAME, out, in, f, n) RUN_VF_MULOP_WIDEN_CASE_0_WRAP(T1, T2, NAME, out, in, f, n) +#define LIMIT -2147483648 + +#include "vf_mulop_widen_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c new file mode 100644 index 0000000..4e1a575 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int16_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmax.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c new file mode 100644 index 0000000..4c4f72d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int32_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmax.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c new file mode 100644 index 0000000..abf62c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int64_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmax.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 { target { no-opts + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c new file mode 100644 index 0000000..7744bcb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int8_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdiv.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrem.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmax.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vmin.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c new file mode 100644 index 0000000..cb62e0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint16_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vremu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c new file mode 100644 index 0000000..e2a5dbb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint32_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vremu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c new file mode 100644 index 0000000..8e7a788 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint64_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vremu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 2 { target { no-opts { + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c new file mode 100644 index 0000000..d213c18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint8_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vand.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vxor.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vdivu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vremu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmaxu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vminu.vx} 2 } } */ +/* { dg-final { scan-assembler-times {vsaddu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c new file mode 100644 index 0000000..05801a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int16_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c new file mode 100644 index 0000000..f05f091 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int32_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c new file mode 100644 index 0000000..adf9ccb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int64_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c new file mode 100644 index 0000000..8b3f5bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int8_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c new file mode 100644 index 0000000..365e650 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint16_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c new file mode 100644 index 0000000..c8fd42a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint32_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c new file mode 100644 index 0000000..bdb76b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint64_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c new file mode 100644 index 0000000..fc9c101 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint8_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c new file mode 100644 index 0000000..741f431 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int16_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c new file mode 100644 index 0000000..1741c22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int32_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c new file mode 100644 index 0000000..d326357 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int64_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c new file mode 100644 index 0000000..3137dc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T int8_t + +TEST_BINARY_VX_SIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c new file mode 100644 index 0000000..121daeb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T uint16_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c new file mode 100644 index 0000000..9616e7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T uint32_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c new file mode 100644 index 0000000..cf985f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T uint64_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c new file mode 100644 index 0000000..3bb382d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d --param=gpr2vr-cost=15" } */ + +#include "vx_binary.h" + +#define T uint8_t + +TEST_BINARY_VX_UNSIGNED_0(T) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c new file mode 100644 index 0000000..2ae4804 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int16_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=scalable -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c new file mode 100644 index 0000000..88cfc72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i32.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int32_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c new file mode 100644 index 0000000..6b29a72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i64.c @@ -0,0 +1,42 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int64_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { no-opts { + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c new file mode 100644 index 0000000..f862eb7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i8.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T int8_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c new file mode 100644 index 0000000..3ecfce6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint16_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c new file mode 100644 index 0000000..7ce1fe8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint32_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c new file mode 100644 index 0000000..c84a30c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u64.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint64_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} { target { no-opts { + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c new file mode 100644 index 0000000..9f3d7df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" + +#define T uint8_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c new file mode 100644 index 0000000..df6872c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i16.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int16_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X8) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c new file mode 100644 index 0000000..05ed639 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i32.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int32_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { no-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c new file mode 100644 index 0000000..6776b1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i64.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int64_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler-not {vaadd.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c new file mode 100644 index 0000000..d3e2785 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-i8.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T int8_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { no-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c new file mode 100644 index 0000000..5497b5a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u16.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint16_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X8) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c new file mode 100644 index 0000000..3a8e85f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint32_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c new file mode 100644 index 0000000..060d591 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u64.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint64_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c new file mode 100644 index 0000000..86a6c45 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=1" } */ + +#include "vx_binary.h" + +#define T uint8_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c new file mode 100644 index 0000000..0bfa2cb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i16.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T int16_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X8) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X8); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c new file mode 100644 index 0000000..3e3acfc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i32.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T int32_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c new file mode 100644 index 0000000..531c119 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i64.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T int64_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler-not {vdiv.vx} } } */ +/* { dg-final { scan-assembler-not {vrem.vx} } } */ +/* { dg-final { scan-assembler-not {vmax.vx} } } */ +/* { dg-final { scan-assembler-not {vmin.vx} } } */ +/* { dg-final { scan-assembler-not {vsadd.vx} } } */ +/* { dg-final { scan-assembler-not {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c new file mode 100644 index 0000000..43246bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-i8.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T int8_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1(T, -, rsub, VX_BINARY_REVERSE_BODY_X16); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, *, mul, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_S_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vmul.vx} } } */ +/* { dg-final { scan-assembler {vdiv.vx} } } */ +/* { dg-final { scan-assembler {vrem.vx} } } */ +/* { dg-final { scan-assembler {vmax.vx} } } */ +/* { dg-final { scan-assembler {vmin.vx} } } */ +/* { dg-final { scan-assembler {vsadd.vx} } } */ +/* { dg-final { scan-assembler {vssub.vx} } } */ +/* { dg-final { scan-assembler {vaadd.vx} { target { any-opts { + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m1" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m2" + "-mrvv-vector-bits=zvl -mrvv-max-lmul=m4" + } } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c new file mode 100644 index 0000000..f51e7a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u16.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T uint16_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X8) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X8); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c new file mode 100644 index 0000000..79b7477 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u32.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T uint32_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X4) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X4); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X4) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X4) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c new file mode 100644 index 0000000..ac5fd69 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u64.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T uint64_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY) + +/* { dg-final { scan-assembler-not {vadd.vx} } } */ +/* { dg-final { scan-assembler-not {vsub.vx} } } */ +/* { dg-final { scan-assembler-not {vrsub.vx} } } */ +/* { dg-final { scan-assembler-not {vand.vx} } } */ +/* { dg-final { scan-assembler-not {vor.vx} } } */ +/* { dg-final { scan-assembler-not {vxor.vx} } } */ +/* { dg-final { scan-assembler-not {vdivu.vx} } } */ +/* { dg-final { scan-assembler-not {vremu.vx} } } */ +/* { dg-final { scan-assembler-not {vmaxu.vx} } } */ +/* { dg-final { scan-assembler-not {vminu.vx} } } */ +/* { dg-final { scan-assembler-not {vsaddu.vx} } } */ +/* { dg-final { scan-assembler-not {vssubu.vx} } } */ +/* { dg-final { scan-assembler-not {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c new file mode 100644 index 0000000..84aa06b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-6-u8.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d --param=gpr2vr-cost=2" } */ + +#include "vx_binary.h" + +#define T uint8_t + +DEF_VX_BINARY_CASE_1_WRAP(T, +, add, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, -, sub, VX_BINARY_BODY_X16) +DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, -, rsub, VX_BINARY_REVERSE_BODY_X16); +DEF_VX_BINARY_CASE_1_WRAP(T, &, and, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, |, or, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, ^, xor, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, /, div, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_1_WRAP(T, %, rem, VX_BINARY_BODY_X16) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_0_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MAX_FUNC_1_WARP(T), max, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_0_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, MIN_FUNC_1_WARP(T), min, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_ADD_FUNC_WRAP(T), sat_add, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, SAT_U_SUB_FUNC_WRAP(T), sat_sub, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor, VX_BINARY_FUNC_BODY_X8) +DEF_VX_BINARY_CASE_3_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil, VX_BINARY_FUNC_BODY_X8) + +/* { dg-final { scan-assembler {vadd.vx} } } */ +/* { dg-final { scan-assembler {vsub.vx} } } */ +/* { dg-final { scan-assembler {vrsub.vx} } } */ +/* { dg-final { scan-assembler {vand.vx} } } */ +/* { dg-final { scan-assembler {vor.vx} } } */ +/* { dg-final { scan-assembler {vxor.vx} } } */ +/* { dg-final { scan-assembler {vdivu.vx} } } */ +/* { dg-final { scan-assembler {vremu.vx} } } */ +/* { dg-final { scan-assembler {vmaxu.vx} } } */ +/* { dg-final { scan-assembler {vminu.vx} } } */ +/* { dg-final { scan-assembler {vsaddu.vx} } } */ +/* { dg-final { scan-assembler {vssubu.vx} } } */ +/* { dg-final { scan-assembler {vaaddu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i16.c new file mode 100644 index 0000000..2b87321 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 8 + +#include "vx-fixed-vxrm.h" + +#define VT vint16m1_t +#define T int16_t +#define ELEM_SIZE 16 +#define SUFFIX i16 +#define FUNC __riscv_vaadd_vv_i16m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i32.c new file mode 100644 index 0000000..b95699b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 4 + +#include "vx-fixed-vxrm.h" + +#define VT vint32m1_t +#define T int32_t +#define ELEM_SIZE 32 +#define SUFFIX i32 +#define FUNC __riscv_vaadd_vv_i32m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i64.c new file mode 100644 index 0000000..48b6010 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i64.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 2 + +#include "vx-fixed-vxrm.h" + +#define VT vint64m1_t +#define T int64_t +#define ELEM_SIZE 64 +#define SUFFIX i64 +#define FUNC __riscv_vaadd_vv_i64m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i8.c new file mode 100644 index 0000000..d07a625 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 16 + +#include "vx-fixed-vxrm.h" + +#define VT vint8m1_t +#define T int8_t +#define ELEM_SIZE 8 +#define SUFFIX i8 +#define FUNC __riscv_vaadd_vv_i8m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaadd.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u16.c new file mode 100644 index 0000000..bd36429 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u16.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 8 + +#include "vx-fixed-vxrm.h" + +#define VT vuint16m1_t +#define T uint16_t +#define ELEM_SIZE 16 +#define SUFFIX u16 +#define FUNC __riscv_vaaddu_vv_u16m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u32.c new file mode 100644 index 0000000..f023a76 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u32.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 4 + +#include "vx-fixed-vxrm.h" + +#define VT vuint32m1_t +#define T uint32_t +#define ELEM_SIZE 32 +#define SUFFIX u32 +#define FUNC __riscv_vaaddu_vv_u32m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u64.c new file mode 100644 index 0000000..d9a37ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u64.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 2 + +#include "vx-fixed-vxrm.h" + +#define VT vuint64m1_t +#define T uint64_t +#define ELEM_SIZE 64 +#define SUFFIX u64 +#define FUNC __riscv_vaaddu_vv_u64m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u8.c new file mode 100644 index 0000000..328e5d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-u8.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -mrvv-vector-bits=zvl --param=gpr2vr-cost=0 " } */ + +#define VL 16 + +#include "vx-fixed-vxrm.h" + +#define VT vuint8m1_t +#define T uint8_t +#define ELEM_SIZE 8 +#define SUFFIX u8 +#define FUNC __riscv_vaaddu_vv_u8m1 + +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNU, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RNE, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_RDN, FUNC) +DEF_FIXED_BINARY_VX_WRAP(VT, T, ELEM_SIZE, SUFFIX, __RISCV_VXRM_ROD, FUNC) + +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,0} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,1} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,2} 1 } } */ +/* { dg-final { scan-assembler-times {csrwi\s+vxrm,3} 1 } } */ +/* { dg-final { scan-assembler-times {vaaddu.vx} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm.h new file mode 100644 index 0000000..438c7ab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm.h @@ -0,0 +1,28 @@ +#ifndef HAVE_DEFINED_VX_FIXED_VXRM_H +#define HAVE_DEFINED_VX_FIXED_VXRM_H + +#include <riscv_vector.h> + +int64_t go[VL] = {}; +int64_t ga[VL] = {}; + +#define DEF_FIXED_BINARY_VX(VT, T, ES, SX, VXRM, FUNC) \ +void __attribute__((noinline)) \ +test_fixed_binary_##VT##_##VXRM##_##FUNC##_vx () { \ + VT a = __riscv_vle##ES##_v_##SX##m1((T *)ga, VL); \ + VT b; \ + T *bp = (T *)&b; \ + \ + for (int i = 0; i < VL; i++) { \ + bp[i] = 123; \ + } \ + \ + VT d = FUNC (a, b, VXRM, VL); \ + \ + __riscv_vse##ES##_v_##SX##m1((T *)&go, d, VL); \ +} + +#define DEF_FIXED_BINARY_VX_WRAP(VT, T, ES, SX, VXRM, FUNC) \ + DEF_FIXED_BINARY_VX(VT, T, ES, SX, VXRM, FUNC) + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h new file mode 100644 index 0000000..4a9daff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -0,0 +1,432 @@ +#ifndef HAVE_DEFINED_VX_VF_BINARY_H +#define HAVE_DEFINED_VX_VF_BINARY_H + +#include <stdint.h> + +#undef HAS_INT128 + +#if __riscv_xlen == 64 +#define HAS_INT128 +typedef unsigned __int128 uint128_t; +typedef signed __int128 int128_t; +#endif + +#define DEF_VX_BINARY_CASE_0(T, OP, NAME) \ +void \ +test_vx_binary_##NAME##_##T##_case_0 (T * restrict out, T * restrict in, \ + T x, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + out[i] = in[i] OP x; \ +} +#define DEF_VX_BINARY_CASE_0_WRAP(T, OP, NAME) \ + DEF_VX_BINARY_CASE_0(T, OP, NAME) +#define RUN_VX_BINARY_CASE_0(T, NAME, out, in, x, n) \ + test_vx_binary_##NAME##_##T##_case_0(out, in, x, n) +#define RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_0(T, NAME, out, in, x, n) + +#define DEF_VX_BINARY_REVERSE_CASE_0(T, OP, NAME) \ +void \ +test_vx_binary_reverse_##NAME##_##T##_case_0 (T * restrict out, \ + T * restrict in, T x, \ + unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + out[i] = x OP in[i]; \ +} +#define DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, OP, NAME) \ + DEF_VX_BINARY_REVERSE_CASE_0(T, OP, NAME) +#define RUN_VX_BINARY_REVERSE_CASE_0(T, NAME, out, in, x, n) \ + test_vx_binary_reverse_##NAME##_##T##_case_0(out, in, x, n) +#define RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_REVERSE_CASE_0(T, NAME, out, in, x, n) + +#define VX_BINARY_BODY(op) \ + out[k + 0] = in[k + 0] op tmp; \ + out[k + 1] = in[k + 1] op tmp; \ + k += 2; + +#define VX_BINARY_BODY_X4(op) \ + VX_BINARY_BODY(op) \ + VX_BINARY_BODY(op) + +#define VX_BINARY_BODY_X8(op) \ + VX_BINARY_BODY_X4(op) \ + VX_BINARY_BODY_X4(op) + +#define VX_BINARY_BODY_X16(op) \ + VX_BINARY_BODY_X8(op) \ + VX_BINARY_BODY_X8(op) + +#define VX_BINARY_BODY_X32(op) \ + VX_BINARY_BODY_X16(op) \ + VX_BINARY_BODY_X16(op) + +#define VX_BINARY_BODY_X64(op) \ + VX_BINARY_BODY_X32(op) \ + VX_BINARY_BODY_X32(op) + +#define VX_BINARY_BODY_X128(op) \ + VX_BINARY_BODY_X64(op) \ + VX_BINARY_BODY_X64(op) + +#define DEF_VX_BINARY_CASE_1(T, OP, NAME, BODY) \ +void \ +test_vx_binary_##NAME##_##T##_case_1 (T * restrict out, T * restrict in, \ + T x, unsigned n) \ +{ \ + unsigned k = 0; \ + T tmp = x + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp ^ 0x3f; \ + BODY(OP) \ + } \ +} +#define DEF_VX_BINARY_CASE_1_WRAP(T, OP, NAME, BODY) \ + DEF_VX_BINARY_CASE_1(T, OP, NAME, BODY) + +#define VX_BINARY_REVERSE_BODY(op) \ + out[k + 0] = tmp op in[k + 0]; \ + out[k + 1] = tmp op in[k + 1]; \ + k += 2; + +#define VX_BINARY_REVERSE_BODY_X4(op) \ + VX_BINARY_REVERSE_BODY(op) \ + VX_BINARY_REVERSE_BODY(op) + +#define VX_BINARY_REVERSE_BODY_X8(op) \ + VX_BINARY_REVERSE_BODY_X4(op) \ + VX_BINARY_REVERSE_BODY_X4(op) + +#define VX_BINARY_REVERSE_BODY_X16(op) \ + VX_BINARY_REVERSE_BODY_X8(op) \ + VX_BINARY_REVERSE_BODY_X8(op) + +#define VX_BINARY_REVERSE_BODY_X32(op) \ + VX_BINARY_REVERSE_BODY_X16(op) \ + VX_BINARY_REVERSE_BODY_X16(op) + +#define VX_BINARY_REVERSE_BODY_X64(op) \ + VX_BINARY_REVERSE_BODY_X32(op) \ + VX_BINARY_REVERSE_BODY_X32(op) + +#define VX_BINARY_REVERSE_BODY_X128(op) \ + VX_BINARY_REVERSE_BODY_X64(op) \ + VX_BINARY_REVERSE_BODY_X64(op) + +#define DEF_VX_BINARY_REVERSE_CASE_1(T, OP, NAME, BODY) \ +void \ +test_vx_binary_reverse_##NAME##_##T##_case_1 (T * restrict out, \ + T * restrict in, \ + T x, unsigned n) \ +{ \ + unsigned k = 0; \ + T tmp = x + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp ^ 0x3f; \ + BODY(OP) \ + } \ +} +#define DEF_VX_BINARY_REVERSE_CASE_1_WRAP(T, OP, NAME, BODY) \ + DEF_VX_BINARY_REVERSE_CASE_1(T, OP, NAME, BODY) + +#define DEF_MAX_0(T) \ +static inline T \ +test_##T##_max_0 (T a, T b) \ +{ \ + return a > b ? a : b; \ +} + +#define DEF_MAX_1(T) \ +static inline T \ +test_##T##_max_1 (T a, T b) \ +{ \ + return a >= b ? a : b; \ +} + +DEF_MAX_0(int8_t) +DEF_MAX_0(int16_t) +DEF_MAX_0(int32_t) +DEF_MAX_0(int64_t) + +DEF_MAX_1(int8_t) +DEF_MAX_1(int16_t) +DEF_MAX_1(int32_t) +DEF_MAX_1(int64_t) + +DEF_MAX_0(uint8_t) +DEF_MAX_0(uint16_t) +DEF_MAX_0(uint32_t) +DEF_MAX_0(uint64_t) + +DEF_MAX_1(uint8_t) +DEF_MAX_1(uint16_t) +DEF_MAX_1(uint32_t) +DEF_MAX_1(uint64_t) + +#define MAX_FUNC_0(T) test_##T##_max_0 +#define MAX_FUNC_0_WARP(T) MAX_FUNC_0(T) + +#define MAX_FUNC_1(T) test_##T##_max_1 +#define MAX_FUNC_1_WARP(T) MAX_FUNC_1(T) + +#define DEF_MIN_0(T) \ +static inline T \ +test_##T##_min_0 (T a, T b) \ +{ \ + return a > b ? b : a; \ +} + +#define DEF_MIN_1(T) \ +static inline T \ +test_##T##_min_1 (T a, T b) \ +{ \ + return a >= b ? b : a; \ +} + +DEF_MIN_0(int8_t) +DEF_MIN_0(int16_t) +DEF_MIN_0(int32_t) +DEF_MIN_0(int64_t) + +DEF_MIN_1(int8_t) +DEF_MIN_1(int16_t) +DEF_MIN_1(int32_t) +DEF_MIN_1(int64_t) + +DEF_MIN_0(uint8_t) +DEF_MIN_0(uint16_t) +DEF_MIN_0(uint32_t) +DEF_MIN_0(uint64_t) + +DEF_MIN_1(uint8_t) +DEF_MIN_1(uint16_t) +DEF_MIN_1(uint32_t) +DEF_MIN_1(uint64_t) + +#define MIN_FUNC_0(T) test_##T##_min_0 +#define MIN_FUNC_0_WARP(T) MIN_FUNC_0(T) + +#define MIN_FUNC_1(T) test_##T##_min_1 +#define MIN_FUNC_1_WARP(T) MIN_FUNC_1(T) + +#define DEF_VX_BINARY_CASE_2(T, FUNC, NAME) \ +void \ +test_vx_binary_##NAME##_##FUNC##_##T##_case_2 (T * restrict out, \ + T * restrict in, \ + T x, unsigned n) \ +{ \ + for (unsigned i = 0; i < n; i++) \ + out[i] = FUNC (in[i], x); \ +} +#define DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) \ + DEF_VX_BINARY_CASE_2(T, FUNC, NAME) +#define RUN_VX_BINARY_CASE_2(T, NAME, FUNC, out, in, x, n) \ + test_vx_binary_##NAME##_##FUNC##_##T##_case_2(out, in, x, n) +#define RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) \ + RUN_VX_BINARY_CASE_2(T, NAME, FUNC, out, in, x, n) + +#define DEF_VX_BINARY_CASE_3(T, FUNC, NAME, BODY) \ +void \ +test_vx_binary_##NAME##_##FUNC##_##T##_case_3 (T * restrict out, \ + T * restrict in, \ + T x, unsigned n) \ +{ \ + unsigned k = 0; \ + T tmp = x + 3; \ + \ + while (k < n) \ + { \ + tmp = tmp ^ 0x82; \ + BODY(FUNC) \ + } \ +} +#define DEF_VX_BINARY_CASE_3_WRAP(T, FUNC, NAME, BODY) \ + DEF_VX_BINARY_CASE_3(T, FUNC, NAME, BODY) + +#define VX_BINARY_FUNC_BODY(func) \ + out[k + 0] = func (in[k + 0], tmp); \ + out[k + 1] = func (in[k + 1], tmp); \ + k += 2; + +#define VX_BINARY_FUNC_BODY_X4(op) \ + VX_BINARY_FUNC_BODY(op) \ + VX_BINARY_FUNC_BODY(op) + +#define VX_BINARY_FUNC_BODY_X8(op) \ + VX_BINARY_FUNC_BODY_X4(op) \ + VX_BINARY_FUNC_BODY_X4(op) + +#define VX_BINARY_FUNC_BODY_X16(op) \ + VX_BINARY_FUNC_BODY_X8(op) \ + VX_BINARY_FUNC_BODY_X8(op) + +#define VX_BINARY_FUNC_BODY_X32(op) \ + VX_BINARY_FUNC_BODY_X16(op) \ + VX_BINARY_FUNC_BODY_X16(op) + +#define VX_BINARY_FUNC_BODY_X64(op) \ + VX_BINARY_FUNC_BODY_X32(op) \ + VX_BINARY_FUNC_BODY_X32(op) + +#define VX_BINARY_FUNC_BODY_X128(op) \ + VX_BINARY_FUNC_BODY_X64(op) \ + VX_BINARY_FUNC_BODY_X64(op) + +#define DEF_SAT_U_ADD(T) \ +T \ +test_##T##_sat_add (T a, T b) \ +{ \ + return (a + b) | (-(T)((T)(a + b) < a)); \ +} + +DEF_SAT_U_ADD(uint8_t) +DEF_SAT_U_ADD(uint16_t) +DEF_SAT_U_ADD(uint32_t) +DEF_SAT_U_ADD(uint64_t) + +#define DEF_SAT_U_SUB(T) \ +T \ +test_##T##_sat_sub (T a, T b) \ +{ \ + return (a - b) & (-(T)(a >= b)); \ +} + +DEF_SAT_U_SUB(uint8_t) +DEF_SAT_U_SUB(uint16_t) +DEF_SAT_U_SUB(uint32_t) +DEF_SAT_U_SUB(uint64_t) + +#define DEF_SAT_S_ADD(T, UT, MIN, MAX) \ +T \ +test_##T##_sat_add (T x, T y) \ +{ \ + T sum = (UT)x + (UT)y; \ + return (x ^ y) < 0 \ + ? sum \ + : (sum ^ x) >= 0 \ + ? sum \ + : x < 0 ? MIN : MAX; \ +} + +DEF_SAT_S_ADD(int8_t, uint8_t, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD(int16_t, uint16_t, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD(int32_t, uint32_t, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD(int64_t, uint64_t, INT64_MIN, INT64_MAX) + +#define DEF_SAT_S_SUB(T, UT, MIN, MAX) \ +T \ +test_##T##_sat_sub (T x, T y) \ +{ \ + T minus = (UT)x - (UT)y; \ + return (x ^ y) >= 0 \ + ? minus \ + : (minus ^ x) >= 0 \ + ? minus \ + : x < 0 ? MIN : MAX; \ +} + +DEF_SAT_S_SUB(int8_t, uint8_t, INT8_MIN, INT8_MAX) +DEF_SAT_S_SUB(int16_t, uint16_t, INT16_MIN, INT16_MAX) +DEF_SAT_S_SUB(int32_t, uint32_t, INT32_MIN, INT32_MAX) +DEF_SAT_S_SUB(int64_t, uint64_t, INT64_MIN, INT64_MAX) + +#define SAT_U_ADD_FUNC(T) test_##T##_sat_add +#define SAT_U_ADD_FUNC_WRAP(T) SAT_U_ADD_FUNC(T) + +#define SAT_U_SUB_FUNC(T) test_##T##_sat_sub +#define SAT_U_SUB_FUNC_WRAP(T) SAT_U_SUB_FUNC(T) + +#define SAT_S_ADD_FUNC(T) test_##T##_sat_add +#define SAT_S_ADD_FUNC_WRAP(T) SAT_S_ADD_FUNC(T) + +#define SAT_S_SUB_FUNC(T) test_##T##_sat_sub +#define SAT_S_SUB_FUNC_WRAP(T) SAT_S_SUB_FUNC(T) + +#define DEF_AVG_FLOOR(NT, WT) \ +NT \ +test_##NT##_avg_floor(NT x, NT y) \ +{ \ + return (NT)(((WT)x + (WT)y) >> 1); \ +} + +DEF_AVG_FLOOR(uint8_t, uint16_t) +DEF_AVG_FLOOR(uint16_t, uint32_t) +DEF_AVG_FLOOR(uint32_t, uint64_t) + +DEF_AVG_FLOOR(int8_t, int16_t) +DEF_AVG_FLOOR(int16_t, int32_t) +DEF_AVG_FLOOR(int32_t, int64_t) + +#define DEF_AVG_CEIL(NT, WT) \ +NT \ +test_##NT##_avg_ceil(NT x, NT y) \ +{ \ + return (NT)(((WT)x + (WT)y + 1) >> 1); \ +} + +DEF_AVG_CEIL(uint8_t, uint16_t) +DEF_AVG_CEIL(uint16_t, uint32_t) +DEF_AVG_CEIL(uint32_t, uint64_t) + +DEF_AVG_CEIL(int8_t, int16_t) +DEF_AVG_CEIL(int16_t, int32_t) +DEF_AVG_CEIL(int32_t, int64_t) + +#ifdef HAS_INT128 + DEF_AVG_FLOOR(uint64_t, uint128_t) + DEF_AVG_FLOOR(int64_t, int128_t) + + DEF_AVG_CEIL(uint64_t, uint128_t) + DEF_AVG_CEIL(int64_t, int128_t) +#endif + +#define AVG_FLOOR_FUNC(T) test_##T##_avg_floor +#define AVG_FLOOR_FUNC_WRAP(T) AVG_FLOOR_FUNC(T) + +#define AVG_CEIL_FUNC(T) test_##T##_avg_ceil +#define AVG_CEIL_FUNC_WRAP(T) AVG_CEIL_FUNC(T) + +#define TEST_BINARY_VX_SIGNED_0(T) \ + DEF_VX_BINARY_CASE_0_WRAP(T, +, add) \ + DEF_VX_BINARY_CASE_0_WRAP(T, -, sub) \ + DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub) \ + DEF_VX_BINARY_CASE_0_WRAP(T, &, and) \ + DEF_VX_BINARY_CASE_0_WRAP(T, |, or) \ + DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) \ + DEF_VX_BINARY_CASE_0_WRAP(T, *, mul) \ + DEF_VX_BINARY_CASE_0_WRAP(T, /, div) \ + DEF_VX_BINARY_CASE_0_WRAP(T, %, rem) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_1_WARP(T), min) \ + DEF_VX_BINARY_CASE_2_WRAP(T, SAT_S_ADD_FUNC(T), sat_add) \ + DEF_VX_BINARY_CASE_2_WRAP(T, SAT_S_SUB_FUNC(T), sat_sub) \ + DEF_VX_BINARY_CASE_2_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor) \ + DEF_VX_BINARY_CASE_2_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil) \ + +#define TEST_BINARY_VX_UNSIGNED_0(T) \ + DEF_VX_BINARY_CASE_0_WRAP(T, +, add) \ + DEF_VX_BINARY_CASE_0_WRAP(T, -, sub) \ + DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub) \ + DEF_VX_BINARY_CASE_0_WRAP(T, &, and) \ + DEF_VX_BINARY_CASE_0_WRAP(T, |, or) \ + DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor) \ + DEF_VX_BINARY_CASE_0_WRAP(T, /, div) \ + DEF_VX_BINARY_CASE_0_WRAP(T, %, rem) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \ + DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_1_WARP(T), min) \ + DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_ADD_FUNC(T), sat_add) \ + DEF_VX_BINARY_CASE_2_WRAP(T, SAT_U_SUB_FUNC(T), sat_sub) \ + DEF_VX_BINARY_CASE_2_WRAP(T, AVG_FLOOR_FUNC_WRAP(T), avg_floor) \ + DEF_VX_BINARY_CASE_2_WRAP(T, AVG_CEIL_FUNC_WRAP(T), avg_ceil) \ + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h new file mode 100644 index 0000000..626347c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -0,0 +1,5693 @@ +#ifndef HAVE_DEFINED_VX_BINARY_DATA_H +#define HAVE_DEFINED_VX_BINARY_DATA_H + +#define N 16 + +#define TEST_BINARY_DATA(T, NAME) test_##T##_##NAME##_data +#define TEST_BINARY_DATA_WRAP(T, NAME) TEST_BINARY_DATA(T, NAME) + +int8_t TEST_BINARY_DATA(int8_t, add)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + }, + { + { 127 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 127, 127, 127, 127, + 126, 126, 126, 126, + -1, -1, -1, -1, + 125, 125, 125, 125, + }, + }, + { + { -128 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + -128, -128, -128, -128, + -127, -127, -127, -127, + -1, -1, -1, -1, + -126, -126, -126, -126, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, add)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + }, + { + { 32767 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 32767, 32767, 32767, 32767, + 32766, 32766, 32766, 32766, + -1, -1, -1, -1, + 32765, 32765, 32765, 32765, + }, + }, + { + { -32768 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + -1, -1, -1, -1, + -32766, -32766, -32766, -32766, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, add)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + }, + { + { 2147483647 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483646, 2147483646, 2147483646, 2147483646, + -1, -1, -1, -1, + 2147483645, 2147483645, 2147483645, 2147483645, + }, + }, + { + { -2147483648 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + -1, -1, -1, -1, + -2147483646, -2147483646, -2147483646, -2147483646, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, add)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + }, + { + { 9223372036854775807ll }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, + -1, -1, -1, -1, + 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, + }, + }, + { + { -9223372036854775808ull }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, add)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + }, + { + { 127 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 128, 128, 128, 128, + }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 254, 254, 254, 254, + 255, 255, 255, 255, + }, + }, + { + { 253 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 255, 255, 255, 255, + }, + { + 253, 253, 253, 253, + 254, 254, 254, 254, + 255, 255, 255, 255, + 252, 252, 252, 252, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, add)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + }, + { + { 32767 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + }, + }, + { + { 65533 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 65535, 65535, 65535, 65535, + }, + { + 65533, 65533, 65533, 65533, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + 65532, 65532, 65532, 65532, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, add)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + }, + { + { 2147483647 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, + { + { 4294967293 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 4294967293, 4294967293, 4294967293, 4294967293, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, add)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + }, + { + { 9223372036854775807ull }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + }, + { + { 18446744073709551613ull }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + { + 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 126, 126, 126, 126, + -1, -1, -1, -1, + 125, 125, 125, 125, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + -127, -127, -127, -127, + -1, -1, -1, -1, + -126, -126, -126, -126, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32766, 32766, 32766, 32766, + -1, -1, -1, -1, + 32765, 32765, 32765, 32765, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + -1, -1, -1, -1, + -32766, -32766, -32766, -32766, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483646, 2147483646, 2147483646, 2147483646, + -1, -1, -1, -1, + 2147483645, 2147483645, 2147483645, 2147483645, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + -1, -1, -1, -1, + -2147483646, -2147483646, -2147483646, -2147483646, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, + -1, -1, -1, -1, + 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 254, 254, 254, 254, + 255, 255, 255, 255, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 128, 128, 128, 128, + }, + }, + { + { 253 }, + { + 253, 253, 253, 253, + 254, 254, 254, 254, + 255, 255, 255, 255, + 252, 252, 252, 252, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 255, 255, 255, 255, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + }, + }, + { + { 65533 }, + { + 65533, 65533, 65533, 65533, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + 65532, 65532, 65532, 65532, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 65535, 65535, 65535, 65535, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + }, + { + { 4294967293 }, + { + 4294967293, 4294967293, 4294967293, 4294967293, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, sub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 11, 11, 11, 11, + 9, 9, 9, 9, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + }, + { + { 18446744073709551613ull }, + { + 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, rsub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 126, 126, 126, 126, + 1, 1, 1, 1, + 125, 125, 125, 125, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 126, 126, 126, 126, + 2, 2, 2, 2, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + -127, -127, -127, -127, + -1, -1, -1, -1, + -126, -126, -126, -126, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -127, -127, -127, -127, + -2, -2, -2, -2, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, rsub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32766, 32766, 32766, 32766, + 1, 1, 1, 1, + 32765, 32765, 32765, 32765, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32766, 32766, 32766, 32766, + 2, 2, 2, 2, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + -1, -1, -1, -1, + -32766, -32766, -32766, -32766, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -32767, -32767, -32767, -32767, + -2, -2, -2, -2, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, rsub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483646, 2147483646, 2147483646, 2147483646, + 1, 1, 1, 1, + 2147483645, 2147483645, 2147483645, 2147483645, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483646, 2147483646, 2147483646, 2147483646, + 2, 2, 2, 2, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + -1, -1, -1, -1, + -2147483646, -2147483646, -2147483646, -2147483646, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -2147483647, -2147483647, -2147483647, -2147483647, + -2, -2, -2, -2, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, rsub)[][3][N] = +{ + { + { 1 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 0, 0, 0, 0, + -1, -1, -1, -1, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, 9223372036854775806ll, + 1, 1, 1, 1, + 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, 9223372036854775805ll, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + 2, 2, 2, 2, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, -9223372036854775806ll, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -2, -2, -2, -2, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, rsub)[][3][N] = +{ + { + { 12 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 11, 11, 11, 11, + 10, 10, 10, 10, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 28, 28, 28, 28, + 4, 4, 4, 4, + 5, 5, 5, 5, + }, + { + 0, 0, 0, 0, + 99, 99, 99, 99, + 123, 123, 123, 123, + 122, 122, 122, 122, + }, + }, + { + { 255 }, + { + 253, 253, 253, 253, + 254, 254, 254, 254, + 255, 255, 255, 255, + 252, 252, 252, 252, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 3, 3, 3, 3, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, rsub)[][3][N] = +{ + { + { 12 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 11, 11, 11, 11, + 10, 10, 10, 10, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32768 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 4, 4, 4, 4, + 5, 5, 5, 5, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 32764, 32764, 32764, 32764, + 32763, 32763, 32763, 32763, + }, + }, + { + { 65535 }, + { + 65533, 65533, 65533, 65533, + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + 65532, 65532, 65532, 65532, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 3, 3, 3, 3, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, rsub)[][3][N] = +{ + { + { 12 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 11, 11, 11, 11, + 10, 10, 10, 10, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483648 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4, 4, 4, 4, + 5, 5, 5, 5, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2147483644, 2147483644, 2147483644, 2147483644, + 2147483643, 2147483643, 2147483643, 2147483643, + }, + }, + { + { 4294967295 }, + { + 4294967293, 4294967293, 4294967293, 4294967293, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967292, 4294967292, 4294967292, 4294967292, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 3, 3, 3, 3, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, rsub)[][3][N] = +{ + { + { 12 }, + { + 1, 1, 1, 1, + 2, 2, 2, 2, + 12, 12, 12, 12, + 10, 10, 10, 10, + }, + { + 11, 11, 11, 11, + 10, 10, 10, 10, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775808ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 4ull, 4ull, 4ull, 4ull, + 5ull, 5ull, 5ull, 5ull, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 9223372036854775804ull, 9223372036854775804ull, 9223372036854775804ull, 9223372036854775804ull, + 9223372036854775803ull, 9223372036854775803ull, 9223372036854775803ull, 9223372036854775803ull, + }, + }, + { + { 18446744073709551615ull }, + { + 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, 18446744073709551613ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, 18446744073709551612ull, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 3, 3, 3, 3, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7f }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + }, + { + { 0xff }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7fff }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + }, + { + { 0xffff }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7fffffff }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + }, + { + { 0xffffffff }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7fffffffffffffffull }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + }, + { + { 0xffffffffffffffffull }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7f }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + }, + { + { 0xff }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7fff }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + }, + { + { 0xffff }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7fffffff }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + }, + { + { 0xffffffff }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, and)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x1, 0x1, 0x1, 0x1, + }, + }, + { + { 0x7fffffffffffffffull }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x0, 0x0, 0x0, 0x0, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + }, + { + { 0xffffffffffffffffull }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xff, 0xff, 0xff, 0xff, + }, + }, + { + { 0x7f }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0xff, 0xff, 0xff, 0xff, + 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, + }, + }, + { + { 0xf0 }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xf0, 0xf0, 0xf0, 0xf0, + 0xf1, 0xf1, 0xf1, 0xf1, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + }, + { + { 0x7fff }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0xffff, 0xffff, 0xffff, 0xffff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + }, + }, + { + { 0xfff0 }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, + 0xfff0, 0xfff0, 0xfff0, 0xfff0, + 0xfff1, 0xfff1, 0xfff1, 0xfff1, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + { + { 0x7fffffff }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + }, + }, + { + { 0xfffffff0 }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0, + 0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + }, + { + { 0x7fffffffffffffffull }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + }, + }, + { + { 0xfffffffffffffff0ull }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, + 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xff, 0xff, 0xff, 0xff, + }, + }, + { + { 0x7f }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0xff, 0xff, 0xff, 0xff, + 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, + }, + }, + { + { 0xf0 }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xf0, 0xf0, 0xf0, 0xf0, + 0xf1, 0xf1, 0xf1, 0xf1, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + }, + { + { 0x7fff }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0xffff, 0xffff, 0xffff, 0xffff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + }, + }, + { + { 0xfff0 }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0xffff, 0xffff, 0xffff, 0xffff, + 0xfff0, 0xfff0, 0xfff0, 0xfff0, + 0xfff1, 0xfff1, 0xfff1, 0xfff1, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + }, + { + { 0x7fffffff }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + }, + }, + { + { 0xfffffff0 }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0, + 0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, or)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + { + 0x1, 0x1, 0x1, 0x1, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + }, + { + { 0x7fffffffffffffffull }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + }, + }, + { + { 0xfffffffffffffff0ull }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, + 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfe, 0xfe, 0xfe, 0xfe, + }, + }, + { + { 0x7f }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + 0x70, 0x70, 0x70, 0x70, + 0xf, 0xf, 0xf, 0xf, + }, + }, + { + { 0xf0 }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xef, 0xef, 0xef, 0xef, + 0x70, 0x70, 0x70, 0x70, + 0xf1, 0xf1, 0xf1, 0xf1, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfffe, 0xfffe, 0xfffe, 0xfffe, + }, + }, + { + { 0x7fff }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + 0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0, + 0x0fff, 0x0fff, 0x0fff, 0x0fff, + }, + }, + { + { 0xfff0 }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xffef, 0xffef, 0xffef, 0xffef, + 0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0, + 0xfff1, 0xfff1, 0xfff1, 0xfff1, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfffffffe, 0xfffffffe, 0xfffffffe, 0xfffffffe, + }, + }, + { + { 0x7fffffff }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, + 0xfffffff, 0xfffffff, 0xfffffff, 0xfffffff, + }, + }, + { + { 0xfffffff0 }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xffffffef, 0xffffffef, 0xffffffef, 0xffffffef, + 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, + 0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull, + }, + }, + { + { 0x7fffffffffffffffull }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, + 0xfffffffffffffffull, 0xfffffffffffffffull, 0xfffffffffffffffull, 0xfffffffffffffffull, + }, + }, + { + { 0xfffffffffffffff0ull }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull, + 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, + 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfe, 0xfe, 0xfe, 0xfe, + }, + }, + { + { 0x7f }, + { + 0x7f, 0x7f, 0x7f, 0x7f, + 0x80, 0x80, 0x80, 0x80, + 0xf, 0xf, 0xf, 0xf, + 0x70, 0x70, 0x70, 0x70, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xff, 0xff, 0xff, 0xff, + 0x70, 0x70, 0x70, 0x70, + 0xf, 0xf, 0xf, 0xf, + }, + }, + { + { 0xf0 }, + { + 0xff, 0xff, 0xff, 0xff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80, 0x80, 0x80, 0x80, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xef, 0xef, 0xef, 0xef, + 0x70, 0x70, 0x70, 0x70, + 0xf1, 0xf1, 0xf1, 0xf1, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfffe, 0xfffe, 0xfffe, 0xfffe, + }, + }, + { + { 0x7fff }, + { + 0x7fff, 0x7fff, 0x7fff, 0x7fff, + 0x8000, 0x8000, 0x8000, 0x8000, + 0xf, 0xf, 0xf, 0xf, + 0x7000, 0x7000, 0x7000, 0x7000, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xffff, 0xffff, 0xffff, 0xffff, + 0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0, + 0x0fff, 0x0fff, 0x0fff, 0x0fff, + }, + }, + { + { 0xfff0 }, + { + 0xffff, 0xffff, 0xffff, 0xffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000, 0x8000, 0x8000, 0x8000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xffef, 0xffef, 0xffef, 0xffef, + 0x7ff0, 0x7ff0, 0x7ff0, 0x7ff0, + 0xfff1, 0xfff1, 0xfff1, 0xfff1, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfffffffe, 0xfffffffe, 0xfffffffe, 0xfffffffe, + }, + }, + { + { 0x7fffffff }, + { + 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0xf, 0xf, 0xf, 0xf, + 0x70000000, 0x70000000, 0x70000000, 0x70000000, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, + 0xfffffff, 0xfffffff, 0xfffffff, 0xfffffff, + }, + }, + { + { 0xfffffff0 }, + { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x80000000, 0x80000000, 0x80000000, 0x80000000, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xffffffef, 0xffffffef, 0xffffffef, 0xffffffef, + 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, 0x7ffffff0, + 0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, xor)[][3][N] = +{ + { + { 0x1 }, + { + 0x1, 0x1, 0x1, 0x1, + 0x2, 0x2, 0x2, 0x2, + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0x3, 0x3, 0x3, 0x3, + 0x1, 0x1, 0x1, 0x1, + 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull, 0xfffffffffffffffeull, + }, + }, + { + { 0x7fffffffffffffffull }, + { + 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0xf, 0xf, 0xf, 0xf, + 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull, + }, + { + 0x0, 0x0, 0x0, 0x0, + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, + 0xfffffffffffffffull, 0xfffffffffffffffull, 0xfffffffffffffffull, 0xfffffffffffffffull, + }, + }, + { + { 0xfffffffffffffff0ull }, + { + 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull, + 0x1f, 0x1f, 0x1f, 0x1f, + 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull, + 0x1, 0x1, 0x1, 0x1, + }, + { + 0xf, 0xf, 0xf, 0xf, + 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull, 0xffffffffffffffefull, + 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, 0x7ffffffffffffff0ull, + 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, mul)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 127 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -127, -127, -127, -127, + -128, -128, -128, -128, + 2, 2, 2, 2, + }, + }, + { + { -128 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -128, -128, -128, -128, + -128, -128, -128, -128, + 0, 0, 0, 0, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, mul)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 32767 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -32767, -32767, -32767, -32767, + -32768, -32768, -32768, -32768, + 2, 2, 2, 2, + }, + }, + { + { -32768 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + 0, 0, 0, 0, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, mul)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 2147483647 }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -2147483647, -2147483647, -2147483647, -2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + 2, 2, 2, 2, + }, + }, + { + { -2147483648 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + 0, 0, 0, 0, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, mul)[][3][N] = +{ + { + { 1 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 9223372036854775807ll }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, -9223372036854775807ll, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 2, 2, 2, 2, + }, + }, + { + { -9223372036854775808ull }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 0, 0, 0, 0, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, div)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, div)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, div)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, div)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, div)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 4, 4, 4, 4, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + 3, 3, 3, 3, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 1, 1, 1, 1, + 128, 128, 128, 128, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, + { + { 128 }, + { + 127, 127, 127, 127, + 255, 255, 255, 255, + 128, 128, 128, 128, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, div)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 4, 4, 4, 4, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + 3, 3, 3, 3, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 1, 1, 1, 1, + 32768, 32768, 32768, 32768, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, + { + { 32768 }, + { + 32767, 32767, 32767, 32767, + 65535, 65535, 65535, 65535, + 32768, 32768, 32768, 32768, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, div)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 4, 4, 4, 4, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + 3, 3, 3, 3, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 1, 1, 1, 1, + 2147483648, 2147483648, 2147483648, 2147483648, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, + { + { 2147483648 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483648, 2147483648, 2147483648, 2147483648, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, div)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 4, 4, 4, 4, + 7, 7, 7, 7, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + 3, 3, 3, 3, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 1, 1, 1, 1, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 2, 2, 2, 2, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, + { + { 9223372036854775808ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + -1, -1, -1, -1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 1, 1, 1, 1, + 128, 128, 128, 128, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 128 }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 127, 127, 127, 127, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 1, 1, 1, 1, + 32768, 32768, 32768, 32768, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 32768 }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 1, 1, 1, 1, + 2147483648, 2147483648, 2147483648, 2147483648, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 2147483648 }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, rem)[][3][N] = +{ + { + { 2 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 8, 8, 8, 8, + 7, 7, 7, 7, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 1, 1, 1, 1, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 1, 1, 1, 1, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 1, 1, 1, 1, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775808ull }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + 127, 127, 127, 127, + 127, 127, 127, 127, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + -128, -128, -128, -128, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 127, 127, 127, 127, + }, + }, + { + { 254 }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 254, 254, 254, 254, + 255, 255, 255, 255, + 254, 254, 254, 254, + 254, 254, 254, 254, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 32767, 32767, 32767, 32767, + }, + }, + { + { 65534 }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 65534, 65534, 65534, 65534, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + }, + { + { 4294967294 }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967294, 4294967294, 4294967294, 4294967294, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, max)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + }, + { + { 18446744073709551614ull }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + { + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + -2, -2, -2, -2, + }, + }, + { + { -128 }, + { + -128, -128, -128, -128, + 1, 1, 1, 1, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + -128, -128, -128, -128, + -128, -128, -128, -128, + -128, -128, -128, -128, + -128, -128, -128, -128, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -2, -2, -2, -2, + }, + }, + { + { -32768 }, + { + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2, -2, -2, -2, + }, + }, + { + { -2147483648 }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + -1, -1, -1, -1, + -2, -2, -2, -2, + }, + }, + { + { 9223372036854775807ll }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + { + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -2, -2, -2, -2, + }, + }, + { + { -9223372036854775808ull }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, 9223372036854775807ll, + 2, 2, 2, 2, + }, + { + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + 127, 127, 127, 127, + 1, 1, 1, 1, + }, + }, + { + { 254 }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 128, 128, 128, 128, + 254, 254, 254, 254, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 1, 1, 1, 1, + }, + }, + { + { 65534 }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 32768, 32768, 32768, 32768, + 65534, 65534, 65534, 65534, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 1, 1, 1, 1, + }, + }, + { + { 4294967294 }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967294, 4294967294, 4294967294, 4294967294, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, min)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 1, 1, 1, 1, + }, + }, + { + { 18446744073709551614ull }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 254, 254, 254, 254, + 255, 255, 255, 255, + 255, 255, 255, 255, + 128, 128, 128, 128, + }, + }, + { + { 254 }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + 255, 255, 255, 255, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 65534, 65534, 65534, 65534, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 32768, 32768, 32768, 32768, + }, + }, + { + { 65534 }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 4294967294, 4294967294, 4294967294, 4294967294, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + }, + { + { 4294967294 }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + }, + { + { 18446744073709551614ull }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + { + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, sat_sub)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 128, 128, 128, 128, + 0, 0, 0, 0, + }, + }, + { + { 254 }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 127, 127, 127, 127, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, sat_sub)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32768, 32768, 32768, 32768, + 0, 0, 0, 0, + }, + }, + { + { 65534 }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 32767, 32767, 32767, 32767, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, sat_sub)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483648, 2147483648, 2147483648, 2147483648, + 0, 0, 0, 0, + }, + }, + { + { 4294967294 }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483647, 2147483647, 2147483647, 2147483647, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, sat_sub)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 0, 0, 0, 0, + }, + }, + { + { 18446744073709551614ull }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 2, 2, 2, 2, + }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -128, -128, -128, -128, + -127, -127, -127, -127, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + 0, 0, 0, 0, + 127, 127, 127, 127, + }, + }, + { + { -128 }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + 1, 1, 1, 1, + }, + { + -1, -1, -1, -1, + -128, -128, -128, -128, + -128, -128, -128, -128, + -127, -127, -127, -127, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + 0, 0, 0, 0, + 32767, 32767, 32767, 32767, + }, + }, + { + { -32768 }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + }, + { + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + 0, 0, 0, 0, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + }, + { + { -2147483648 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + }, + { + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, sat_add)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -1, -1, -1, -1, + 0, 0, 0, 0, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + }, + { + { -9223372036854775808ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + }, + { + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, sat_sub)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 3, 3, 3, 3, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -128, -128, -128, -128, + -127, -127, -127, -127, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + -128, -128, -128, -128, + -128, -128, -128, -128, + -126, -126, -126, -126, + }, + }, + { + { -128 }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + -128, -128, -128, -128, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + 0, 0, 0, 0, + 127, 127, 127, 127, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, sat_sub)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 3, 3, 3, 3, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + -32768, -32768, -32768, -32768, + -32766, -32766, -32766, -32766, + }, + }, + { + { -32768 }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + -32768, -32768, -32768, -32768, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 0, 0, 0, 0, + 32767, 32767, 32767, 32767, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, sat_sub)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 3, 3, 3, 3, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483646, -2147483646, -2147483646, -2147483646, + }, + }, + { + { -2147483648 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + -2147483648, -2147483648, -2147483648, -2147483648, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 0, 0, 0, 0, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, sat_sub)[][3][N] = +{ + { + { 1 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + -1, -1, -1, -1, + 3, 3, 3, 3, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + 1, 1, 1, 1, + }, + { + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775806ull, -9223372036854775806ull, -9223372036854775806ull, -9223372036854775806ull, + }, + }, + { + { -9223372036854775808ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -1, -1, -1, -1, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 0, 0, 0, 0, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 127, 127, 127, 127, + 191, 191, 191, 191, + 64, 64, 64, 64, + }, + }, + { + { 255 }, + { + 0, 0, 0, 0, + 255, 255, 255, 255, + 254, 254, 254, 254, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 255, 255, 255, 255, + 254, 254, 254, 254, + 128, 128, 128, 128, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32767, 32767, 32767, 32767, + 49151, 49151, 49151, 49151, + 16384, 16384, 16384, 16384, + }, + }, + { + { 65535 }, + { + 0, 0, 0, 0, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 32768, 32768, 32768, 32768, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483647, 2147483647, 2147483647, 2147483647, + 3221225471, 3221225471, 3221225471, 3221225471, + 1073741824, 1073741824, 1073741824, 1073741824, + }, + }, + { + { 4294967295 }, + { + 0, 0, 0, 0, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, + 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, + }, + }, + { + { 18446744073709551615ull }, + { + 0, 0, 0, 0, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -128, -128, -128, -128, + -127, -127, -127, -127, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + -1, -1, -1, -1, + 0, 0, 0, 0, + 64, 64, 64, 64, + }, + }, + { + {-128 }, + { + 0, 0, 0, 0, + -128, -128, -128, -128, + 126, 126, 126, 126, + 127, 127, 127, 127, + }, + { + -64, -64, -64, -64, + -128, -128, -128, -128, + -1, -1, -1, -1, + -1, -1, -1, -1, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + -1, -1, -1, -1, + 0, 0, 0, 0, + 16384, 16384, 16384, 16384, + }, + }, + { + {-32768 }, + { + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + 32766, 32766, 32766, 32766, + 32767, 32767, 32767, 32767, + }, + { + -16384, -16384, -16384, -16384, + -32768, -32768, -32768, -32768, + -1, -1, -1, -1, + -1, -1, -1, -1, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -1, -1, -1, -1, + 0, 0, 0, 0, + 1073741824, 1073741824, 1073741824, 1073741824, + }, + }, + { + {-2147483648 }, + { + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + 2147483646, 2147483646, 2147483646, 2147483646, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + { + -1073741824, -1073741824, -1073741824, -1073741824, + -2147483648, -2147483648, -2147483648, -2147483648, + -1, -1, -1, -1, + -1, -1, -1, -1, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, avg_floor)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -1, -1, -1, -1, + 0, 0, 0, 0, + 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, + }, + }, + { + {-9223372036854775808ull }, + { + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + { + -4611686018427387904ull, -4611686018427387904ull, -4611686018427387904ull, -4611686018427387904ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -1, -1, -1, -1, + -1, -1, -1, -1, + }, + }, +}; + +uint8_t TEST_BINARY_DATA(uint8_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 255, 255, 255, 255, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 128, 128, 128, 128, + 191, 191, 191, 191, + 64, 64, 64, 64, + }, + }, + { + { 255 }, + { + 0, 0, 0, 0, + 255, 255, 255, 255, + 254, 254, 254, 254, + 1, 1, 1, 1, + }, + { + 128, 128, 128, 128, + 255, 255, 255, 255, + 255, 255, 255, 255, + 128, 128, 128, 128, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + 49151, 49151, 49151, 49151, + 16384, 16384, 16384, 16384, + }, + }, + { + { 65535 }, + { + 0, 0, 0, 0, + 65535, 65535, 65535, 65535, + 65534, 65534, 65534, 65534, + 1, 1, 1, 1, + }, + { + 32768, 32768, 32768, 32768, + 65535, 65535, 65535, 65535, + 65535, 65535, 65535, 65535, + 32768, 32768, 32768, 32768, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + 3221225471, 3221225471, 3221225471, 3221225471, + 1073741824, 1073741824, 1073741824, 1073741824, + }, + }, + { + { 4294967295 }, + { + 0, 0, 0, 0, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967294, 4294967294, 4294967294, 4294967294, + 1, 1, 1, 1, + }, + { + 2147483648, 2147483648, 2147483648, 2147483648, + 4294967295, 4294967295, 4294967295, 4294967295, + 4294967295, 4294967295, 4294967295, 4294967295, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, 13835058055282163711ull, + 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, + }, + }, + { + { 18446744073709551615ull }, + { + 0, 0, 0, 0, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, 18446744073709551614ull, + 1, 1, 1, 1, + }, + { + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + }, +}; + +int8_t TEST_BINARY_DATA(int8_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 127 }, + { + 127, 127, 127, 127, + -128, -128, -128, -128, + -127, -127, -127, -127, + 1, 1, 1, 1, + }, + { + 127, 127, 127, 127, + 0, 0, 0, 0, + 0, 0, 0, 0, + 64, 64, 64, 64, + }, + }, + { + {-128 }, + { + 0, 0, 0, 0, + -128, -128, -128, -128, + 126, 126, 126, 126, + 127, 127, 127, 127, + }, + { + -64, -64, -64, -64, + -128, -128, -128, -128, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int16_t TEST_BINARY_DATA(int16_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 32767 }, + { + 32767, 32767, 32767, 32767, + -32768, -32768, -32768, -32768, + -32767, -32767, -32767, -32767, + 1, 1, 1, 1, + }, + { + 32767, 32767, 32767, 32767, + 0, 0, 0, 0, + 0, 0, 0, 0, + 16384, 16384, 16384, 16384, + }, + }, + { + {-32768 }, + { + 0, 0, 0, 0, + -32768, -32768, -32768, -32768, + 32766, 32766, 32766, 32766, + 32767, 32767, 32767, 32767, + }, + { + -16384, -16384, -16384, -16384, + -32768, -32768, -32768, -32768, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int32_t TEST_BINARY_DATA(int32_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 2147483647 }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + -2147483648, -2147483648, -2147483648, -2147483648, + -2147483647, -2147483647, -2147483647, -2147483647, + 1, 1, 1, 1, + }, + { + 2147483647, 2147483647, 2147483647, 2147483647, + 0, 0, 0, 0, + 0, 0, 0, 0, + 1073741824, 1073741824, 1073741824, 1073741824, + }, + }, + { + {-2147483648 }, + { + 0, 0, 0, 0, + -2147483648, -2147483648, -2147483648, -2147483648, + 2147483646, 2147483646, 2147483646, 2147483646, + 2147483647, 2147483647, 2147483647, 2147483647, + }, + { + -1073741824, -1073741824, -1073741824, -1073741824, + -2147483648, -2147483648, -2147483648, -2147483648, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +int64_t TEST_BINARY_DATA(int64_t, avg_ceil)[][3][N] = +{ + { + { 0 }, + { + 2, 2, 2, 2, + 1, 1, 1, 1, + 0, 0, 0, 0, + 4, 4, 4, 4, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + 2, 2, 2, 2, + }, + }, + { + { 9223372036854775807ull }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, -9223372036854775807ull, + 1, 1, 1, 1, + }, + { + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 0, 0, 0, 0, + 0, 0, 0, 0, + 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, 4611686018427387904ull, + }, + }, + { + {-9223372036854775808ull }, + { + 0, 0, 0, 0, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, 9223372036854775806ull, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + }, + { + -4611686018427387904ull, -4611686018427387904ull, -4611686018427387904ull, -4611686018427387904ull, + -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, -9223372036854775808ull, + -1, -1, -1, -1, + 0, 0, 0, 0, + }, + }, +}; + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h new file mode 100644 index 0000000..3c00dbb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_run.h @@ -0,0 +1,26 @@ +#ifndef HAVE_DEFINED_VX_BINARY_RUN_H +#define HAVE_DEFINED_VX_BINARY_RUN_H + +int +main () +{ + unsigned i, k; + T out[N]; + + for (i = 0; i < sizeof (TEST_DATA) / sizeof (TEST_DATA[0]); i++) + { + T x = TEST_DATA[i][0][0]; + T *in = TEST_DATA[i][1]; + T *expect = TEST_DATA[i][2]; + + TEST_RUN (T, NAME, out, in, x, N); + + for (k = 0; k < N; k++) + if (out[k] != expect[k]) + __builtin_abort (); + } + + return 0; +} + +#endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i16.c new file mode 100644 index 0000000..0307b3f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i32.c new file mode 100644 index 0000000..d73325b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i64.c new file mode 100644 index 0000000..481774b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i8.c new file mode 100644 index 0000000..7de89ee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u16.c new file mode 100644 index 0000000..73d1a57 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u32.c new file mode 100644 index 0000000..60a7aa4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u64.c new file mode 100644 index 0000000..803bcba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u8.c new file mode 100644 index 0000000..f28147b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME avg_floor +#define FUNC AVG_FLOOR_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i16.c new file mode 100644 index 0000000..8def643 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i32.c new file mode 100644 index 0000000..d9ca67d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i64.c new file mode 100644 index 0000000..313109a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i8.c new file mode 100644 index 0000000..47e4a5d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u16.c new file mode 100644 index 0000000..6297672 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u32.c new file mode 100644 index 0000000..30db24b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u64.c new file mode 100644 index 0000000..db3c911 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v && rv64 } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u8.c new file mode 100644 index 0000000..a7755f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-2-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME avg_ceil +#define FUNC AVG_CEIL_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c new file mode 100644 index 0000000..ac7bd2e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME add + +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c new file mode 100644 index 0000000..1e8b78f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME add + +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c new file mode 100644 index 0000000..e2e352e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME add + +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c new file mode 100644 index 0000000..8a197e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME add + +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c new file mode 100644 index 0000000..b616f39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME add + +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c new file mode 100644 index 0000000..bf0449c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME add + +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c new file mode 100644 index 0000000..2611892 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME add + +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c new file mode 100644 index 0000000..60cfe7b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME add + +DEF_VX_BINARY_CASE_0_WRAP(T, +, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c new file mode 100644 index 0000000..a6a7db8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c new file mode 100644 index 0000000..79b7569 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c new file mode 100644 index 0000000..a80d8d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c new file mode 100644 index 0000000..d0c6f4c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c new file mode 100644 index 0000000..44bbaec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c new file mode 100644 index 0000000..d634a1a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c new file mode 100644 index 0000000..10816c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c new file mode 100644 index 0000000..f275016 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vand-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME and + +DEF_VX_BINARY_CASE_0_WRAP(T, &, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i16.c new file mode 100644 index 0000000..64cf31c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i32.c new file mode 100644 index 0000000..2fe6623 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i64.c new file mode 100644 index 0000000..03dbe03 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i8.c new file mode 100644 index 0000000..e54e5bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u16.c new file mode 100644 index 0000000..afb848d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u32.c new file mode 100644 index 0000000..4acaa5b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u64.c new file mode 100644 index 0000000..335a909 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u8.c new file mode 100644 index 0000000..160d362 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vdiv-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME div + +DEF_VX_BINARY_CASE_0_WRAP(T, /, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i16.c new file mode 100644 index 0000000..d36495c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i32.c new file mode 100644 index 0000000..acd8aeb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i64.c new file mode 100644 index 0000000..5ecc206 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i8.c new file mode 100644 index 0000000..5ac63e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u16.c new file mode 100644 index 0000000..ebe3f09 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u32.c new file mode 100644 index 0000000..ceec03b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u64.c new file mode 100644 index 0000000..8657253 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u8.c new file mode 100644 index 0000000..aefc72a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-1-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME max +#define FUNC MAX_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i16.c new file mode 100644 index 0000000..77445b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i32.c new file mode 100644 index 0000000..fc4fb55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i64.c new file mode 100644 index 0000000..1afa12e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i8.c new file mode 100644 index 0000000..9c1222b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u16.c new file mode 100644 index 0000000..4617f07 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u32.c new file mode 100644 index 0000000..f0302e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u64.c new file mode 100644 index 0000000..a82cfc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u8.c new file mode 100644 index 0000000..8199ccd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmax-run-2-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME max +#define FUNC MAX_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, max) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i16.c new file mode 100644 index 0000000..180c82bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i32.c new file mode 100644 index 0000000..980b63c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i64.c new file mode 100644 index 0000000..26fae23 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i8.c new file mode 100644 index 0000000..c5c14a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u16.c new file mode 100644 index 0000000..5295bb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u32.c new file mode 100644 index 0000000..1e09610 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u64.c new file mode 100644 index 0000000..ed757e6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u8.c new file mode 100644 index 0000000..dd4b93a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-1-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME min +#define FUNC MIN_FUNC_0_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i16.c new file mode 100644 index 0000000..bfdabeb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i32.c new file mode 100644 index 0000000..af34049 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i64.c new file mode 100644 index 0000000..013bd83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i8.c new file mode 100644 index 0000000..0f4fd2d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u16.c new file mode 100644 index 0000000..5e450d85 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u32.c new file mode 100644 index 0000000..45bfd12 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u64.c new file mode 100644 index 0000000..46f0031 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u8.c new file mode 100644 index 0000000..971404b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmin-run-2-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME min +#define FUNC MIN_FUNC_1_WARP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i16.c new file mode 100644 index 0000000..c6be0ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME mul + +DEF_VX_BINARY_CASE_0_WRAP(T, *, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i32.c new file mode 100644 index 0000000..3c78042 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME mul + +DEF_VX_BINARY_CASE_0_WRAP(T, *, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i64.c new file mode 100644 index 0000000..63925d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME mul + +DEF_VX_BINARY_CASE_0_WRAP(T, *, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i8.c new file mode 100644 index 0000000..69962f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME mul + +DEF_VX_BINARY_CASE_0_WRAP(T, *, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c new file mode 100644 index 0000000..0a11aad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c new file mode 100644 index 0000000..759ad2b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c new file mode 100644 index 0000000..1b3007c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c new file mode 100644 index 0000000..b060744 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c new file mode 100644 index 0000000..0dc8bee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c new file mode 100644 index 0000000..8bc2528 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c new file mode 100644 index 0000000..d286bdf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c new file mode 100644 index 0000000..dba4338 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME or + +DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c new file mode 100644 index 0000000..4320789 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c new file mode 100644 index 0000000..43a001b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c new file mode 100644 index 0000000..2e9b43a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c new file mode 100644 index 0000000..d4185c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u16.c new file mode 100644 index 0000000..46e74f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u32.c new file mode 100644 index 0000000..94e3613 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u64.c new file mode 100644 index 0000000..566a1a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u8.c new file mode 100644 index 0000000..1532079 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrem-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME rem + +DEF_VX_BINARY_CASE_0_WRAP(T, %, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i16.c new file mode 100644 index 0000000..65ce6a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i32.c new file mode 100644 index 0000000..170779c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i64.c new file mode 100644 index 0000000..796cfdf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i8.c new file mode 100644 index 0000000..0419e59 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u16.c new file mode 100644 index 0000000..bf9f6ce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u32.c new file mode 100644 index 0000000..afe037d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u64.c new file mode 100644 index 0000000..5d4c01e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u8.c new file mode 100644 index 0000000..43d785f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vrsub-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME rsub + +DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_REVERSE_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i16.c new file mode 100644 index 0000000..1f0fd46 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME sat_add +#define FUNC SAT_S_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i32.c new file mode 100644 index 0000000..4a8df0c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME sat_add +#define FUNC SAT_S_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i64.c new file mode 100644 index 0000000..534cd25 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME sat_add +#define FUNC SAT_S_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i8.c new file mode 100644 index 0000000..de2a9b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME sat_add +#define FUNC SAT_S_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u16.c new file mode 100644 index 0000000..e1531b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME sat_add +#define FUNC SAT_U_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u32.c new file mode 100644 index 0000000..4aa7143 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME sat_add +#define FUNC SAT_U_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u64.c new file mode 100644 index 0000000..30992c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME sat_add +#define FUNC SAT_U_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u8.c new file mode 100644 index 0000000..c6852a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsadd-run-1-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME sat_add +#define FUNC SAT_U_ADD_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i16.c new file mode 100644 index 0000000..bd985c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME sat_sub +#define FUNC SAT_S_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i32.c new file mode 100644 index 0000000..c510ea0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME sat_sub +#define FUNC SAT_S_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i64.c new file mode 100644 index 0000000..b82278d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME sat_sub +#define FUNC SAT_S_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i8.c new file mode 100644 index 0000000..5fae704 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-i8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME sat_sub +#define FUNC SAT_S_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u16.c new file mode 100644 index 0000000..f0293a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u16.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME sat_sub +#define FUNC SAT_U_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u32.c new file mode 100644 index 0000000..34e1493 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u32.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME sat_sub +#define FUNC SAT_U_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u64.c new file mode 100644 index 0000000..65800b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u64.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME sat_sub +#define FUNC SAT_U_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u8.c new file mode 100644 index 0000000..f09843a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vssub-run-1-u8.c @@ -0,0 +1,17 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME sat_sub +#define FUNC SAT_U_SUB_FUNC_WRAP(T) +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) + +DEF_VX_BINARY_CASE_2_WRAP(T, FUNC, NAME) + +#define TEST_RUN(T, NAME, out, in, x, n) \ + RUN_VX_BINARY_CASE_2_WRAP(T, NAME, FUNC, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c new file mode 100644 index 0000000..e28f954 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c new file mode 100644 index 0000000..032ecad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c new file mode 100644 index 0000000..19bbe2d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c new file mode 100644 index 0000000..7063a9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c new file mode 100644 index 0000000..42a1508 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c new file mode 100644 index 0000000..2df5b14 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c new file mode 100644 index 0000000..c4f7e54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c new file mode 100644 index 0000000..869380a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME sub + +DEF_VX_BINARY_CASE_0_WRAP(T, -, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c new file mode 100644 index 0000000..8441720 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int16_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c new file mode 100644 index 0000000..cdb773f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c new file mode 100644 index 0000000..8618b9e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int64_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c new file mode 100644 index 0000000..13724ce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-i8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int8_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c new file mode 100644 index 0000000..e6030f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c new file mode 100644 index 0000000..cdb773f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T int32_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c new file mode 100644 index 0000000..44f0fff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c new file mode 100644 index 0000000..2e983e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vxor-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME xor + +DEF_VX_BINARY_CASE_0_WRAP(T, ^, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c index 5880ccc..a5224e7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv32gcv.c @@ -3,9 +3,6 @@ #include "vec-avg-template.h" -/* { dg-final { scan-assembler-times {\tvwadd\.vv} 6 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 3 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 3 } } */ -/* { dg-final { scan-assembler-times {\tvadd\.vi} 3 } } */ -/* { dg-final { scan-assembler-times {\tvnsra.wi} 6 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 6 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c index 916f33d..32446ae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/widen/vec-avg-rv64gcv.c @@ -3,9 +3,6 @@ #include "vec-avg-template.h" -/* { dg-final { scan-assembler-times {\tvwadd\.vv} 6 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*0} 3 } } */ -/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 3 } } */ -/* { dg-final { scan-assembler-times {\tvadd\.vi} 3 } } */ -/* { dg-final { scan-assembler-times {\tvnsra\.wi} 6 } } */ +/* { dg-final { scan-assembler-times {csrwi\s*vxrm,\s*2} 6 } } */ /* { dg-final { scan-assembler-times {vaaddu\.vv} 6 } } */ +/* { dg-final { scan-assembler-times {vaadd\.vv} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/crc-builtin-zvbc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/crc-builtin-zvbc.c new file mode 100644 index 0000000..2d5fa88 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/crc-builtin-zvbc.c @@ -0,0 +1,66 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvbc -mabi=lp64d" } */ + +#include <stdint-gcc.h> + +int8_t crc8_data8 () +{ + return __builtin_crc8_data8 (0x34, 'a', 0x12); +} + +int16_t crc16_data8 () +{ + return __builtin_crc16_data8 (0x1234, 'a', 0x1021); +} + +int16_t crc16_data16 () +{ + return __builtin_crc16_data16 (0x1234, 0x3214, 0x1021); +} + +int32_t crc32_data8 () +{ + return __builtin_crc32_data8 (0xffffffff, 0x32, 0x4002123); +} + +int32_t crc32_data16 () +{ + return __builtin_crc32_data16 (0xffffffff, 0x3232, 0x4002123); +} + +int32_t crc32_data32 () +{ + return __builtin_crc32_data32 (0xffffffff, 0x123546ff, 0x4002123); +} + +int8_t rev_crc8_data8 () +{ + return __builtin_rev_crc8_data8 (0x34, 'a', 0x12); +} + +int16_t rev_crc16_data8 () +{ + return __builtin_rev_crc16_data8 (0x1234, 'a', 0x1021); +} + +int16_t rev_crc16_data16 () +{ + return __builtin_rev_crc16_data16 (0x1234, 0x3214, 0x1021); +} + +int32_t rev_crc32_data8 () +{ + return __builtin_rev_crc32_data8 (0xffffffff, 0x32, 0x4002123); +} + +int32_t rev_crc32_data16 () +{ + return __builtin_rev_crc32_data16 (0xffffffff, 0x3232, 0x4002123); +} + +int32_t rev_crc32_data32 () +{ + return __builtin_rev_crc32_data32 (0xffffffff, 0x123546ff, 0x4002123); +} +/* { dg-final { scan-assembler-times "vclmul.vx" 12 } } */ +/* { dg-final { scan-assembler-times "vclmulh.vx" 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c index af89f62..3e8a980 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-49.c @@ -32,5 +32,5 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c index 5b75935..e8fc7bb 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-50.c @@ -32,5 +32,5 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c index cd23141..9828987 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-52.c @@ -32,5 +32,5 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c index fb57803..1528482 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-74.c @@ -33,7 +33,7 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, } /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 3 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c index 09067d3..186f6c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-75.c @@ -34,6 +34,6 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, /* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 1 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 1 } } */ /* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr113829.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113829.c new file mode 100644 index 0000000..48c291a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr113829.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gcv -mabi=lp64d" } */ + +#pragma riscv intrinsic "vector" +void +foo (void) +{ + __riscv_vfredosum_tu (X); /* { dg-error "undeclared" } */ + /* { dg-error "too many arguments" "" { target *-*-* } .-1 } */ +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c new file mode 100644 index 0000000..266e948 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr119164.c @@ -0,0 +1,22 @@ +/* Reduced from SPEC2017 blender: node_texture_util.c. + The conditional function call was tripping mode switching state machine */ + +/* { dg-do compile { target { rv64 && { ! riscv_abi_e } } } } */ +/* { dg-options " -Ofast -march=rv64gcv_zvl256b -ftree-vectorize -mrvv-vector-bits=zvl" } */ + +void *a; +float *b; +short c; +void d(); +void e() { + if (a) + d(); + if (c) { + b[0] = b[0] * 0.5f + 0.5f; + b[1] = b[1] * 0.5f + 0.5f; + } +} + +/* { dg-final { scan-assembler-not {frrm\s+[axs][0-9]+} } } */ +/* { dg-final { scan-assembler-not {fsrmi\s+[01234]} } } */ +/* { dg-final { scan-assembler-not {fsrm\s+[axs][0-9]+} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c new file mode 100644 index 0000000..d22091e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr120436.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O0" } */ + +/* Use -O0 as otherwise the unused intrinsics get + optimized away. We used to ICE here instead of + emitting an error. */ + +#include "riscv_vector.h" + +void +clean_subreg (int32_t *in, int32_t *out, size_t m) /* { dg-error {this operation requires the RVV ISA extension} } */ +{ + vint16m8_t v24, v8, v16; + vint32m8_t result = __riscv_vle32_v_i32m8 (in, 32); /* { dg-error {built-in function '__riscv_vle32_v_i32m8\(in, 32\)' requires the 'v' ISA extension} } */ + vint32m1_t v0 = __riscv_vget_v_i32m8_i32m1 (result, 0); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c index 04dec7b..4f6785a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-5.c @@ -6,9 +6,9 @@ /* ** foo: -** addi\t[a-x0-9]+,\s*[a-x0-9]+,100 +** ... ** vsetvli\tzero,a2,e64,m2,t[au],m[au] -** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero +** vmv.s.x\tv[0-9]+.* ** vs2r.v\tv[0-9]+,0\([a-x0-9]+\) ** ret */ @@ -23,7 +23,7 @@ void foo (void *base, void *out, size_t vl) ** foo2: ** fld\tfa[0-9]+,\s*100\(a0\) ** vsetvli\tzero,a2,e64,m2,t[au],m[au] -** vfmv\.v\.f\tv[0-9]+,\s*fa[0-9]+ +** vfmv\.s\.f\tv[0-9]+,\s*fa[0-9]+ ** vs2r.v\tv[0-9]+,0\([a-x0-9]+\) ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c index 0ebb92e..a8c9263c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-6.c @@ -23,7 +23,7 @@ void foo (void *base, void *out, size_t vl) ** foo2: ** fld\tfa[0-9]+,\s*100\(a0\) ** vsetvli\tzero,a2,e64,m2,t[au],m[au] -** vfmv\.v\.f\tv[0-9]+,\s*fa[0-9]+ +** vfmv\.s\.f\tv[0-9]+,\s*fa[0-9]+ ** vs2r.v\tv[0-9]+,0\([a-x0-9]+\) ** ret */ @@ -52,7 +52,7 @@ void foo3 (void *base, void *out, size_t vl) /* ** foo4: ** ... -** vfmv\.v\.f\tv[0-9]+,\s*fa[0-9]+ +** vfmv\.s\.f\tv[0-9]+,\s*fa[0-9]+ ** ... ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c index 512fa62..cf53aca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-7.c @@ -6,9 +6,9 @@ /* ** foo: -** addi\t[a-x0-9]+,\s*[a-x0-9]+,100 +** ... ** vsetvli\tzero,a2,e64,m2,t[au],m[au] -** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero +** vmv\.v\.x\tv[0-9]+,\s*a[0-9]+ ** vs2r.v\tv[0-9]+,0\([a-x0-9]+\) ** ret */ @@ -37,7 +37,7 @@ void foo2 (void *base, void *out, size_t vl) /* ** foo3: ** ... -** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero +** vmv\.v\.x\tv[0-9]+,\s*a[0-9]+ ** ... ** ret */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-8.c index d9d10f3..fd3b7c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-8.c @@ -175,9 +175,8 @@ void foo12 (void *base, void *out, size_t vl) /* ** foo13: ** ... -** vmv.v.x\tv[0-9]+,\s*[a-x0-9]+ +** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero ** ... -** ret */ void foo13 (void *base, void *out, size_t vl) { @@ -189,7 +188,7 @@ void foo13 (void *base, void *out, size_t vl) /* ** foo14: ** ... -** vmv.v.x\tv[0-9]+,\s*[a-x0-9]+ +** vlse64.v\tv[0-9]+,0\([a-x0-9]+\),zero ** ... */ void foo14 (void *base, void *out, size_t vl) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c index 80ee1b5..64c22dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c @@ -23,4 +23,3 @@ vuint64m2_t f3(vuint64m2_t var_17, uint64_t var_60, size_t vl) /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*0,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */ /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */ -/* { dg-final { scan-assembler-times {sgtu} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/pr120297.c b/gcc/testsuite/gcc.target/riscv/rvv/pr120297.c new file mode 100644 index 0000000..3d1845d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/pr120297.c @@ -0,0 +1,50 @@ +/* { dg-do run } */ +/* { dg-require-effective-target riscv_v_ok } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fwhole-program" } */ + +unsigned a; +short c; +char d; +unsigned long e; +_Bool f[10][10]; +unsigned g[10]; +long long ak; +char i = 7; +long long t[10]; +short x[10][10][10][10]; +short y[10][10][10][10]; + +void +h (char i, long long t[], short x[][10][10][10], short y[][10][10][10], + _Bool aa) +{ + for (int j = 2; j < 8; j += 2) + { + for (short k = 0; k < 10; k++) + { + for (int l = 3; l < 8; l += 2) + a = x[1][j][k][l]; + c = x[c][1][1][c]; + } + for (int k = 0; k < 10; k++) + { + f[2][k] |= (_Bool) t[c]; + g[c] = t[c + 1]; + d += y[j][1][k][k]; + e = e > i ? e : i; + } + } +} + +int +main () +{ + t[c] = 1; + h (i, t, x, y, a); + for (int j = 0; j < 10; ++j) + for (int k = 0; k < 10; ++k) + ak ^= f[j][k] + 238516665 + (ak >> 2); + ak ^= g[c] + 238516665 + (ak >> 2); + if (ak != 234635118ull) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/pr121073.c b/gcc/testsuite/gcc.target/riscv/rvv/pr121073.c new file mode 100644 index 0000000..2789d0f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/pr121073.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fsigned-char -fno-strict-aliasing -fwrapv -Wno-stringop-overflow -Wno-aggressive-loop-optimizations" } */ + +int a; +unsigned char p[1][21]; +void init() { + for (int s = 0; s < 21; ++s) + for (int t = 0; t < 21; ++t) + p[s][t] = 39; + for (short t = 0; t < 9; t += -5077966496202321318LL + 28071) + a = p[3][t] && p[2][t]; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp index 3824997..d76a2d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp +++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv.exp @@ -132,5 +132,22 @@ foreach op $AUTOVEC_TEST_OPTS { "$op" "" } +# vx_vf tests +set AUTOVEC_TEST_OPTS [list \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m8 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=dynamic -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m4 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m8 -ffast-math} \ + {-ftree-vectorize -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=dynamic -ffast-math} ] +foreach op $AUTOVEC_TEST_OPTS { + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/autovec/vx_vf/*.\[cS\]]] \ + "$op" "" +} + # All done. dg-finish diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c index 0379429..edb12a1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_prop-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-vector-bits=zvl" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv64gc_zve32f -mabi=lp64d -O3 -mrvv-vector-bits=zvl -fno-thread-jumps" } */ int d0, sj, v0, rp, zi; @@ -38,4 +38,4 @@ ka: goto ka; } -/* { dg-final { scan-assembler-times {vsetivli\tzero,\s*1} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\tzero,\s*1} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c index 3a64b3b..e0bd0fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-21.c @@ -29,4 +29,4 @@ void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" no-opts "-Oz" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c index cd9a5c8..0ff7f3b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-26.c @@ -32,4 +32,4 @@ void f (int8_t * restrict in, int8_t * restrict out, int n, int m, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" no-opts "-Oz" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c index 35cad2d..bd1585c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-36.c @@ -22,4 +22,4 @@ void f (int8_t * restrict in, int8_t * restrict out, int n, int cond) } /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" no-opts "-Oz" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c index cd3e961..9bade06 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-37.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -mtune=rocket" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c index fa5f3c6..55740ba 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-39.c @@ -16,4 +16,4 @@ void f (int8_t *base, int8_t *out, size_t m, size_t n) { } /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" no-opts "-Oz" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c index 99c1722..91102ac 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-41.c @@ -16,4 +16,4 @@ void f (int8_t *base, int8_t *out, size_t m, size_t n) { } /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" no-opts "-Oz" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c index 5db1a40..3d3c5d6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-56.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c index 3f22fc8..013d32c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-67.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c index 64666d3..aef8325 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-68.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c index 07a64b4..fa4328f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-71.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2 -fno-thread-jumps" } */ #include "riscv_vector.h" @@ -50,5 +50,5 @@ void f (int8_t * restrict in, int8_t * restrict out, int l, int n, int m, size_t } } -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 4 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr117974.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr117974.c new file mode 100644 index 0000000..bf99240 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr117974.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -Ofast" } */ + +float g(float q[], int N){ + float dqnorm = 0.0; + + #pragma GCC unroll 4 + + for (int i=0; i < N; i++) { + dqnorm = dqnorm + q[i] * q[i]; + } + return dqnorm; +} + +/* need slightly different test for when -funroll-loops is enabled to keep + test output stable. Otherwise test may be flakey. */ +/* { dg-final { scan-assembler-times {beq\s+[a-x0-9]+,zero,.L12\s+vsetvli} 3 { target { no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {beq\s+[a-x0-9]+,[a-x0-9]+,.L12\s+vsetvli} 3 { target { any-opts "-funroll-loops" } } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c index d7f6d18..321eb3b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -mtune=rocket" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c index 1354c5e..29dcfef 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -mtune=rocket" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c index 6366dd9..8b6299e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -mtune=rocket" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c index bbff028..3b836f9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */ +/* { dg-options "-mrvv-vector-bits=scalable -march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -mtune=rocket" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c index be14365..47eb43e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c @@ -18,4 +18,4 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t k) { /* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*4} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c index 2304246..45c8a4d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c @@ -18,6 +18,6 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n, int c } } -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ /* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*5} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c index 3df00d6..9bef7dd 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c @@ -17,5 +17,5 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n) { } } -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c index 3228a75..28c3dd0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c @@ -17,5 +17,5 @@ void foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out, size_t n) { } } -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ -/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*m1,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vtype-call-clobbered.c b/gcc/testsuite/gcc.target/riscv/rvv/vtype-call-clobbered.c index be9f312..78c8a4a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/vtype-call-clobbered.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/vtype-call-clobbered.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64 -O2" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O2" } */ /* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c new file mode 100644 index 0000000..7667e56 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_f.c @@ -0,0 +1,88 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sifive_vector.h" + +typedef _Float16 float16_t; +typedef float float32_t; +typedef double float64_t; + +/* +** test_sf_vc_v_fv_u16mf4: +** ... +** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+ +** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u16mf4(1, vs2, fs1, vl); +} + +/* +** test_sf_vc_v_fv_se_u16mf4: +** ... +** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+ +** sf\.vc\.v\.fv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, float16_t fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u16mf4(1, vs2, fs1, vl); +} + +/* +** test_sf_vc_fv_se_u16mf2: +** ... +** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+ +** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, float16_t fs1, size_t vl) { + __riscv_sf_vc_fv_se_u16mf2(1, 3, vs2, fs1, vl); +} + +/* +** test_sf_vc_v_fvv_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u16m1(1, vd, vs2, fs1, vl); +} + +/* +** test_sf_vc_v_fvv_se_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.v\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, float16_t fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u16m1(1, vd, vs2, fs1, vl); +} + +/* +** test_sf_vc_fvv_se_u32m8: +** ... +** vsetivli\s+zero+,0+,e32+,m8,ta,ma+ +** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u32m8(1, vd, vs2, fs1, vl); +} + + +/* +** test_sf_vc_fvw_se_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.fvw\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+ +** ... +*/ +void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float32_t fs1, size_t vl) { + __riscv_sf_vc_fvw_se_u32m2(1, vd, vs2, fs1, vl); +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c new file mode 100644 index 0000000..5528cc5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_i.c @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sifive_vector.h" + + +/* +** test_sf_vc_v_i_u16m4: +** ... +** vsetivli\s+zero+,0+,e16+,m4,ta,ma+ +** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) { + return __riscv_sf_vc_v_i_u16m4(1, 2, 4, vl); +} + +/* +** test_sf_vc_v_i_se_u16m4: +** ... +** vsetivli\s+zero+,0+,e16+,m4,ta,ma+ +** sf\.vc\.v\.i\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) { + return __riscv_sf_vc_v_i_se_u16m4(1, 2, 4, vl); +} + +/* +** test_sf_vc_i_se_u16mf4: +** ... +** vsetivli\s+zero+,0+,e16+,mf4,ta,ma+ +** sf\.vc\.i\t[0-9]+,[0-9]+,[0-9]+,[0-9]+ +** ... +*/ +void test_sf_vc_i_se_u16mf4(size_t vl) { + __riscv_sf_vc_i_se_u16mf4(1, 2, 3, 4, vl); +} + +/* +** test_sf_vc_v_iv_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint32m2_t test_sf_vc_v_iv_u32m2(vuint32m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u32m2(1, vs2, 4, vl); +} + +/* +** test_sf_vc_v_iv_se_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.v\.iv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint32m2_t test_sf_vc_v_iv_se_u32m2(vuint32m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u32m2(1, vs2, 4, vl); +} + +/* +** test_sf_vc_iv_se_u16m2: +** ... +** vsetivli\s+zero+,0+,e16+,m2,ta,ma+ +** sf\.vc\.iv\t[0-9]+,[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +void test_sf_vc_iv_se_u16m2(vuint16m2_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u16m2(1, 3, vs2, 4, vl); +} + +/* +** test_sf_vc_v_ivv_u8m8: +** ... +** vsetivli\s+zero+,0+,e8+,m8,ta,ma+ +** sf\.vc\.v\.ivv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint8m8_t test_sf_vc_v_ivv_u8m8(vuint8m8_t vd, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u8m8(1, vd, vs2, 4, vl); +} + +/* +** test_sf_vc_v_ivv_se_u8m8: +** ... +** vsetivli\s+zero+,0+,e8+,m8,ta,ma+ +** sf\.vc\.v\.ivv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint8m8_t test_sf_vc_v_ivv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u8m8(1, vd, vs2, 4, vl); +} + +/* +** test_sf_vc_ivv_se_u64m1: +** ... +** vsetivli\s+zero+,0+,e64+,m1,ta,ma+ +** sf\.vc\.ivv\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +void test_sf_vc_ivv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u64m1(1, vd, vs2, 4, vl); +} + +/* +** test_sf_vc_v_ivw_u8mf4: +** ... +** vsetivli\s+zero+,0+,e8+,mf4,ta,ma+ +** sf\.vc\.v\.ivw\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint16mf2_t test_sf_vc_v_ivw_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u8mf4(1, vd, vs2, 4, vl); +} + +/* +** test_sf_vc_v_ivw_se_u8mf4: +** ... +** vsetivli\s+zero+,0+,e8+,mf4,ta,ma+ +** sf\.vc\.v\.ivw\t[0-9]+,v[0-9]+,v[0-9]+,[0-9]+ +** ... +*/ +vuint16mf2_t test_sf_vc_v_ivw_se_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u8mf4(1, vd, vs2, 4, vl); +} + +void test_sf_vc_ivw_se_u32m4(vuint64m8_t vd, vuint32m4_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u32m4(1, vd, vs2, 4, vl); +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_v.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_v.c new file mode 100644 index 0000000..e3022c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_v.c @@ -0,0 +1,107 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sifive_vector.h" + + +/* +** test_sf_vc_v_vv_u8mf8: +** ... +** vsetivli\s+zero+,0+,e8+,mf8,ta,ma+ +** sf\.vc\.v\.vv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint8mf8_t test_sf_vc_v_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t rs1, size_t vl) { + return __riscv_sf_vc_v_vv_u8mf8(1, vs2, rs1, vl); +} + +/* +** test_sf_vc_v_vv_se_u8mf8: +** ... +** vsetivli\s+zero+,0+,e8+,mf8,ta,ma+ +** sf\.vc\.v\.vv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint8mf8_t test_sf_vc_v_vv_se_u8mf8(vuint8mf8_t vs2, vuint8mf8_t rs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u8mf8(1, vs2, rs1, vl); +} + +/* +** test_sf_vc_vv_se_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.vv\t[0-9]+,[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +void test_sf_vc_vv_se_u16m1(vuint16m1_t vs2, vuint16m1_t rs1, size_t vl) { + __riscv_sf_vc_vv_se_u16m1(1, 3, vs2, rs1, vl); +} + +/* +** test_sf_vc_v_vvv_u32mf2: +** ... +** vsetivli\s+zero+,0+,e32+,mf2,ta,ma+ +** sf\.vc\.v\.vvv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint32mf2_t test_sf_vc_v_vvv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t rs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u32mf2(1, vd, vs2, rs1, vl); +} + +/* +** test_sf_vc_v_vvv_se_u32mf2: +** ... +** vsetivli\s+zero+,0+,e32+,mf2,ta,ma+ +** sf\.vc\.v\.vvv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint32mf2_t test_sf_vc_v_vvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t rs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u32mf2(1, vd, vs2, rs1, vl); +} + +/* +** test_sf_vc_vvv_se_u64m1: +** ... +** vsetivli\s+zero+,0+,e64+,m1,ta,ma+ +** sf\.vc\.vvv\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +void test_sf_vc_vvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t rs1, size_t vl) { + __riscv_sf_vc_vvv_se_u64m1(1, vd, vs2, rs1, vl); +} + + +/* +** test_sf_vc_v_vvw_u8m1: +** ... +** vsetivli\s+zero+,0+,e8+,m1,ta,ma+ +** sf\.vc\.v\.vvw\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint16m2_t test_sf_vc_v_vvw_u8m1(vuint16m2_t vd, vuint8m1_t vs2, vuint8m1_t rs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u8m1(1, vd, vs2, rs1, vl); +} + +/* +** test_sf_vc_v_vvw_se_u8m1: +** ... +** vsetivli\s+zero+,0+,e8+,m1,ta,ma+ +** sf\.vc\.v\.vvw\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +vuint16m2_t test_sf_vc_v_vvw_se_u8m1(vuint16m2_t vd, vuint8m1_t vs2, vuint8m1_t rs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u8m1(1, vd, vs2, rs1, vl); +} + +/* +** test_sf_vc_vvw_se_u16mf2: +** ... +** vsetivli\s+zero+,0+,e16+,mf2,ta,ma+ +** sf\.vc\.vvw\t[0-9]+,v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +void test_sf_vc_vvw_se_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, vuint16mf2_t rs1, size_t vl) { + __riscv_sf_vc_vvw_se_u16mf2(1, vd, vs2, rs1, vl); +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_x.c b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_x.c new file mode 100644 index 0000000..10c92c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_x.c @@ -0,0 +1,138 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "sifive_vector.h" + +/* +** test_sf_vc_v_x_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.v\.x\t[0-9]+,[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint32m1_t test_sf_vc_v_x_u32m1(uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_x_u32m1(1, 2, xs1, vl); +} + +/* +** test_sf_vc_v_x_se_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.v\.x\t[0-9]+,[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint32m1_t test_sf_vc_v_x_se_u32m1(uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u32m1(1, 2, xs1, vl); +} + +/* +** test_sf_vc_x_se_u16m8: +** ... +** vsetivli\s+zero+,0+,e16+,m8,ta,ma+ +** sf\.vc\.x\t[0-9]+,[0-9]+,[0-9]+,a[0-9]+ +** ... +*/ +void test_sf_vc_x_se_u16m8(uint16_t xs1, size_t vl) { + __riscv_sf_vc_x_se_u16m8(1, 2, 3, xs1, vl); +} + +/* +** test_sf_vc_v_xv_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.v\.xv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint32m2_t test_sf_vc_v_xv_u32m2(vuint32m2_t vs2, uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_xv_u32m2(1, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xv_se_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.v\.xv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint32m2_t test_sf_vc_v_xv_se_u32m2(vuint32m2_t vs2, uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u32m2(1, vs2, xs1, vl); +} + +/* +** test_sf_vc_xv_se_u16m4: +** ... +** vsetivli\s+zero+,0+,e16+,m4,ta,ma+ +** sf\.vc\.xv\t[0-9]+,[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +void test_sf_vc_xv_se_u16m4(vuint16m4_t vs2, uint16_t xs1, size_t vl) { + __riscv_sf_vc_xv_se_u16m4(1, 3, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xvv_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.v\.xvv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint16m1_t test_sf_vc_v_xvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, uint16_t xs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u16m1(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xvv_se_u16m1: +** ... +** vsetivli\s+zero+,0+,e16+,m1,ta,ma+ +** sf\.vc\.v\.xvv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint16m1_t test_sf_vc_v_xvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, uint16_t xs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u16m1(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_xvv_se_u32m2: +** ... +** vsetivli\s+zero+,0+,e32+,m2,ta,ma+ +** sf\.vc\.xvv\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +void test_sf_vc_xvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, uint32_t xs1, size_t vl) { + __riscv_sf_vc_xvv_se_u32m2(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xvw_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.v\.xvw\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint64m2_t test_sf_vc_v_xvw_u32m1(vuint64m2_t vd, vuint32m1_t vs2, uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u32m1(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_v_xvw_se_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.v\.xvw\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +vuint64m2_t test_sf_vc_v_xvw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, uint32_t xs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u32m1(1, vd, vs2, xs1, vl); +} + +/* +** test_sf_vc_xvw_se_u32m1: +** ... +** vsetivli\s+zero+,0+,e32+,m1,ta,ma+ +** sf\.vc\.xvw\t[0-9]+,v[0-9]+,v[0-9]+,a[0-9]+ +** ... +*/ +void test_sf_vc_xvw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, uint32_t xs1, size_t vl) { + __riscv_sf_vc_xvw_se_u32m1(1, vd, vs2, xs1, vl); +} + diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c new file mode 100644 index 0000000..6939157 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120461.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=xt-c920 -mrvv-vector-bits=zvl -fzero-call-used-regs=all" */ + +void +foo () +{} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120642.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120642.c new file mode 100644 index 0000000..1a72580 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr120642.c @@ -0,0 +1,4 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcpu=xt-c920 -mrvv-vector-bits=zvl" } */ +int __attribute__((__vector_size__(4 * sizeof(int)))) v; +void foo() { v /= 3; } diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h index c8a135a..e40902a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith.h @@ -4,6 +4,10 @@ #include <stdint-gcc.h> #include <stdbool.h> +#if __riscv_xlen == 64 +typedef unsigned __int128 uint128_t; +#endif + /******************************************************************************/ /* Saturation Add (unsigned and signed) */ /******************************************************************************/ @@ -13,6 +17,7 @@ sat_u_add_##T##_fmt_1 (T x, T y) \ { \ return (x + y) | (-(T)((T)(x + y) < x)); \ } +#define DEF_SAT_U_ADD_FMT_1_WRAP(T) DEF_SAT_U_ADD_FMT_1(T) #define DEF_SAT_U_ADD_FMT_2(T) \ T __attribute__((noinline)) \ @@ -20,6 +25,7 @@ sat_u_add_##T##_fmt_2 (T x, T y) \ { \ return (T)(x + y) >= x ? (x + y) : -1; \ } +#define DEF_SAT_U_ADD_FMT_2_WRAP(T) DEF_SAT_U_ADD_FMT_2(T) #define DEF_SAT_U_ADD_FMT_3(T) \ T __attribute__((noinline)) \ @@ -29,6 +35,7 @@ sat_u_add_##T##_fmt_3 (T x, T y) \ T overflow = __builtin_add_overflow (x, y, &ret); \ return (T)(-overflow) | ret; \ } +#define DEF_SAT_U_ADD_FMT_3_WRAP(T) DEF_SAT_U_ADD_FMT_3(T) #define DEF_SAT_U_ADD_FMT_4(T) \ T __attribute__((noinline)) \ @@ -37,6 +44,7 @@ sat_u_add_##T##_fmt_4 (T x, T y) \ T ret; \ return __builtin_add_overflow (x, y, &ret) ? -1 : ret; \ } +#define DEF_SAT_U_ADD_FMT_4_WRAP(T) DEF_SAT_U_ADD_FMT_4(T) #define DEF_SAT_U_ADD_FMT_5(T) \ T __attribute__((noinline)) \ @@ -45,6 +53,7 @@ sat_u_add_##T##_fmt_5 (T x, T y) \ T ret; \ return __builtin_add_overflow (x, y, &ret) == 0 ? ret : -1; \ } +#define DEF_SAT_U_ADD_FMT_5_WRAP(T) DEF_SAT_U_ADD_FMT_5(T) #define DEF_SAT_U_ADD_FMT_6(T) \ T __attribute__((noinline)) \ @@ -52,13 +61,62 @@ sat_u_add_##T##_fmt_6 (T x, T y) \ { \ return (T)(x + y) < x ? -1 : (x + y); \ } +#define DEF_SAT_U_ADD_FMT_6_WRAP(T) DEF_SAT_U_ADD_FMT_6(T) + +#define DEF_SAT_U_ADD_FMT_7(WT, T) \ +T __attribute__((noinline)) \ +sat_u_add_##WT##_##T##_fmt_7(T x, T y) \ +{ \ + T max = -1; \ + WT val = (WT)x + (WT)y; \ + return val > max ? max : (T)val; \ +} +#define DEF_SAT_U_ADD_FMT_7_WRAP(WT, T) DEF_SAT_U_ADD_FMT_7(WT, T) + +#define DEF_SAT_U_ADD_FMT_8(T) \ +T __attribute__((noinline)) \ +sat_u_add_##T##_fmt_8(T x, T y) \ +{ \ + return x <= (T)(x + y) ? (x + y) : -1; \ +} +#define DEF_SAT_U_ADD_FMT_8_WRAP(T) DEF_SAT_U_ADD_FMT_8(T) + +#define DEF_SAT_U_ADD_FMT_9(T) \ +T __attribute__((noinline)) \ +sat_u_add_##T##_fmt_9(T x, T y) \ +{ \ + return x > (T)(x + y) ? -1 : (x + y); \ +} +#define DEF_SAT_U_ADD_FMT_9_WRAP(T) DEF_SAT_U_ADD_FMT_9(T) #define RUN_SAT_U_ADD_FMT_1(T, x, y) sat_u_add_##T##_fmt_1(x, y) +#define RUN_SAT_U_ADD_FMT_1_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_1(T, x, y) #define RUN_SAT_U_ADD_FMT_2(T, x, y) sat_u_add_##T##_fmt_2(x, y) +#define RUN_SAT_U_ADD_FMT_2_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_2(T, x, y) #define RUN_SAT_U_ADD_FMT_3(T, x, y) sat_u_add_##T##_fmt_3(x, y) +#define RUN_SAT_U_ADD_FMT_3_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_3(T, x, y) #define RUN_SAT_U_ADD_FMT_4(T, x, y) sat_u_add_##T##_fmt_4(x, y) +#define RUN_SAT_U_ADD_FMT_4_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_4(T, x, y) #define RUN_SAT_U_ADD_FMT_5(T, x, y) sat_u_add_##T##_fmt_5(x, y) +#define RUN_SAT_U_ADD_FMT_5_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_5(T, x, y) #define RUN_SAT_U_ADD_FMT_6(T, x, y) sat_u_add_##T##_fmt_6(x, y) +#define RUN_SAT_U_ADD_FMT_6_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_6(T, x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U16(T, x, y) \ + sat_u_add_uint16_t_##T##_fmt_7(x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP(T, x, y) \ + RUN_SAT_U_ADD_FMT_7_FROM_U16(T, x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U32(T, x, y) \ + sat_u_add_uint32_t_##T##_fmt_7(x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP(T, x, y) \ + RUN_SAT_U_ADD_FMT_7_FROM_U32(T, x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U64(T, x, y) \ + sat_u_add_uint64_t_##T##_fmt_7(x, y) +#define RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T, x, y) \ + RUN_SAT_U_ADD_FMT_7_FROM_U64(T, x, y) +#define RUN_SAT_U_ADD_FMT_8(T, x, y) sat_u_add_##T##_fmt_8(x, y) +#define RUN_SAT_U_ADD_FMT_8_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_8(T, x, y) +#define RUN_SAT_U_ADD_FMT_9(T, x, y) sat_u_add_##T##_fmt_9(x, y) +#define RUN_SAT_U_ADD_FMT_9_WRAP(T, x, y) RUN_SAT_U_ADD_FMT_9(T, x, y) #define DEF_SAT_U_ADD_IMM_FMT_1(T, IMM) \ T __attribute__((noinline)) \ @@ -193,6 +251,18 @@ sat_s_add_imm_##T##_fmt_1##_##INDEX (T x) \ #define RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect) \ if (sat_s_add_imm##_##T##_fmt_1##_##INDEX(x) != expect) __builtin_abort () +#define DEF_SAT_S_ADD_IMM_FMT_2(INDEX, T, UT, IMM, MIN, MAX) \ +T __attribute__((noinline)) \ +sat_s_add_imm_##T##_fmt_2##_##INDEX (T x) \ +{ \ + T sum = (T)((UT)x + (UT)IMM); \ + return ((x ^ sum) < 0 && (x ^ IMM) >= 0) ? \ + (-(T)(x < 0) ^ MAX) : sum; \ +} + +#define RUN_SAT_S_ADD_IMM_FMT_2(INDEX, T, x, expect) \ + if (sat_s_add_imm##_##T##_fmt_2##_##INDEX(x) != expect) __builtin_abort () + /******************************************************************************/ /* Saturation Sub (Unsigned and Signed) */ /******************************************************************************/ @@ -602,4 +672,25 @@ sat_s_trunc_##WT##_to_##NT##_fmt_8 (WT x) \ #define RUN_SAT_S_TRUNC_FMT_8(NT, WT, x) sat_s_trunc_##WT##_to_##NT##_fmt_8 (x) #define RUN_SAT_S_TRUNC_FMT_8_WRAP(NT, WT, x) RUN_SAT_S_TRUNC_FMT_8(NT, WT, x) +/******************************************************************************/ +/* Saturation Mult (unsigned and signed) */ +/******************************************************************************/ + +#define DEF_SAT_U_MUL_FMT_1(NT, WT) \ +NT __attribute__((noinline)) \ +sat_u_mul_##NT##_from_##WT##_fmt_1 (NT a, NT b) \ +{ \ + WT x = (WT)a * (WT)b; \ + NT max = -1; \ + if (x > (WT)(max)) \ + return max; \ + else \ + return (NT)x; \ +} + +#define DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) DEF_SAT_U_MUL_FMT_1(NT, WT) +#define RUN_SAT_U_MUL_FMT_1(NT, WT, a, b) \ + sat_u_mul_##NT##_from_##WT##_fmt_1 (a, b) +#define RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, a, b) RUN_SAT_U_MUL_FMT_1(NT, WT, a, b) + #endif diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_arith_data.h b/gcc/testsuite/gcc.target/riscv/sat/sat_arith_data.h index 9f9f7d0..bd33ff1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_arith_data.h +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_arith_data.h @@ -12,6 +12,7 @@ #define TEST_BINARY_STRUCT_NAME(T, NAME) test_##T##_##NAME##_s #define TEST_BINARY_STRUCT_DECL(T, NAME) struct TEST_BINARY_STRUCT_NAME(T, NAME) +#define TEST_BINARY_STRUCT_DECL_WRAP(T, NAME) TEST_BINARY_STRUCT_DECL(T, NAME) #define TEST_BINARY_STRUCT(T, NAME) \ struct TEST_BINARY_STRUCT_NAME(T, NAME) \ { \ @@ -32,6 +33,16 @@ TEST_UNARY_STRUCT (uint16_t, uint32_t) TEST_UNARY_STRUCT (uint16_t, uint64_t) TEST_UNARY_STRUCT (uint32_t, uint64_t) +TEST_BINARY_STRUCT (uint8_t, usadd) +TEST_BINARY_STRUCT (uint16_t, usadd) +TEST_BINARY_STRUCT (uint32_t, usadd) +TEST_BINARY_STRUCT (uint64_t, usadd) + +TEST_BINARY_STRUCT (uint8_t, usmul) +TEST_BINARY_STRUCT (uint16_t, usmul) +TEST_BINARY_STRUCT (uint32_t, usmul) +TEST_BINARY_STRUCT (uint64_t, usmul) + TEST_BINARY_STRUCT (int8_t, ssadd) TEST_BINARY_STRUCT (int16_t, ssadd) TEST_BINARY_STRUCT (int32_t, ssadd) @@ -236,6 +247,62 @@ TEST_UNARY_STRUCT_DECL(int32_t, int64_t) \ {-2147483648, -9223372036854775808ull}, }; +TEST_BINARY_STRUCT_DECL(uint8_t, usadd) TEST_BINARY_DATA(uint8_t, usadd)[] = +{ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 254, 254, }, + { 1, 254, 255, }, + { 2, 254, 255, }, + { 0, 255, 255, }, + { 1, 255, 255, }, + { 2, 255, 255, }, + { 255, 255, 255, }, +}; + +TEST_BINARY_STRUCT_DECL(uint16_t, usadd) TEST_BINARY_DATA(uint16_t, usadd)[] = +{ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 65534, 65534, }, + { 1, 65534, 65535, }, + { 2, 65534, 65535, }, + { 0, 65535, 65535, }, + { 1, 65535, 65535, }, + { 2, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +TEST_BINARY_STRUCT_DECL(uint32_t, usadd) TEST_BINARY_DATA(uint32_t, usadd)[] = +{ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 4294967294, 4294967294, }, + { 1, 4294967294, 4294967295, }, + { 2, 4294967294, 4294967295, }, + { 0, 4294967295, 4294967295, }, + { 1, 4294967295, 4294967295, }, + { 2, 4294967295, 4294967295, }, + { 4294967295, 4294967295, 4294967295, }, +}; + +TEST_BINARY_STRUCT_DECL(uint64_t, usadd) TEST_BINARY_DATA(uint64_t, usadd)[] = +{ + { 0, 0, 0, }, + { 0, 1, 1, }, + { 1, 1, 2, }, + { 0, 18446744073709551614u, 18446744073709551614u, }, + { 1, 18446744073709551614u, 18446744073709551615u, }, + { 2, 18446744073709551614u, 18446744073709551615u, }, + { 0, 18446744073709551615u, 18446744073709551615u, }, + { 1, 18446744073709551615u, 18446744073709551615u, }, + { 2, 18446744073709551615u, 18446744073709551615u, }, + { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, +}; + TEST_BINARY_STRUCT_DECL(int8_t, ssadd) TEST_BINARY_DATA(int8_t, ssadd)[] = { { 0, 0, 0}, @@ -372,4 +439,60 @@ TEST_BINARY_STRUCT_DECL(int64_t, sssub) TEST_BINARY_DATA(int64_t, sssub)[] = { 9223372036854775806ll, 9223372036854775800ll, 6}, }; +TEST_BINARY_STRUCT_DECL(uint8_t, usmul) TEST_BINARY_DATA(uint8_t, usmul)[] = +{ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 1, }, + { 1, 127, 127, }, + { 2, 127, 254, }, + { 3, 127, 255, }, + { 127, 127, 255, }, + { 1, 255, 255, }, + { 127, 255, 255, }, + { 255, 255, 255, }, +}; + +TEST_BINARY_STRUCT_DECL(uint16_t, usmul) TEST_BINARY_DATA(uint16_t, usmul)[] = +{ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 1, }, + { 1, 32767, 32767, }, + { 2, 32767, 65534, }, + { 3, 32767, 65535, }, + { 32767, 32767, 65535, }, + { 1, 65535, 65535, }, + { 32767, 65535, 65535, }, + { 65535, 65535, 65535, }, +}; + +TEST_BINARY_STRUCT_DECL(uint32_t, usmul) TEST_BINARY_DATA(uint32_t, usmul)[] = +{ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 1, }, + { 1, 2147483647, 2147483647, }, + { 2, 2147483647, 4294967294, }, + { 3, 2147483647, 4294967295, }, + { 2147483647, 2147483647, 4294967295, }, + { 1, 4294967295, 4294967295, }, + { 2147483647, 4294967295, 4294967295, }, + { 4294967295, 4294967295, 4294967295, }, +}; + +TEST_BINARY_STRUCT_DECL(uint64_t, usmul) TEST_BINARY_DATA(uint64_t, usmul)[] = +{ + { 0, 0, 0, }, + { 0, 1, 0, }, + { 1, 1, 1, }, + { 1, 9223372036854775807ull, 9223372036854775807ull, }, + { 2, 9223372036854775807ull, 18446744073709551614ull, }, + { 3, 9223372036854775807ull, 18446744073709551615ull, }, + { 9223372036854775807ull, 9223372036854775807ull, 18446744073709551615ull, }, + { 1, 18446744073709551615ull, 18446744073709551615ull, }, + { 9223372036854775807ull, 18446744073709551615ull, 18446744073709551615ull, }, + { 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i16.c index 55890d8..50f0f1f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i16.c @@ -1,32 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int16_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_ADD_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i32.c index 29e843f..dc65817 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i32.c @@ -1,31 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int32_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_ADD_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i64.c index 7f29d21..9995bc7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i64.c @@ -1,29 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int64_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_ADD_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i8.c index 3ad7bdd..caf745a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-1-i8.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int8_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_ADD_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i16.c index 07d3101..f19187d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i16.c @@ -1,32 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int16_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_ADD_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i32.c index 81b85b4..88dc37d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i32.c @@ -1,31 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int32_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_ADD_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i64.c index 9a3d83e..891d6cf 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i64.c @@ -1,29 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int64_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_ADD_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i8.c index ecc9a0f..a07172b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-2-i8.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int8_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_ADD_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i16.c index 7e93385..5077198 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i16.c @@ -1,32 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int16_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_ADD_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i32.c index 09bf497..07af4e1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i32.c @@ -1,31 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int32_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_ADD_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i64.c index 5652cdb..7c4be5b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i64.c @@ -1,29 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int64_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_ADD_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i8.c index 0eb0c84..fc0e1b7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-3-i8.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int8_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_ADD_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i16.c index 9dfdb9e..4c0b38a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i16.c @@ -1,32 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int16_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_ADD_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i32.c index 74df576..45b4638 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i32.c @@ -1,31 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int32_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_ADD_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i64.c index 5937699..294eb52 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i64.c @@ -1,29 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int64_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_ADD_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i8.c index af850d0..143fa3c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-4-i8.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_add_int8_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_ADD_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i16.c index 34459b8..1023934 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i32.c index 4d4841f..bccb768 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i64.c index df81887..34de520 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i8.c index 9a4ce33..6d136ec 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-1-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i16.c index cdac5bd..ee8e439 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i32.c index 4ac952e..8996dd2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i64.c index 4d25e7f..155c8e9 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i8.c index d57e0a0..4502ed3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-2-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i16.c index 08b961a..21289c9 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i32.c index 3611b6e..3d4a6fa 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i64.c index 3eaa6c2..b55d221 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i8.c index 6d38e5f..9fef8b0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-3-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i16.c index 2e73450..fd135e5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i32.c index ec3022d..38ade40 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i64.c index 911856e..04ba746 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i8.c index 94d48ef..32aea5c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add-run-4-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i16.c new file mode 100644 index 0000000..414cb61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i16.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, -7, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_1(1, int16_t, uint16_t, -1, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i32.c new file mode 100644 index 0000000..adf5b39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, 10, INT32_MIN, INT32_MAX) + +DEF_SAT_S_ADD_IMM_FMT_1(1, int32_t, uint32_t, -1, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i64.c new file mode 100644 index 0000000..b88e064 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_1(0, int64_t, uint64_t, 10, INT64_MIN, INT64_MAX) + +DEF_SAT_S_ADD_IMM_FMT_1(1, int64_t, uint64_t, -1, INT64_MIN, INT64_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i8.c new file mode 100644 index 0000000..0e337ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-i8.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, 9, INT8_MIN, INT8_MAX) + +DEF_SAT_S_ADD_IMM_FMT_1(1, int8_t, uint8_t, -1, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1.c deleted file mode 100644 index b6f1731..0000000 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1.c +++ /dev/null @@ -1,29 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ - -#include "sat_arith.h" - -/* -** sat_s_add_imm_int8_t_fmt_1_0: -** addi\s+[atx][0-9]+,\s*a0,\s*9 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** srli\s+[atx][0-9]+,\s*a0,\s*7 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+a0,\s*a0,\s*63 -** xori\s+[atx][0-9]+,\s*a0,\s*127 -** neg\s+a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*a0,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ -DEF_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, 9, INT8_MIN, INT8_MAX) - -/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i16.c new file mode 100644 index 0000000..f217fe1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i16.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int16_t, uint16_t, -7, INT16_MIN, INT16_MAX) + +DEF_SAT_S_ADD_IMM_FMT_2(1, int16_t, uint16_t, -1, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i32.c new file mode 100644 index 0000000..4025b5a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int32_t, uint32_t, 10, INT32_MIN, INT32_MAX) + +DEF_SAT_S_ADD_IMM_FMT_2(1, int32_t, uint32_t, -1, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i64.c new file mode 100644 index 0000000..3fc2514 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int64_t, uint64_t, 10, INT64_MIN, INT64_MAX) + +DEF_SAT_S_ADD_IMM_FMT_2(1, int64_t, uint64_t, -1, INT64_MIN, INT64_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i8.c new file mode 100644 index 0000000..a0e15cf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-i8.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int8_t, uint8_t, 9, INT8_MIN, INT8_MAX) + +DEF_SAT_S_ADD_IMM_FMT_2(1, int8_t, uint8_t, -1, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2.c deleted file mode 100644 index 3878286..0000000 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2.c +++ /dev/null @@ -1,32 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ - -#include "sat_arith.h" - -/* -** sat_s_add_imm_int16_t_fmt_1_0: -** addi\s+[atx][0-9]+,\s*a0,\s*-7 -** xori\s+[atx][0-9]+,\s*a0,\s*-7 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+a0,\s*a0,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** neg\s+a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*a0,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ -DEF_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, -7, INT16_MIN, INT16_MAX) - -/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3.c deleted file mode 100644 index c9fbc66..0000000 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3.c +++ /dev/null @@ -1,30 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ - -#include "sat_arith.h" - -/* -** sat_s_add_imm_int32_t_fmt_1_0: -** addi\s+[atx][0-9]+,\s*a0,\s*10 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srli\s+[atx][0-9]+,\s*a0,\s*31 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+a0,\s*a0,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** neg\s+a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,a0,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ -DEF_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, 10, INT32_MIN, INT32_MAX) - -/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-4.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-4.c deleted file mode 100644 index 2aa9545..0000000 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-4.c +++ /dev/null @@ -1,28 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ - -#include "sat_arith.h" - -/* -** sat_s_add_imm_int64_t_fmt_1_0: -** addi\s+[atx][0-9]+,\s*a0,\s*10 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srli\s+[atx][0-9]+,\s*a0,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*a0,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ -DEF_SAT_S_ADD_IMM_FMT_1(0, int64_t, uint64_t, 10, INT64_MIN, INT64_MAX) - -/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i16.c index 187a098..ae2c306 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i16.c @@ -7,6 +7,7 @@ DEF_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, -32768, INT16_MIN, INT16_MAX) DEF_SAT_S_ADD_IMM_FMT_1(1, int16_t, uint16_t, 32767, INT16_MIN, INT16_MAX) DEF_SAT_S_ADD_IMM_FMT_1(2, int16_t, uint16_t, 100, INT16_MIN, INT16_MAX) DEF_SAT_S_ADD_IMM_FMT_1(3, int16_t, uint16_t, -100, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_1(4, int16_t, uint16_t, -1, INT16_MIN, INT16_MAX) #define T int16_t #define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect) @@ -21,6 +22,8 @@ T d[][2] = { { -32768, -32668, }, { -32768, -32768, }, { 0, -100, }, + { -32768, -32768, }, + { 0, -1, }, }; int @@ -38,5 +41,8 @@ main () RUN (3, T, d[6][0], d[6][1]); RUN (3, T, d[7][0], d[7][1]); + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + return 0; } diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i32.c index 899fda8..02a947f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i32.c @@ -7,6 +7,7 @@ DEF_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, -2147483648, INT32_MIN, INT32_MAX) DEF_SAT_S_ADD_IMM_FMT_1(1, int32_t, uint32_t, 2147483647, INT32_MIN, INT32_MAX) DEF_SAT_S_ADD_IMM_FMT_1(2, int32_t, uint32_t, 100, INT32_MIN, INT32_MAX) DEF_SAT_S_ADD_IMM_FMT_1(3, int32_t, uint32_t, -100, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD_IMM_FMT_1(4, int32_t, uint32_t, -1, INT32_MIN, INT32_MAX) #define T int32_t #define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect) @@ -21,6 +22,8 @@ T d[][2] = { { -300, -200, }, { 100, 0, }, { 0, -100, }, + { 100, 99, }, + { 0, -1, }, }; int @@ -38,5 +41,8 @@ main () RUN (3, T, d[6][0], d[6][1]); RUN (3, T, d[7][0], d[7][1]); + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + return 0; } diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-4.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i64.c index 3dc4f72..40270ec 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-4.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i64.c @@ -7,6 +7,7 @@ DEF_SAT_S_ADD_IMM_FMT_1(0, int64_t, uint64_t, (-9223372036854775807ll - 1), INT6 DEF_SAT_S_ADD_IMM_FMT_1(1, int64_t, uint64_t, 9223372036854775807ll, INT64_MIN, INT64_MAX) DEF_SAT_S_ADD_IMM_FMT_1(2, int64_t, uint64_t, 100, INT64_MIN, INT64_MAX) DEF_SAT_S_ADD_IMM_FMT_1(3, int64_t, uint64_t, -100, INT64_MIN, INT64_MAX) +DEF_SAT_S_ADD_IMM_FMT_1(4, int64_t, uint64_t, -1, INT64_MIN, INT64_MAX) #define T int64_t #define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect) @@ -21,6 +22,8 @@ T d[][2] = { { -1, 99, }, { 0, -100, }, { 100, 0, }, + { 0, -1, }, + { 100, 99, }, }; int @@ -38,5 +41,8 @@ main () RUN (3, T, d[6][0], d[6][1]); RUN (3, T, d[7][0], d[7][1]); + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + return 0; } diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i8.c index c71b717..9efb743 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-1-i8.c @@ -7,6 +7,7 @@ DEF_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, -128, INT8_MIN, INT8_MAX) DEF_SAT_S_ADD_IMM_FMT_1(1, int8_t, uint8_t, 127, INT8_MIN, INT8_MAX) DEF_SAT_S_ADD_IMM_FMT_1(2, int8_t, uint8_t, 6, INT8_MIN, INT8_MAX) DEF_SAT_S_ADD_IMM_FMT_1(3, int8_t, uint8_t, -6, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD_IMM_FMT_1(4, int8_t, uint8_t, -1, INT8_MIN, INT8_MAX) #define T int8_t #define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_1(INDEX, T, x, expect) @@ -21,6 +22,8 @@ T d[][2] = { { -10, -4, }, { -128, -128, }, { 127, 121, }, + { -128, -128, }, + { 1, 0, }, }; int @@ -38,5 +41,8 @@ main () RUN (3, T, d[6][0], d[6][1]); RUN (3, T, d[7][0], d[7][1]); + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + return 0; } diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i16.c new file mode 100644 index 0000000..4f24624 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i16.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int16_t, uint16_t, -32768, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(1, int16_t, uint16_t, 32767, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(2, int16_t, uint16_t, 100, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(3, int16_t, uint16_t, -100, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(4, int16_t, uint16_t, -1, INT16_MIN, INT16_MAX) + +#define T int16_t +#define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_2(INDEX, T, x, expect) + +T d[][2] = { + /* arg_0, expect */ + { -1, -32768, }, + { 2, -32766, }, + { 1, 32767, }, + { -10, 32757, }, + { 32669, 32767, }, + { -32768, -32668, }, + { -32768, -32768, }, + { 0, -100, }, + { -32768, -32768, }, + { 0, -1, }, +}; + +int +main () +{ + RUN (0, T, d[0][0], d[0][1]); + RUN (0, T, d[1][0], d[1][1]); + + RUN (1, T, d[2][0], d[2][1]); + RUN (1, T, d[3][0], d[3][1]); + + RUN (2, T, d[4][0], d[4][1]); + RUN (2, T, d[5][0], d[5][1]); + + RUN (3, T, d[6][0], d[6][1]); + RUN (3, T, d[7][0], d[7][1]); + + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i32.c new file mode 100644 index 0000000..8d9ddeb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i32.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int32_t, uint32_t, -2147483648, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(1, int32_t, uint32_t, 2147483647, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(2, int32_t, uint32_t, 100, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(3, int32_t, uint32_t, -100, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(4, int32_t, uint32_t, -1, INT32_MIN, INT32_MAX) + +#define T int32_t +#define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_2(INDEX, T, x, expect) + +T d[][2] = { + /* arg_0, expect */ + { -1, -2147483648, }, + { 2, -2147483646, }, + { 1, 2147483647, }, + { -10, 2147483637, }, + { 300, 400, }, + { -300, -200, }, + { 100, 0, }, + { 0, -100, }, + { 100, 99, }, + { 0, -1, }, +}; + +int +main () +{ + RUN (0, T, d[0][0], d[0][1]); + RUN (0, T, d[1][0], d[1][1]); + + RUN (1, T, d[2][0], d[2][1]); + RUN (1, T, d[3][0], d[3][1]); + + RUN (2, T, d[4][0], d[4][1]); + RUN (2, T, d[5][0], d[5][1]); + + RUN (3, T, d[6][0], d[6][1]); + RUN (3, T, d[7][0], d[7][1]); + + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i64.c new file mode 100644 index 0000000..4523f9a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i64.c @@ -0,0 +1,48 @@ +/* { dg-do run } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int64_t, uint64_t, (-9223372036854775807ll - 1), INT64_MIN, INT64_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(1, int64_t, uint64_t, 9223372036854775807ll, INT64_MIN, INT64_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(2, int64_t, uint64_t, 100, INT64_MIN, INT64_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(3, int64_t, uint64_t, -100, INT64_MIN, INT64_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(4, int64_t, uint64_t, -1, INT64_MIN, INT64_MAX) + +#define T int64_t +#define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_2(INDEX, T, x, expect) + +T d[][2] = { + /* arg_0, expect */ + { -1, (-9223372036854775807ll - 1), }, + { 2, -9223372036854775806ll, }, + { 1, 9223372036854775807ll, }, + { -7, 9223372036854775800ll, }, + { 0, 100, }, + { -1, 99, }, + { 0, -100, }, + { 100, 0, }, + { 0, -1, }, + { 100, 99, }, +}; + +int +main () +{ + RUN (0, T, d[0][0], d[0][1]); + RUN (0, T, d[1][0], d[1][1]); + + RUN (1, T, d[2][0], d[2][1]); + RUN (1, T, d[3][0], d[3][1]); + + RUN (2, T, d[4][0], d[4][1]); + RUN (2, T, d[5][0], d[5][1]); + + RUN (3, T, d[6][0], d[6][1]); + RUN (3, T, d[7][0], d[7][1]); + + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i8.c new file mode 100644 index 0000000..96445ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-run-2-i8.c @@ -0,0 +1,49 @@ +/* { dg-do run } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int8_t, uint8_t, -128, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(1, int8_t, uint8_t, 127, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(2, int8_t, uint8_t, 6, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(3, int8_t, uint8_t, -6, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(4, int8_t, uint8_t, -1, INT8_MIN, INT8_MAX) + +#define T int8_t +#define RUN(INDEX,T, x, expect) RUN_SAT_S_ADD_IMM_FMT_2(INDEX, T, x, expect) + +T d[][2] = { + /* arg_0, expect */ + { -1, -128, }, + { 2, -126, }, + { 1, 127, }, + { -10, 117, }, + { 122, 127, }, + { -10, -4, }, + { -128, -128, }, + { 127, 121, }, + { -128, -128, }, + { 1, 0, }, +}; + +int +main () +{ + RUN (0, T, d[0][0], d[0][1]); + RUN (0, T, d[1][0], d[1][1]); + + RUN (1, T, d[2][0], d[2][1]); + RUN (1, T, d[3][0], d[3][1]); + + RUN (2, T, d[4][0], d[4][1]); + RUN (2, T, d[5][0], d[5][1]); + + RUN (3, T, d[6][0], d[6][1]); + RUN (3, T, d[7][0], d[7][1]); + + RUN (4, T, d[8][0], d[8][1]); + RUN (4, T, d[9][0], d[9][1]); + + return 0; +} + diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i16.c index e9f7080..e9f7080 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-2-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i16.c diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i32.c index 9dae425..9dae425 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-3-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i32.c diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i8.c index 84c6bc7..84c6bc7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm-1-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i8.c diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i16.c new file mode 100644 index 0000000..a73a77f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int16_t, uint16_t, -32769, INT16_MIN, INT16_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(1, int16_t, uint16_t, 32768, INT16_MIN, INT16_MAX) + +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i32.c new file mode 100644 index 0000000..9dae425 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, -2147483649, INT32_MIN, INT32_MAX) +DEF_SAT_S_ADD_IMM_FMT_1(1, int32_t, uint32_t, 2147483648, INT32_MIN, INT32_MAX) + +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i8.c new file mode 100644 index 0000000..a9cd4b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_add_imm_type_check-2-i8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_S_ADD_IMM_FMT_2(0, int8_t, uint8_t, -129, INT8_MIN, INT8_MAX) +DEF_SAT_S_ADD_IMM_FMT_2(1, int8_t, uint8_t, 128, INT8_MIN, INT8_MAX) + +/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i16.c index c244eb4..734e8be 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i16.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int16_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_SUB_FMT_1(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i32.c index 9d8245d..3aa4c58 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i32.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int32_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srliw\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-7] -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_1(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c index 929de16..4c0caa1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i64.c @@ -1,27 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int64_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_1(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i8.c index a918d5c..6c1441b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-1-i8.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int8_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_SUB_FMT_1(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i16.c index 2da1c0d..57a4327 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i16.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int16_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_SUB_FMT_2(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i32.c index 20b28e7..28582fb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i32.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int32_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srliw\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-7] -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_2(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c index a540198..130ca46 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i64.c @@ -1,27 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int64_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_2(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i8.c index c54057d..cd407b2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-2-i8.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int8_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_SUB_FMT_2(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i16.c index 469a113..748d61a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i16.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int16_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_SUB_FMT_3(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i32.c index b2c03f6..be7869a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i32.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int32_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srliw\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-7] -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_3(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c index e3fe6c7..d16a7fb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i64.c @@ -1,27 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int64_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_3(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i8.c index 150cde1..14a2454 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-3-i8.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int8_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_SUB_FMT_3(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i16.c index 26d159c..614d1ec 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i16.c @@ -1,30 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int16_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_SUB_FMT_4(int16_t, uint16_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i32.c index d576c38..2f52bd7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i32.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int32_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srliw\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-7] -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_4(int32_t, uint32_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c index f42ffea..cef478b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i64.c @@ -1,27 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int64_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_S_SUB_FMT_4(int64_t, uint64_t, INT64_MIN, INT64_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i8.c index ee510a6..3ed7790 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-4-i8.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_sub_int8_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*a1 -** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_SUB_FMT_4(int8_t, uint8_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i16.c index e248b73..b2c5735 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i32.c index bebb4be..6d1518e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i64.c index f31eb29..adcd1bb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i8.c index e165e39..31fa0a6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-1-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i16.c index 08a9b5c..0c5ad8c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i32.c index fc79969..5e89539 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i64.c index 8d5f745..199e204 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i8.c index 9f6ef30..4cfe787 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-2-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i16.c index 0523d13..3cf4ecd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i32.c index e720964..ce2151c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i64.c index 49ed051..158eeaa 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i8.c index 99b413f..8eb7ab5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-3-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i16.c index c7056ed..339a403 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i32.c index 7168f94..285733a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i64.c index 29b2b54..546bac1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i8.c index 65027b7..dafc86f1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_sub-run-4-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c index 451a375..6d1fbc4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_1: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_1(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c index 2aafb94..56a6699 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_1: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_1(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c index 6e21ee3..10c3320 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_1: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_1(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c index 5e971e4..558d704 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_1: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_1(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c index 87e5a52..02bef46 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_1: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_1(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c index 22a0dd4..da04904 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-1-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_1: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_1(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c index cb307ac..41391e2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_2: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_2(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c index b4bee21..3e5f9e1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_2: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_2(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c index c467c8d..228eeab 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_2: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_2(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c index 883b77b..78542ca 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_2: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_2(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c index bb9ffce..556e8ea 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_2: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_2(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c index a54db48..918a8c3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-2-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_2: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_2(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c index 219156c..13c0291 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_3: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_3(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c index 87b8a70..03077b7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_3: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_3(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c index 7acd515..e09a88d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_3: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_3(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c index 9141f08..ca071d1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_3: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_3(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c index 839a6f7..4acd93c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_3: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_3(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c index 5d13f09..362970c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-3-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_3: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_3(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c index 34dc804..94d9cc4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_4: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_4(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c index 89c476e..51a6e7b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_4: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_4(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c index 03ca7b7..9101b40 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_4: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_4(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c index aafe167..48452e3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_4: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_4(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c index 08e5eb3..6757913 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_4: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_4(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c index b0e71fe..9c65582 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-4-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_4: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_4(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c index b42c759..f02f866 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_5: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_5(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c index 625372e..6753c03 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_5: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_5(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c index 250e174..3fd17fa 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_5: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_5(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c index 4a6ac6d..fba761a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_5: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_5(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c index 02aa6db..8872f7f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_5: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_5(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c index ae1bcb9..13539aa 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-5-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_5: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_5(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c index 9a740d7..4aa9a8f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_6: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_6(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c index 1e42bfd..a772ee8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_6: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_6(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c index c3bd46d..9c5d88b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_6: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_6(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c index a6575f5..f9f18e9 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_6: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_6(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c index fd7b72e..3658fbb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_6: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_6(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c index 242d2d0..f1a7eb8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-6-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_6: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_6(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c index 3f258b8..50b06d5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_7: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_7(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c index f37a57e..12be220 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_7: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_7(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c index 4e4a7eb..cb73531 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_7: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_7(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c index 29b64b4..d52394c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_7: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_7(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c index 2bfe898..cf79778 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_7: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_7(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c index 494a314..67485a3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-7-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_7: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_7(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c index 678dec6..a34bf4a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i16-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int16_t_to_int8_t_fmt_8: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_8(int8_t, int16_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c index 4acc789..9c25ff0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int16_t_fmt_8: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_8(int16_t, int32_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c index 34a992b..9ee75e2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i32-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int32_t_to_int8_t_fmt_8: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_8(int8_t, int32_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c index 1919ba5..8cd361e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i16.c @@ -1,28 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int16_t_fmt_8: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** li\s+[atx][0-9]+,\s*-32768 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*16 -** sraiw\s+a0,\s*a0,\s*16 -** ret -*/ DEF_SAT_S_TRUNC_FMT_8(int16_t, int64_t, INT16_MIN, INT16_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c index 541e55c..ace064b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i32.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int32_t_fmt_8: -** li\s+[atx][0-9]+,\s*-2147483648 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xor\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_S_TRUNC_FMT_8(int32_t, int64_t, INT32_MIN, INT32_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c index 36a0085..e9a4d3b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-8-i64-to-i8.c @@ -1,26 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_s_trunc_int64_t_to_int8_t_fmt_8: -** slti\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** li\s+[atx][0-9]+,\s*-128 -** slt\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** srai\s+[atx][0-9]+,\s*[atx][0-9]+,\s*63 -** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*127 -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** and\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slliw\s+a0,\s*a0,\s*24 -** sraiw\s+a0,\s*a0,\s*24 -** ret -*/ DEF_SAT_S_TRUNC_FMT_8(int8_t, int64_t, INT8_MIN, INT8_MAX) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i16-to-i8.c index 1f230c5..7ed6809 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i16.c index 563760b..82e4201 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i8.c index af50d3e..78be831 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i16.c index 4ac7025..e8a497f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i32.c index ca6d31c..1420541 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i8.c index 697e1bc..31fecc7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-1-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i16-to-i8.c index 0d9da40..333bb92 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i16.c index 2e183ef..f494909 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i8.c index 1950092..d8a619b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i16.c index b11b097..348832d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i32.c index 419e909..fc183cf 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i8.c index de3d9f1..dec54d3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-2-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i16-to-i8.c index 032c83b..2b8700a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i16.c index 51f4946..cf3f763 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i8.c index b959bce..20a68bb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i16.c index ddfb522..5159ab1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i32.c index 22965e2..edeff90 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i8.c index 7cba408..7a22637 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-3-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i16-to-i8.c index 6dfdd4b..65f9aea 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i16.c index fcf8e47..ab32e5d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i8.c index 9d911a4..eecfc49 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i16.c index 3cc2498..410d202 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i32.c index b9abf50..17518ba 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i8.c index d90682f..bf0c43e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-4-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i16-to-i8.c index 1911166..bac1fda 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i16.c index 28116eb..3a82ea0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i8.c index 54b1ffb..26a89e7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i16.c index 633417b..a8bfeef 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i32.c index c5e4e4a..f79a049 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i8.c index 9acbee0..eea31af 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-5-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i16-to-i8.c index db1a698..0ea32f0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i16.c index e6b52d4..39e44d8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i8.c index d83836d..cb42b7e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i16.c index e910edf..f64a46b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i32.c index 98dd0c2..18e9029 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i8.c index b843300..d8cda79 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-6-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i16-to-i8.c index ab51ad5..894d5f5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i16.c index 9b2c525..1ced757 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i8.c index ab409f2..ab41a84 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i16.c index 9013952..c078136 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i32.c index 67e19e7..af86e69 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i8.c index a573706..4a2532d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-7-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i16-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i16-to-i8.c index dbd70de..65c82ad 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i16-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i16-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i16.c index 25bb42f..a8cb8e1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i8.c index 7c71b3d..5b5f8f4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i32-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i16.c index 61392b5..f489846 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i32.c index b47e5da..a3f3ae5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i8.c index 1cd7f80..aafe96b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_s_trunc-run-8-i64-to-i8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u16.c index 3c916bc..8f1b5c0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint16_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_1(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u32.c index edded3e..2c66eee 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_fmt_1: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a[01],\s*a[01] -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_FMT_1(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u64.c index 821e4bc..28d7b7c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_FMT_1(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u8.c index fd73c3a..ab18336 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-1-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint8_t_fmt_1: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_1(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u16.c index a166d28..c03b15d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint16_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_2(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u32.c index c06731b..f753c01 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_fmt_2: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a[01],\s*a[01] -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_FMT_2(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u64.c index ae10dff..cad539c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_FMT_2(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u8.c index f3977be..b595241 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-2-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint8_t_fmt_2: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_2(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u16.c index 5898c3b..08cd820 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint16_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_3(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u32.c index a1017c9..e0b73748 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_fmt_3: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a[01],\s*a[01] -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_FMT_3(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u64.c index 83fcb60..7ce0121 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_FMT_3(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u8.c index 2c398e0c..48f61c1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-3-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint8_t_fmt_3: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_3(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u16.c index c18a5d59..49d5af1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint16_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_4(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u32.c index fa2e55d..20ad476 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_fmt_4: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a[01],\s*a[01] -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_FMT_4(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u64.c index 6818c0c..6d2c9a7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_FMT_4(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u8.c index 1096de8..15e613b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-4-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint8_t_fmt_4: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_4(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u16.c index fd4be5c..225ba0c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint16_t_fmt_5: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_5(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u32.c index 4fbc807..106baf7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_fmt_5: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a[01],\s*a[01] -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_FMT_5(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u64.c index 5bc2948..48e84f6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_fmt_5: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_FMT_5(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u8.c index 74109c3..9c0d42a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-5-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint8_t_fmt_5: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_5(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u16.c index 3cb9cbe..0b541e0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint16_t_fmt_6: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_FMT_6(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u32.c index fd1cb1a..ee79156 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint32_t_fmt_6: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** add\s+[atx][0-9]+,\s*a[01],\s*a[01] -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_FMT_6(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u64.c index c968f33..fd79139 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint64_t_fmt_6: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_FMT_6(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u8.c index 9cd95ad..f826aa4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-6-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_uint8_t_fmt_6: -** add\s+[atx][0-9]+,\s*a0,\s*a1 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_FMT_6(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c new file mode 100644 index 0000000..446a951 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_7(uint32_t, uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c new file mode 100644 index 0000000..626effc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_7(uint64_t, uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c new file mode 100644 index 0000000..3014634 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_7(uint64_t, uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c new file mode 100644 index 0000000..541a1d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_7(uint16_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c new file mode 100644 index 0000000..26749a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_7(uint32_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c new file mode 100644 index 0000000..321f662 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_7(uint64_t, uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u16.c new file mode 100644 index 0000000..a7062b5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_8(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u32.c new file mode 100644 index 0000000..2e43c7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_8(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u64.c new file mode 100644 index 0000000..4ad18c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_8(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u8.c new file mode 100644 index 0000000..608d31b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-8-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_8(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u16.c new file mode 100644 index 0000000..b9766d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u16.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_9(uint16_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u32.c new file mode 100644 index 0000000..2456d39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u32.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_9(uint32_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u64.c new file mode 100644 index 0000000..0a0ff24 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u64.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_9(uint64_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u8.c new file mode 100644 index 0000000..53879dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-9-u8.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +DEF_SAT_U_ADD_FMT_9(uint8_t) + +/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u16.c index cb3879d..548fae3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u16.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_1 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_1(T) +DEF_SAT_U_ADD_FMT_1_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_1_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u32.c index c9a6080..e76b636 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u32.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_1 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_1(T) +DEF_SAT_U_ADD_FMT_1_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_1_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u64.c index c19b7e2..0ea6509 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u64.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_1 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_1(T) +DEF_SAT_U_ADD_FMT_1_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_1_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u8.c index f197249..3aa7441 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-1-u8.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_1 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_1(T) +DEF_SAT_U_ADD_FMT_1_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_1_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u16.c index 99b5c3a..f6f8b9d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u16.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_2(T) +DEF_SAT_U_ADD_FMT_2_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_2_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u32.c index 13f5954..da8c3eb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u32.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_2(T) +DEF_SAT_U_ADD_FMT_2_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_2_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u64.c index cdbea7b..03f5960 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u64.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_2(T) +DEF_SAT_U_ADD_FMT_2_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_2_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u8.c index 508531c..af898e55 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-2-u8.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_2 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_2(T) +DEF_SAT_U_ADD_FMT_2_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_2_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u16.c index bd935dc..7862a48 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u16.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_3 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_3(T) +DEF_SAT_U_ADD_FMT_3_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_3_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u32.c index deccf9a..d2fbcf2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u32.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_3 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_3(T) +DEF_SAT_U_ADD_FMT_3_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_3_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u64.c index 4f99367..23b5488 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u64.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_3 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_3(T) +DEF_SAT_U_ADD_FMT_3_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_3_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u8.c index 670932f..b5931d4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-3-u8.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_3 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_3(T) +DEF_SAT_U_ADD_FMT_3_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_3_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u16.c index 33a595d..a9937a7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u16.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_4 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_4(T) +DEF_SAT_U_ADD_FMT_4_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_4_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u32.c index 8a5b7c1..966831a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u32.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_4 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_4(T) +DEF_SAT_U_ADD_FMT_4_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_4_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u64.c index fa20aae..08db7a1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u64.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_4 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_4(T) +DEF_SAT_U_ADD_FMT_4_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_4_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u8.c index 083d6e5..f7bbb5a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-4-u8.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_4 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_4(T) +DEF_SAT_U_ADD_FMT_4_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_4_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u16.c index a1d5d70..da1782d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u16.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_5(T) +DEF_SAT_U_ADD_FMT_5_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_5_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u32.c index 7608e71..524106a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u32.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_5(T) +DEF_SAT_U_ADD_FMT_5_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_5_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u64.c index 496ab58..62fdd25 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u64.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_5(T) +DEF_SAT_U_ADD_FMT_5_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_5_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u8.c index 936028c..334eb04 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-5-u8.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_5 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_5(T) +DEF_SAT_U_ADD_FMT_5_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_5_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u16.c index d304288..28a2fb8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u16.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint16_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6 +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_6(T) +DEF_SAT_U_ADD_FMT_6_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 65534, 65534, }, - { 1, 65534, 65535, }, - { 2, 65534, 65535, }, - { 0, 65535, 65535, }, - { 1, 65535, 65535, }, - { 2, 65535, 65535, }, - { 65535, 65535, 65535, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_6_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u32.c index 1a1ea59..3b19af3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u32.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint32_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6 +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_6(T) +DEF_SAT_U_ADD_FMT_6_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 4294967294, 4294967294, }, - { 1, 4294967294, 4294967295, }, - { 2, 4294967294, 4294967295, }, - { 0, 4294967295, 4294967295, }, - { 1, 4294967295, 4294967295, }, - { 2, 4294967295, 4294967295, }, - { 4294967295, 4294967295, 4294967295, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_6_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u64.c index dc977d5..f35334a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u64.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint64_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6 +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_6(T) +DEF_SAT_U_ADD_FMT_6_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 18446744073709551614u, 18446744073709551614u, }, - { 1, 18446744073709551614u, 18446744073709551615u, }, - { 2, 18446744073709551614u, 18446744073709551615u, }, - { 0, 18446744073709551615u, 18446744073709551615u, }, - { 1, 18446744073709551615u, 18446744073709551615u, }, - { 2, 18446744073709551615u, 18446744073709551615u, }, - { 18446744073709551615u, 18446744073709551615u, 18446744073709551615u, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_6_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u8.c index 8bc204e..e04fbf0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-6-u8.c @@ -1,25 +1,15 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" +#include "sat_arith_data.h" -#define T uint8_t -#define RUN_SAT_BINARY RUN_SAT_U_ADD_FMT_6 +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) -DEF_SAT_U_ADD_FMT_6(T) +DEF_SAT_U_ADD_FMT_6_WRAP(T1) -T test_data[][3] = { - /* arg_0, arg_1, expect */ - { 0, 0, 0, }, - { 0, 1, 1, }, - { 1, 1, 2, }, - { 0, 254, 254, }, - { 1, 254, 255, }, - { 2, 254, 255, }, - { 0, 255, 255, }, - { 1, 255, 255, }, - { 2, 255, 255, }, - { 255, 255, 255, }, -}; +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_6_WRAP(T1, x, y) -#include "scalar_sat_binary.h" +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c new file mode 100644 index 0000000..3363220 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint16_t +#define T2 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c new file mode 100644 index 0000000..bc4ca2f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint16_t +#define T2 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c new file mode 100644 index 0000000..04abd95 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint32_t +#define T2 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c new file mode 100644 index 0000000..c514a86 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define T2 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U16_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c new file mode 100644 index 0000000..b1a644b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define T2 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U32_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c new file mode 100644 index 0000000..8664ffa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define T2 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_7_WRAP(T2, T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_7_FROM_U64_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u16.c new file mode 100644 index 0000000..aaf13be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_8_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_8_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u32.c new file mode 100644 index 0000000..0ec8d90 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_8_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_8_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u64.c new file mode 100644 index 0000000..f367f67 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_8_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_8_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u8.c new file mode 100644 index 0000000..0fd4036 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-8-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_8_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_8_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u16.c new file mode 100644 index 0000000..4289e2a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint16_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_9_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_9_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u32.c new file mode 100644 index 0000000..d3dd52e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint32_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_9_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_9_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u64.c new file mode 100644 index 0000000..a9f0964 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint64_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_9_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_9_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u8.c new file mode 100644 index 0000000..91cdb7e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-9-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define T1 uint8_t +#define DATA TEST_BINARY_DATA_WRAP(T1, usadd) +#define T TEST_BINARY_STRUCT_DECL(T1, usadd) + +DEF_SAT_U_ADD_FMT_9_WRAP(T1) + +#define RUN_BINARY(x, y) RUN_SAT_U_ADD_FMT_9_WRAP(T1, x, y) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u16.c index 3c31ac3..b6388dc 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm3_uint16_t_fmt_1: -** addi\s+[atx][0-9]+,\s*a0,\s*3 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_1(uint16_t, 3) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u32.c index c6b352c..cae6796 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm7_uint32_t_fmt_1: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*a0,\s*7 -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_1(uint32_t, 7) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u64.c index 1d9df3c..f9d6939 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm8_uint64_t_fmt_1: -** addi\s+[atx][0-9]+,\s*a0,\s*8 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_1(uint64_t, 8) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u8.c index 101acd8..d90209a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-1-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm9_uint8_t_fmt_1: -** addi\s+[atx][0-9]+,\s*a0,\s*9 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_1(uint8_t, 9) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u16.c index ac57cc9..a34194d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm3_uint16_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*3 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_2(uint16_t, 3) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u32.c index 6aca60c..9a801d2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm7_uint32_t_fmt_2: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*a0,\s*7 -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_2(uint32_t, 7) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u64.c index d041724..2eb57a3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm8_uint64_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*8 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_2(uint64_t, 8) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u8.c index 7baeb8d..363b2df8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-2-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm9_uint8_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*9 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_2(uint8_t, 9) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u16.c index 6dbabf6..aaf1209 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm3_uint16_t_fmt_3: -** addi\s+[atx][0-9]+,\s*a0,\s*3 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_3(uint16_t, 3) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u32.c index 1c52b21..e430b37 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm7u_uint32_t_fmt_3: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*a0,\s*7 -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_3(uint32_t, 7u) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u64.c index ef60ce2..aef5c58 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm8ull_uint64_t_fmt_3: -** addi\s+[atx][0-9]+,\s*a0,\s*8 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_3(uint64_t, 8ull) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u8.c index 81a4b21..039d982 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-3-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm9_uint8_t_fmt_3: -** addi\s+[atx][0-9]+,\s*a0,\s*9 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_3(uint8_t, 9) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u16.c index 2f6c0460..baf70c3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u16.c @@ -1,21 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm3_uint16_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*3 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*48 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_4(uint16_t, 3) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u32.c index 1fc9a50..a4bfe50 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm7u_uint32_t_fmt_4: -** slli\s+[atx][0-9]+,\s*a0,\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*a0,\s*7 -** slli\s+[atx][0-9]+,\s*[atx][0-9],\s*32 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_4(uint32_t, 7u) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u64.c index 0ca423c..f355de6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm8ull_uint64_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*8 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_4(uint64_t, 8ull) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u8.c index c8a43fa..54880d7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-4-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_add_imm9_uint8_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*9 -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** neg\s+[atx][0-9]+,\s*[atx][0-9]+ -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_ADD_IMM_FMT_4(uint8_t, 9) /* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u16.c index 090c765..e715bb0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u32.c index 8dade74..8b8b475 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u64.c index ace2df8..f6f6408 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u8.c index 0ce546f..f2154fc 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-1-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u16.c index 7b6bd73..8e3aa83 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u32.c index 8024152..403cf14 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u64.c index 4a76dbb..17eca5e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u8.c index 8e8759c..9a277a1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-2-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u16.c index 64924a6..2068037 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u32.c index 04f3217..5f8f1e6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u64.c index 8ef6c14..c574521 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u8.c index 8867361..6b9439a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-3-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u16.c index 0b75206..224c3ae 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u32.c index e548d0c..5c03e1b7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u64.c index 4335d82..1ceacd2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u8.c index 872923e..aef253c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_add_imm-run-4-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u128.c new file mode 100644 index 0000000..cd6f2f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u32.c new file mode 100644 index 0000000..7409232 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u64.c new file mode 100644 index 0000000..43ab563 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u128.c new file mode 100644 index 0000000..dea9f6d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c new file mode 100644 index 0000000..fa3758a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "mulhu" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c new file mode 100644 index 0000000..b1bf4fa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u64-from-u128.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint64_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ +/* { dg-final { scan-assembler-times "mulhu" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u128.c new file mode 100644 index 0000000..dfc9d2e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u128.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint128_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u16.c new file mode 100644 index 0000000..ec79e5d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u16.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint16_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u32.c new file mode 100644 index 0000000..eb95184 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u32.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint32_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u64.c new file mode 100644 index 0000000..ee41593 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc -mabi=ilp32d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u16-from-u64.c new file mode 100644 index 0000000..b1d33a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u16-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint16_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u32-from-u64.c new file mode 100644 index 0000000..af5ffecf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u32-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint32_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u8-from-u64.c new file mode 100644 index 0000000..d65cab0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-2-u8-from-u64.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ + +#include "sat_arith.h" + +#define NT uint8_t +#define WT uint64_t + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +/* { dg-final { scan-tree-dump-times ".SAT_MUL" 1 "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c new file mode 100644 index 0000000..79f6297 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u32.c new file mode 100644 index 0000000..e212391 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c new file mode 100644 index 0000000..79d3fb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint16_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c new file mode 100644 index 0000000..e5a9462 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c new file mode 100644 index 0000000..ad63db3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint32_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c new file mode 100644 index 0000000..cbe2a22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u64-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint64_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c new file mode 100644 index 0000000..1f54c30 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u128.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint128_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u16.c new file mode 100644 index 0000000..f5a0ab5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u16.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint16_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u32.c new file mode 100644 index 0000000..32074a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u32.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint32_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c new file mode 100644 index 0000000..16ca905 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c @@ -0,0 +1,16 @@ +/* { dg-do run { target { rv32 || rv64 } } } */ +/* { dg-additional-options "-std=c99" } */ + +#include "sat_arith.h" +#include "sat_arith_data.h" + +#define NT uint8_t +#define WT uint64_t +#define NAME usmul +#define DATA TEST_BINARY_DATA_WRAP(NT, NAME) +#define T TEST_BINARY_STRUCT_DECL_WRAP(NT, NAME) +#define RUN_BINARY(x, y) RUN_SAT_U_MUL_FMT_1_WRAP(NT, WT, x, y) + +DEF_SAT_U_MUL_FMT_1_WRAP(NT, WT) + +#include "scalar_sat_binary_run_xxx.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u16.c index eb140ae..66a439e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_1(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u32.c index 59ad242..6f40907 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_1: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_1(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u64.c index 47a8382..647fc6d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_1(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u8.c index f01317b..a344c58 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_1: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_1(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u16.c index 4b7bd3a..87fb1fc 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_10: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_10(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u32.c index a28213f..280236a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_10: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_10(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u64.c index 432da0c..4b7d339 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_10: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_10(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u8.c index 0658d38..191c3a5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_10: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_10(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u16.c index 2e4b875..9dc41e1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_11: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_11(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u32.c index 61fb80f..475f944 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_11: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_11(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u64.c index 2a28b1f..61e3584 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_11: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_11(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u8.c index 3033844..7a61055 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_11: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_11(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u16.c index 9cb86df..c4d21cb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_12: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_12(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u32.c index babe768..56beb83 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_12: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_12(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u64.c index 294ef5a..1bef3fe 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_12: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_12(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u8.c index 8b8f924..9004281 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_12: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_12(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u16.c index e724752..7b85582 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_2(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u32.c index 9240406..cfdf66c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_2: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_2(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u64.c index 3e1efba..3898817 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_2(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u8.c index 600688a..3318211 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_2: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_2(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u16.c index bb2d0b7..61bb5e5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_3(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u32.c index 06635df..73bfa99 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_3: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_3(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u64.c index ac485da..24d1e69 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_3(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u8.c index cdc8776..5523112 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_3: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_3(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u16.c index 407ff8f..fb6a604 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_4(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u32.c index cb2cd05..0f7e2d3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_4: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_4(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u64.c index 0ce6269..c762647 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_4(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u8.c index 302206a..3e5d2e6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_4: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_4(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u16.c index ce2758f..ab1b375 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_5: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_5(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u32.c index d33cef3..1b8ce84 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_5: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_5(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u64.c index 1bf1e97..3fc4e7a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_5: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_5(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u8.c index b2ed732..5c34ead 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_5: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_5(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u16.c index 20614ec..70dc6ec 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_6: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_6(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u32.c index 5d7adfd..cc36036 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_6: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_6(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u64.c index b3c6f8d..ea633ff 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_6: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_6(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u8.c index a4f92a8..7c4747a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_6: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_6(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u16.c index ebfe673..cac8471 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_7: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_7(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u32.c index 9884123..18b8e5f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_7: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_7(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u64.c index 67236d5..f5ade61 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_7: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_7(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u8.c index 549d9d2..9b528a4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_7: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_7(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u16.c index aa5aec7..0d093c3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_8: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_8(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u32.c index 89a8cc9..f04ea1d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_8: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_8(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u64.c index a52948d..17dd8f3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_8: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_8(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u8.c index 5606733..b043207 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_8: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_8(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u16.c index 984867a..19b1a5b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u16.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint16_t_fmt_9: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_FMT_9(uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u32.c index d1109a4..a0026a1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u32.c @@ -1,22 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint32_t_fmt_9: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** slli\s+a1,\s*a1,\s*32 -** srli\s+a1,\s*a1,\s*32 -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_FMT_9(uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u64.c index a9acf15..01c155e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint64_t_fmt_9: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*a0,\s*a1 -** addi\s+a0,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_FMT_9(uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u8.c index 47551fa..7b94d40 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u8.c @@ -1,18 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_uint8_t_fmt_9: -** sub\s+[atx][0-9]+,\s*a0,\s*a1 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_FMT_9(uint8_t) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u16.c index 1534cf9..20e14d6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u32.c index 5c60d28..1a0c394 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u64.c index 403764c..ee348b3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u8.c index 931420a..216af86 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-1-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u16.c index ae87544..109539d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u32.c index 43414ae..9e35fa2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u64.c index 3ef70a1..3c7c8db 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u8.c index 2a157f0..df291e2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-10-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u16.c index 534795c..88dded4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u32.c index 4d0a34f..239b422 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u64.c index d74d10d..9a524fd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u8.c index 949bd0d..b9b84ea 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-11-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u16.c index 80cce95..91bd9de 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u32.c index 3ecd19c..eaaa256 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u64.c index 2d7bfc4..04d2a20 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u8.c index 209965c..caedfe7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-12-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u16.c index 7deaae9a5..06a44f1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u32.c index d9b1d5c..9d38c9c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u64.c index 2774c23..5c10409 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u8.c index 6fa44ca..0ff9827 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-2-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u16.c index ea52ff4..aab99ca 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u32.c index fdea891..5231d6f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u64.c index 164ee77..d7462a8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u8.c index 724adf9..5da7838 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-3-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u16.c index 9b57861..8e69888 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u32.c index df2eece..9b22dda 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u64.c index 09e9ac3..abd0a95 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u8.c index c8ae7a6..d92c0e1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-4-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u16.c index 9f575a47..b404bfd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u32.c index c370455..b746712 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u64.c index 22d82f9..da90b7a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u8.c index b282311..38dcabe 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-5-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u16.c index e0dda45..fd55bec 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u32.c index dfd95ef..2e810dd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u64.c index 7cac446..e86eebc 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u8.c index 0b4cbdb..e749bb5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-6-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u16.c index 10c65fe..eb57d55 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u32.c index e3b4dde..c1a5bcf 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u64.c index 6e93fcf..27d4b82 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u8.c index d101d28..feb56e1 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-7-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u16.c index 4e50e3f..a22f1df 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u32.c index 3c8f78d..b98931d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u64.c index 932596a..dff3c0a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u8.c index 1f74562..d2f3126 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-8-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u16.c index 66a82f2..3740099 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u32.c index a54b5c3..b6ae459 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u64.c index 97943b3e..55198d6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u8.c index ab8b475..ce73d26 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-run-9-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-1.c index 573ef11..475b31e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-1.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm32768_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*32768 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint16_t, 32768) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-2.c index 0fefbe7..a984f84b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-2.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm65533_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-3 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint16_t, 65533) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-3.c index ad6d4f9..b2930d4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-3.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm65534_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-2 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint16_t, 65534) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-4.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-4.c index 02dcbc5..362cf48 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-4.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-4.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint16_t, 1) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16.c index 7346fbb..9f17082 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm6_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*6 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint16_t, 6) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-1.c index c7dac8a..801a86e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-1.c @@ -1,23 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm2147483648_uint32_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint32_t, 2147483648) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-2.c index 4320db3..e044768 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-2.c @@ -1,24 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm68719476732_uint32_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-4 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint32_t, 68719476732) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-3.c index 765d13c..5518064 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-3.c @@ -1,24 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm4294967294_uint32_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-2 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint32_t, 4294967294) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-4.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-4.c index ca11cf1..a4cb49b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-4.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-4.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint32_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint32_t, 1) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32.c index 3711930..64808bf 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm255_uint32_t_fmt_1: -** li\s+[atx][0-9]+,\s*255 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint32_t, 255) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-1.c index 2e490f0..493a14d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-1.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm18446744073709551614u_uint64_t_fmt_1: -** li\s+[atx][0-9]+,\s*-2 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint64_t, 18446744073709551614u) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-2.c index 45baa8f..4faae52 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-2.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint64_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint64_t, 1) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64.c index a29a6e9..3f993fd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm82_uint64_t_fmt_1: -** li\s+[atx][0-9]+,\s*82 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint64_t, 82) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-1.c index d1c6e94..a0d9235 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-1.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm128_uint8_t_fmt_1: -** li\s+[atx][0-9]+,\s*128 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint8_t, 128) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-2.c index 4c8cf90..67dae03 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-2.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm253_uint8_t_fmt_1: -** li\s+[atx][0-9]+,\s*253 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint8_t, 253) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c index b958f5e..0054532 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm254_uint8_t_fmt_1: -** li\s+[atx][0-9]+,\s*254 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint8_t, 254) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c index 1951ec5..c12b560 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint8_t_fmt_1: -** li\s+[atx][0-9]+,\s*1 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint8_t, 1) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c index 86d0b39..ce9f495 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm11_uint8_t_fmt_1: -** li\s+[atx][0-9]+,\s*11 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_1(uint8_t, 11) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c index 31c1bb8..93d7169 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm32768_uint16_t_fmt_2: -** li\s+[atx][0-9]+,\s*32768 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 32768) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c index 68807b9..8ac2ce8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm65533_uint16_t_fmt_2: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-3 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 65533) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c index 62deec1..740d6ac 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c @@ -1,18 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint16_t_fmt_2: -** snez\s+[atx][0-9]+,\s*a0 -** subw\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 1) /* { dg-final { scan-tree-dump-not ".SAT_SUB" "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c index f789fee..c82c478 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm6_uint16_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*-6 -** sltiu\s+a0,\s*[atx][0-9]+,\s*6 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint16_t, 6) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c index 2f4a439..b2f690a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c @@ -1,23 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm2147483648_uint32_t_fmt_2: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2147483648) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c index dcfba62..e62010b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c @@ -1,24 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm68719476732_uint32_t_fmt_2: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-4 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 68719476732) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c index a3f48f7..dd063d8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c @@ -1,16 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint32_t_fmt_2: -** snez\s+[atx][0-9]+,\s*a0 -** subw\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ - DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 1) /* { dg-final { scan-tree-dump-not ".SAT_SUB" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c index 0bd8ddc..c0eb8a7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm255_uint32_t_fmt_2: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** addi\s+[atx][0-9]+,\s*a0,\s*-255 -** sltiu\s+a0,\s*[atx][0-9]+,\s*255 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 255) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c index 7b6d857..ed69313 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c @@ -1,16 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint64_t_fmt_2: -** snez\s+[atx][0-9]+,\s*a0 -** sub\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ - DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 1) /* { dg-final { scan-tree-dump-not ".SAT_SUB" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c index c334665..fb7db13 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c @@ -1,18 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm82_uint64_t_fmt_2: -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-82 -** sltiu\s+a0,\s*[atx][0-9]+,\s*82 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 82) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c index 26e77f0..efe6c00 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm128_uint8_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*-128 -** sltiu\s+a0,\s*[atx][0-9]+,\s*128 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 128) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c index c5ac1b0..1262648 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm253_uint8_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*-253 -** sltiu\s+a0,\s*[atx][0-9]+,\s*253 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 253) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c index ee59b5a..108daf2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c @@ -1,17 +1,8 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm1_uint8_t_fmt_2: -** snez\s+[atx][0-9]+,\s*a0 -** subw\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ - DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 1) /* { dg-final { scan-tree-dump-not ".SAT_SUB" "optimized" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c index 69dcc2a..784a97b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm11_uint8_t_fmt_2: -** addi\s+[atx][0-9]+,\s*a0,\s*-11 -** sltiu\s+a0,\s*[atx][0-9]+,\s*11 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint8_t, 11) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c index f312362..0f16f9c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm32769_uint16_t_fmt_3: -** li\s+[atx][0-9]+,\s*32768 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 32769) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c index fa9a9ef..49daab5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm65533_uint16_t_fmt_3: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-3 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 65533) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c index b98de41..30fc2bf 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm6_uint16_t_fmt_3: -** li\s+[atx][0-9]+,\s*6 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint16_t, 6) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c index 79457a3..2d3c63d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c @@ -1,24 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm2147483649_uint32_t_fmt_3: -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 2147483649) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c index 2e8426e..8d96c00 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c @@ -1,24 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm68719476732_uint32_t_fmt_3: -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-4 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 68719476732) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c index 845218c..c06c441 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm255_uint32_t_fmt_3: -** li\s+[atx][0-9]+,\s*255 -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint32_t, 255) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c index ee2fbf8..4d2b96d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm82_uint64_t_fmt_3: -** li\s+[atx][0-9]+,\s*82 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint64_t, 82) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c index 8cc81e2..8c3eb14 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm134_uint8_t_fmt_3: -** li\s+[atx][0-9]+,\s*134 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 134) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c index 8d8c70b..b02d832 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm253_uint8_t_fmt_3: -** li\s+[atx][0-9]+,\s*253 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 253) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c index 348d75b..d8e0a69 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm11_uint8_t_fmt_3: -** li\s+[atx][0-9]+,\s*11 -** sub\s+[atx][0-9]+,\s*[atx][0-9]+,\s*a0 -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_3(uint8_t, 11) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c index 089c168..8f3726f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm32768_uint16_t_fmt_4: -** li\s+[atx][0-9]+,\s*32768 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 32768) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c index b96e3f3..56c377e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c @@ -1,22 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm65533_uint16_t_fmt_4: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-3 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 65533) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c index 5c209bc..29c6b86 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c @@ -1,20 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm6_uint16_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*-6 -** sltiu\s+a0,\s*[atx][0-9]+,\s*6 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint16_t, 6) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c index 2f4a439..b2f690a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c @@ -1,23 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm2147483648_uint32_t_fmt_2: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*31 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 2147483648) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c index dcfba62..e62010b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c @@ -1,24 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm68719476732_uint32_t_fmt_2: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** li\s+[atx][0-9]+,\s*1 -** slli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-4 -** sub\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint32_t, 68719476732) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c index ee1ad9a..6cfb1e4c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c @@ -1,21 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm255_uint32_t_fmt_4: -** slli\s+a0,\s*a0,\s*32 -** srli\s+a0,\s*a0,\s*32 -** addi\s+[atx][0-9]+,\s*a0,\s*-255 -** sltiu\s+a0,\s*[atx][0-9]+,\s*255 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** sext\.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint32_t, 255) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c index c334665..fb7db13 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c @@ -1,18 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm82_uint64_t_fmt_2: -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-82 -** sltiu\s+a0,\s*[atx][0-9]+,\s*82 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_2(uint64_t, 82) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c index 3fe4103..49a4150 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm128_uint8_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*-128 -** sltiu\s+a0,\s*[atx][0-9]+,\s*128 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 128) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c index 18dc505..1022de2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm253_uint8_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*-253 -** sltiu\s+a0,\s*[atx][0-9]+,\s*253 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 253) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c index 5c40f32..48aaeb2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c @@ -1,19 +1,10 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_sub_imm11_uint8_t_fmt_4: -** addi\s+[atx][0-9]+,\s*a0,\s*-11 -** sltiu\s+a0,\s*[atx][0-9]+,\s*11 -** addi\s+a0,\s*a0,\s*-1 -** and\s+a0,\s*a0,\s*[atx][0-9]+ -** andi\s+a0,\s*a0,\s*0xff -** ret -*/ DEF_SAT_U_SUB_IMM_FMT_4(uint8_t, 11) /* { dg-final { scan-tree-dump-times ".SAT_SUB " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u16.c index 2bc3be3..a193d88 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u32.c index b1d1ee3..e1dd81c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u64.c index 2539d75..a71526c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u8.c index 5091872..4fedf96 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-1-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u16.c index 0f4f9e4..f990c43 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u32.c index ea15d85..44d5e88 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u64.c index 612da92..91ea986 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u8.c index fc38095..7da49eb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-2-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u16.c index 150ab2a..8c44ee0 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u32.c index c7d2850..f5c4e5a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u64.c index 6bf5cd2..393f7f6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u8.c index dfef1f2..e46463b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-3-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u16.c index 610e021..3062e0f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u32.c index 1d9e0cb..e621cd2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u64.c index f864a67..cfc96bf 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u8.c index 603f2ee..771ec4a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-run-4-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u16.c index b73290a..d368621 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u16.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_1(uint16_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u32.c index 8af803f..02ca992 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u32.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint32_t_fmt_1: -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_TRUNC_FMT_1(uint32_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u64.c index 1c887d4..cc01abd 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint8_t_fmt_1: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_1(uint8_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u8.c index 6bcf64b..e28ee5c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-1-u8.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint16_t_to_uint8_t_fmt_1: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_1(uint8_t, uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u16.c index 8a35e72..59302cb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u16.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint16_t_fmt_1: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_1(uint16_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u32.c index a3b52de..735ea7e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u32.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint16_t_to_uint8_t_fmt_2: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_2(uint8_t, uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u64.c index b9b43f1..8fd3f43 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u64.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint16_t_fmt_2: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_2(uint16_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u8.c index 7ed3623..bb4ecc5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-2-u8.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint8_t_fmt_1: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_1(uint8_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u16.c index 7572c9e..e476897 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u16.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint8_t_fmt_2: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_2(uint8_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u32.c index d83b5dd..524d625 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u32.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint8_t_fmt_2: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_2(uint8_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u64.c index b7202f9..ba8b238 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u64.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint16_t_fmt_2: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_2(uint16_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u8.c index e90b853..cba8573 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-3-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint32_t_fmt_2: -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_TRUNC_FMT_2(uint32_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u16.c index e8655b9..5852028 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u16.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint16_t_fmt_3: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_3(uint16_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u32.c index 41e676a..5d5cf97 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u32.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint32_t_fmt_3: -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_TRUNC_FMT_3(uint32_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u64.c index 32eeb88..866e240 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u64.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint8_t_fmt_3: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_3(uint8_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u8.c index 5d043ce..f3adfb6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-4-u8.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint16_t_to_uint8_t_fmt_3: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_3(uint8_t, uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u16.c index 7e5906b..4e132a9 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u16.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint16_t_fmt_3: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_3(uint16_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u32.c index e1b0acd..893f43e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u32.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint16_t_to_uint8_t_fmt_4: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_4(uint8_t, uint16_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u64.c index 618d50bd..5c0c7a7e 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u64.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint16_t_fmt_4: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_4(uint16_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u8.c index c9a9a4c..395bb1b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-5-u8.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint8_t_fmt_3: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_3(uint8_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u16.c index 418cdc8..8f20c8f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u16.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint32_t_to_uint8_t_fmt_4: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_4(uint8_t, uint32_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u32.c index 4903a04..f7e7ff2 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u32.c @@ -1,17 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint8_t_fmt_4: -** sltiu\s+[atx][0-9]+,\s*a0,\s*255 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff -** ret -*/ DEF_SAT_U_TRUNC_FMT_4(uint8_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u64.c index 6f8191c..2d9b6a6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u64.c @@ -1,20 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint16_t_fmt_4: -** li\s+[atx][0-9]+,\s*65536 -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** slli\s+a0,\s*a0,\s*48 -** srli\s+a0,\s*a0,\s*48 -** ret -*/ DEF_SAT_U_TRUNC_FMT_4(uint16_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u8.c index 24bb846..4fa81fe 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-6-u8.c @@ -1,19 +1,9 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */ #include "sat_arith.h" -/* -** sat_u_trunc_uint64_t_to_uint32_t_fmt_4: -** li\s+[atx][0-9]+,\s*-1 -** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*32 -** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+ -** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1 -** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+ -** sext.w\s+a0,\s*a0 -** ret -*/ DEF_SAT_U_TRUNC_FMT_4(uint32_t, uint64_t) /* { dg-final { scan-tree-dump-times ".SAT_TRUNC " 1 "optimized" } } */ +/* { dg-final { scan-assembler-not "\.L\[0-9\]+" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u16.c index a5f43e9..72c175c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u32.c index a76ae08..aef195a 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u64.c index d05ea79..4517418 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u8.c index adaa421..2e51023 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-1-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u16.c index 38fcba3..8ea83d6 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u32.c index 93705f9..1d0dd5b 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u64.c index c116484..f69968c 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u8.c index 4fbdc91..dcff0b4 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-2-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u16.c index 2281610..33f46ec 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u32.c index 126c97c..b9c4617 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u64.c index 61ad79d..21755a7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u8.c index 4142e87..bcf2081 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-3-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u16.c index 8952c06..69f5352 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u32.c index 8952c06..69f5352 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u64.c index 20ceda6..f001c39 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u8.c index 7011e50..1394d9f 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-4-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u16.c index e868da1..de5d723 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u32.c index 7f52283fb..c345bfa 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u64.c index ee13f0a..8ca8cc7 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u8.c index 8471c76..54e00e8 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-5-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u16.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u16.c index f056bd4..a957cc3 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u16.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u16.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u32.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u32.c index 96c06eb..9691b4d 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u32.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u32.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u64.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u64.c index 1623e52..ff2c2a5 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u64.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u64.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u8.c b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u8.c index a1b8a5f..918eabb 100644 --- a/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u8.c +++ b/gcc/testsuite/gcc.target/riscv/sat/sat_u_trunc-run-6-u8.c @@ -1,4 +1,4 @@ -/* { dg-do run { target { riscv_v } } } */ +/* { dg-do run { target { rv32 || rv64 } } } */ /* { dg-additional-options "-std=c99" } */ #include "sat_arith.h" diff --git a/gcc/testsuite/gcc.target/riscv/ventana-16122.c b/gcc/testsuite/gcc.target/riscv/ventana-16122.c new file mode 100644 index 0000000..59e6467 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/ventana-16122.c @@ -0,0 +1,19 @@ +/* { dg-do compile { target { rv64 } } } */ + +extern void NG (void); +typedef signed char int8_t; +typedef signed short int16_t; +typedef signed int int32_t; +void f74(void) { + int16_t x309 = 0x7fff; + volatile int32_t x310 = 0x7fffffff; + int8_t x311 = 59; + int16_t x312 = -0x8000; + static volatile int32_t t74 = 614992577; + + t74 = (x309==((x310^x311)%x312)); + + if (t74 != 0) { NG(); } else { ; } + +} + diff --git a/gcc/testsuite/gcc.target/riscv/xor-synthesis-1.c b/gcc/testsuite/gcc.target/riscv/xor-synthesis-1.c new file mode 100644 index 0000000..c630a79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xor-synthesis-1.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gb -mabi=lp64d" } */ + +unsigned long foo(unsigned long src) { return src ^ 0xffffffffefffffffUL; } + +/* { dg-final { scan-assembler-times "\\sbinvi\t" 1 } } */ +/* { dg-final { scan-assembler-times "\\snot\t" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/xor-synthesis-2.c b/gcc/testsuite/gcc.target/riscv/xor-synthesis-2.c new file mode 100644 index 0000000..25457d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xor-synthesis-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gb -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ + +unsigned long foo(unsigned long src) { return src ^ 0x8800000000000007; } + +/* xfailed until we remove mvconst_internal. */ +/* { dg-final { scan-assembler-times "\\sbinvi\t" 2 { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times "\\sxori\t" 1 { xfail *-*-* } } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/xor-synthesis-3.c b/gcc/testsuite/gcc.target/riscv/xor-synthesis-3.c new file mode 100644 index 0000000..765904b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xor-synthesis-3.c @@ -0,0 +1,8 @@ +/* { dg-do compile { target { rv64 } } } */ +/* { dg-options "-march=rv64gb -mabi=lp64d" } */ + +unsigned long foo(unsigned long src) { return src ^ 0x8c00000000000001; } + +/* { dg-final { scan-assembler-times "\\srori\t" 2 } } */ +/* { dg-final { scan-assembler-times "\\sxori\t" 1 } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c index 6746c31..38966fe 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-xtheadfmv-medany.c @@ -35,6 +35,4 @@ double foo (int i, int j) return z; } -/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */ -/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mth\.fmv\.hw\.x\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c index fb1ac2b..f0d9c80 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx-zfa-medany.c @@ -35,6 +35,4 @@ double foo (int i, int j) return z; } -/* { dg-final { scan-assembler-not {\mth\.flrd\M} } } */ -/* { dg-final { scan-assembler-times {\mlw\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mfmvp\.d\.x\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mth\.flrd\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c index 9b4e237..81b240e 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv-fmv.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { rv32 } } } */ /* { dg-options "-march=rv32gc_xtheadfmv -mabi=ilp32d" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz"} } */ double ll2d (long long ll) diff --git a/gcc/testsuite/gcc.target/riscv/xtheadint-push-pop.c b/gcc/testsuite/gcc.target/riscv/xtheadint-push-pop.c index dc5609c..167fa15 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadint-push-pop.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadint-push-pop.c @@ -20,12 +20,6 @@ void func_machine (void) /* { dg-final { scan-assembler-times {\mth\.ipop\M} 2 { target { rv32 } } } } */ -__attribute__ ((interrupt ("user"))) -void func_usr (void) -{ - f (); -} - __attribute__ ((interrupt ("supervisor"))) void func_supervisor (void) { diff --git a/gcc/testsuite/gcc.target/riscv/zalrsc.c b/gcc/testsuite/gcc.target/riscv/zalrsc.c new file mode 100644 index 0000000..19a26bf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zalrsc.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64imfd_zalrsc -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } {"-O0"} } */ + +/* lr.w/sc.w */ +int *i; +int lr_sc(int v) +{ + return __atomic_exchange_4(i, v, __ATOMIC_RELAXED); +} + +/* { dg-final { scan-assembler-times {\mlr.w} 1 } } */ +/* { dg-final { scan-assembler-times {\msc.w} 1 } } */ +/* { dg-final { scan-assembler-not {"mv\t"} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c index c123bb5..69914db 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-slliuw.c +++ b/gcc/testsuite/gcc.target/riscv/zba-slliuw.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ long foo (long i) diff --git a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c index f85c20e..3121cb6 100644 --- a/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c +++ b/gcc/testsuite/gcc.target/riscv/zbb-rol-ror-03.c @@ -10,7 +10,7 @@ unsigned int rol(unsigned int rs1, unsigned int rs2) } unsigned int ror(unsigned int rs1, unsigned int rs2) { - int shamt = rs2 & (64 - 1); + int shamt = rs2 & (32 - 1); return (rs1 >> shamt) | (rs1 << ((32 - shamt) & (32 - 1))); } diff --git a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c index 5a52adc..150cfd7 100644 --- a/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c +++ b/gcc/testsuite/gcc.target/riscv/zfa-fmovh-fmovp.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32g_zfa -mabi=ilp32 -O0" } */ +/* { dg-options "-march=rv32g_zfa -mabi=ilp32 -O0 -mtune=sifive-p400-series" } */ double foo(long long a) { diff --git a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c new file mode 100644 index 0000000..1ad1b77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mtune=generic" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mtune=generic" { target { rv32 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-O3" } } */ + +#define N 10000 + +int primitiveSemantics_compare_reg_reg_return_reg_reg_00(int *a, int min_v) +{ + int last = 0; + + for (int i = 0; i < N; i++) + { + if (a[i] < min_v) + last = a[i]; + } + return last; +} + +/* { dg-final { scan-assembler-times {\mczero\.nez\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-1.c b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-1.c new file mode 100644 index 0000000..3602626 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i_zilsd -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +long long y; +long long foo(long long x) +{ + return y + x; +} + +/* { dg-final { scan-assembler-times "ld\t" 1 } } */ +/* { dg-final { scan-assembler-not "lw\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-2.c b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-2.c new file mode 100644 index 0000000..3adcd21 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen-split-subreg-2.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i_zilsd -mabi=ilp32" } */ + +long long y; +long long foo(long long x) +{ + return y >> x; +} +/* TODO: We should not split that 64 bit load into two 32 bit load if we have + zilsd, but we split that during the expand time, so it's hard to fix via cost + model turning, we could either fix that for expander, or...combine those two + 32 bit load back later. */ +/* { dg-final { scan-assembler-times "ld\t" 1 { xfail riscv*-*-* } } } */ + +/* Os and Oz will use libcall, so the 64 bit load won't be split. */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Oz" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zilsd-code-gen.c b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen.c new file mode 100644 index 0000000..9155622 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zilsd-code-gen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i_zilsd -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +long long foo1(long long *a) +{ + return *a; +} + +long long g; + +void foo2(long long a) +{ + g = a; +} + +/* { dg-final { scan-assembler-times "ld\t" 1 } } */ +/* { dg-final { scan-assembler-times "sd\t" 1 } } */ |