diff options
Diffstat (limited to 'gcc')
30 files changed, 485 insertions, 15 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index c838fcd..8d412b6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,141 @@ +2025-04-24 Jakub Jelinek <jakub@redhat.com> + Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + PR target/119873 + * config/s390/s390.cc (s390_call_saved_register_used): Don't return + true if default definition of PARM_DECL SSA_NAME of the same register + is passed in call saved register. + (s390_function_ok_for_sibcall): Adjust comment. + +2025-04-24 Jan Hubicka <hubicka@ucw.cz> + + PR target/119919 + * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost): Account + correctly cond_expr and min/max when one of operands is 0 or -1. + +2025-04-24 Jan Hubicka <hubicka@ucw.cz> + + PR ipa/119924 + * ipa-cp.cc (update_counts_for_self_gen_clones): Use nonzero_p. + (update_profiling_info): Likewise. + (update_specialized_profile): Likewise. + +2025-04-24 Richard Sandiford <richard.sandiford@arm.com> + + PR target/119610 + * config/aarch64/aarch64.cc (aarch64_allocate_and_probe_stack_space): + Add a bytes_below_sp parameter and use it to calculate the CFA + offsets. Attach the first SVE CFA note to the move into the + associated temporary register. + (aarch64_allocate_and_probe_stack_space): Update calls accordingly. + Start out with bytes_per_sp set to the frame size and decrement + it after each allocation. + +2025-04-24 Kyrylo Tkachov <ktkachov@nvidia.com> + + * opts.cc (validate_ipa_reorder_locality_lto_partition): Check opts + instead of opts_set for x_flag_ipa_reorder_for_locality. + (finish_options): Update call site. + +2025-04-24 Kyrylo Tkachov <ktkachov@nvidia.com> + + * common.opt (LTO_PARTITION_DEFAULT): Delete. + (flto-partition=): Change default back to balanced. + * flag-types.h (lto_partition_model): Remove LTO_PARTITION_DEFAULT. + * opts.cc (validate_ipa_reorder_locality_lto_partition): + Check opts_set->x_flag_lto_partition instead of LTO_PARTITION_DEFAULT. + (finish_options): Remove handling of LTO_PARTITION_DEFAULT. + +2025-04-24 Jakub Jelinek <jakub@redhat.com> + + PR debug/119711 + * dwarf2out.h (struct dw_val_node): Add u member. + (struct dw_loc_descr_node): Remove dw_loc_opc, dtprel, + frame_offset_rel and dw_loc_addr members. + (dw_loc_opc, dw_loc_dtprel, dw_loc_frame_offset_rel, dw_loc_addr): + Define. + (struct dw_attr_struct): Remove dw_attr member. + (dw_attr): Define. + * dwarf2out.cc (loc_descr_equal_p_1): Use dw_loc_dtprel instead of + dtprel. + (output_loc_operands, new_addr_loc_descr, loc_checksum, + loc_checksum_ordered): Likewise. + (resolve_args_picking_1): Use dw_loc_frame_offset_rel instead of + frame_offset_rel. + (loc_list_from_tree_1): Likewise. + (resolve_addr_in_expr): Use dw_loc_dtprel instead of dtprel. + (copy_deref_exprloc): Copy val_class, val_entry and v members + instead of whole dw_loc_oprnd1 and dw_loc_oprnd2. + (optimize_string_length): Copy val_class, val_entry and v members + instead of whole dw_attr_val. + (hash_loc_operands): Use dw_loc_dtprel instead of dtprel. + (compare_loc_operands, compare_locs): Likewise. + +2025-04-24 liuhongt <hongtao.liu@intel.com> + + PR target/103750 + * config/i386/sse.md (*<avx512>_cmp<mode>3_and15): New define_insn. + (*<avx512>_ucmp<mode>3_and15): Ditto. + (*<avx512>_cmp<mode>3_and3): Ditto. + (*avx512vl_ucmpv2di3_and3): Ditto. + (*<avx512>_cmp<V48H_AVX512VL:mode>3_zero_extend<SWI248x:mode>): + Change operands[3] predicate to <cmp_imm_predicate>. + (*<avx512>_cmp<V48H_AVX512VL:mode>3_zero_extend<SWI248x:mode>_2): + Ditto. + (*<avx512>_cmp<mode>3): Add GET_MODE_NUNITS (<MODE>mode) >= 8 + to the condition. + (*<avx512>_ucmp<mode>3): Ditto. + (V48_AVX512VL_4): New mode iterator. + (VI48_AVX512VL_4): Ditto. + (V8_AVX512VL_2): Ditto. + +2025-04-23 Jan Hubicka <hubicka@ucw.cz> + + * ipa-cp.cc (base_count): Remove. + (struct caller_statistics): Rename n_hot_calls to n_interesting_calls; + add called_without_ipa_profile. + (init_caller_stats): Update. + (cs_interesting_for_ipcp_p): New function. + (gather_caller_stats): collect n_interesting_calls and + called_without_profile. + (ipcp_cloning_candidate_p): Use n_interesting-calls rather then hot. + (good_cloning_opportunity_p): Rewrite heuristics when IPA profile is + present + (estimate_local_effects): Update. + (value_topo_info::propagate_effects): Update. + (compare_edge_profile_counts): Remove. + (ipcp_propagate_stage): Do not collect base_count. + (get_info_about_necessary_edges): Record whether function is called + without profile. + (decide_about_value): Update. + (ipa_cp_cc_finalize): Do not initialie base_count. + * profile-count.cc (profile_count::operator*): New. + (profile_count::operator*=): New. + * profile-count.h (profile_count::operator*): Declare + (profile_count::operator*=): Declare. + * params.opt: Remove ipa-cp-profile-count-base. + * doc/invoke.texi: Likewise. + +2025-04-23 Jan Hubicka <hubicka@ucw.cz> + + * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost): Cost truth_value + exprs. + +2025-04-23 liuhongt <hongtao.liu@intel.com> + + * config/i386/predicates.md (vector_or_0_or_1s_operand): New predicate. + (nonimm_or_0_or_1s_operand): Ditto. + * config/i386/sse.md (vcond_mask_<mode><sseintvecmodelower>): + Extend the predicate of operands1 to accept 0 or allones + operands. + (vcond_mask_<mode><sseintvecmodelower>): Ditto. + (vcond_mask_v1tiv1ti): Ditto. + (vcond_mask_<mode><sseintvecmodelower>): Ditto. + * config/i386/i386.md (mov<mode>cc): Ditto for operands[2] and + operands[3]. + * config/i386/i386-expand.cc (ix86_expand_sse_fp_minmax): + Force immediate_operand to register. + 2025-04-22 Jan Hubicka <hubicka@ucw.cz> * config/i386/i386.cc (ix86_vector_costs::add_stmt_cost): Add special cases diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 1041049..c872ff4 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20250423 +20250425 diff --git a/gcc/cobol/ChangeLog b/gcc/cobol/ChangeLog index 27c31c1..d7d8596 100644 --- a/gcc/cobol/ChangeLog +++ b/gcc/cobol/ChangeLog @@ -1,3 +1,20 @@ +2025-04-24 Robert Dubner <rdubner@symas.com> + + * genapi.cc: (initialize_variable_internal): Change TRACE1 formatting. + (create_and_call): Repair RETURN-CODE processing. + (mh_source_is_group): Repair run-time IF type comparison. + (psa_FldLiteralA): Change TRACE1 formatting. + (parser_symbol_add): Eliminate unnecessary code. + * genutil.cc: Eliminate SET_EXCEPTION_CODE macro. + (get_data_offset_dest): Repair set_exception_code logic. + (get_data_offset_source): Likewise. + (get_binary_value): Likewise. + (refer_refmod_length): Likewise. + (refer_fill_depends): Likewise. + (refer_offset_dest): Likewise. + (refer_size_dest): Likewise. + (refer_offset_source): Likewise. + 2025-04-16 Bob Dubner <rdubner@symas.com> PR cobol/119759 diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index b34409a..15df22d 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -218,6 +218,37 @@ static const riscv_implied_info_t riscv_implied_info[] = { return subset_list->xlen () == 32 && subset_list->lookup ("f"); }}, + {"zca", "c", + [] (const riscv_subset_list *subset_list) -> bool + { + /* For RV32 Zca implies C for one of these combinations of + extensions: Zca, F_Zca_Zcf and FD_Zca_Zcf_Zcd. */ + if (subset_list->xlen () == 32) + { + if (subset_list->lookup ("d")) + return subset_list->lookup ("zcf") && subset_list->lookup ("zcd"); + + if (subset_list->lookup ("f")) + return subset_list->lookup ("zcf"); + + return true; + } + + /* For RV64 Zca implies C for one of these combinations of + extensions: Zca and FD_Zca_Zcd (Zcf is not available + for RV64). */ + if (subset_list->xlen () == 64) + { + if (subset_list->lookup ("d")) + return subset_list->lookup ("zcd"); + + return true; + } + + /* Do nothing for future RV128 specification. Behaviour + for this case is not yet well defined. */ + return false; + }}, {"smaia", "ssaia"}, {"smstateen", "ssstateen"}, diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc index d59e87b..91ce801 100644 --- a/gcc/config/gcn/gcn.cc +++ b/gcc/config/gcn/gcn.cc @@ -6587,8 +6587,8 @@ gcn_hsa_declare_function_name (FILE *file, const char *name, if (avgpr % vgpr_block_size) avgpr += vgpr_block_size - (avgpr % vgpr_block_size); - fputs ("\t.rodata\n" - "\t.p2align\t6\n" + switch_to_section (readonly_data_section); + fputs ("\t.p2align\t6\n" "\t.amdhsa_kernel\t", file); assemble_name (file, name); fputs ("\n", file); @@ -6707,7 +6707,7 @@ gcn_hsa_declare_function_name (FILE *file, const char *name, fputs (" .end_amdgpu_metadata\n", file); #endif - fputs ("\t.text\n", file); + switch_to_section (current_function_section ()); fputs ("\t.align\t256\n", file); fputs ("\t.type\t", file); assemble_name (file, name); diff --git a/gcc/config/s390/s390.cc b/gcc/config/s390/s390.cc index 0e9140e..e3edf85 100644 --- a/gcc/config/s390/s390.cc +++ b/gcc/config/s390/s390.cc @@ -14524,7 +14524,17 @@ s390_call_saved_register_used (tree call_expr) gcc_assert (REG_NREGS (r) == 1); if (!call_used_or_fixed_reg_p (REGNO (r))) - return true; + { + rtx parm; + if (TREE_CODE (parameter) == SSA_NAME + && SSA_NAME_IS_DEFAULT_DEF (parameter) + && SSA_NAME_VAR (parameter) + && TREE_CODE (SSA_NAME_VAR (parameter)) == PARM_DECL + && (parm = DECL_INCOMING_RTL (SSA_NAME_VAR (parameter))) + && rtx_equal_p (parm_rtx, parm)) + break; + return true; + } } } } diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index d9f0298..cd128e2 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2025-04-24 Jason Merrill <jason@redhat.com> + + PR c++/116954 + * contracts.cc (remove_contract_attributes): Return early if + not enabled. + 2025-04-22 Nathaniel Shead <nathanieloshead@gmail.com> * name-lookup.cc (lookup_imported_hidden_friend): Remove diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h index 7798efb..856202c 100644 --- a/gcc/cp/cp-tree.h +++ b/gcc/cp/cp-tree.h @@ -6755,8 +6755,14 @@ struct GTY((chain_next ("%h.next"))) tinst_level { /* The location where the template is instantiated. */ location_t locus; - /* errorcount + sorrycount when we pushed this level. */ - unsigned short errors; + /* errorcount + sorrycount when we pushed this level. If the value + overflows, it will always seem like we currently have more errors, so we + will limit template recursion even from non-erroneous templates. In a TU + with over 32k errors, that's fine. */ + unsigned short errors : 15; + + /* set in pop_tinst_level if there have been errors since we pushed. */ + bool had_errors : 1; /* Count references to this object. If refcount reaches refcount_infinity value, we don't increment or decrement the diff --git a/gcc/cp/pt.cc b/gcc/cp/pt.cc index a71705f..e8d342f 100644 --- a/gcc/cp/pt.cc +++ b/gcc/cp/pt.cc @@ -11418,6 +11418,7 @@ push_tinst_level_loc (tree tldcl, tree targs, location_t loc) new_level->targs = targs; new_level->locus = loc; new_level->errors = errorcount + sorrycount; + new_level->had_errors = false; new_level->next = NULL; new_level->refcount = 0; new_level->path = new_level->visible = nullptr; @@ -11468,6 +11469,9 @@ pop_tinst_level (void) /* Restore the filename and line number stashed away when we started this instantiation. */ input_location = current_tinst_level->locus; + if (unsigned errs = errorcount + sorrycount) + if (errs > current_tinst_level->errors) + current_tinst_level->had_errors = true; set_refcount_ptr (current_tinst_level, current_tinst_level->next); --tinst_depth; } @@ -11487,7 +11491,7 @@ reopen_tinst_level (struct tinst_level *level) set_refcount_ptr (current_tinst_level, level); pop_tinst_level (); - if (current_tinst_level) + if (current_tinst_level && !current_tinst_level->had_errors) current_tinst_level->errors = errorcount+sorrycount; tree decl = level->maybe_get_node (); @@ -28072,7 +28076,9 @@ instantiate_pending_templates (int retries) tree instantiation = reopen_tinst_level ((*t)->tinst); bool complete = false; - if (TYPE_P (instantiation)) + if (limit_bad_template_recursion (instantiation)) + /* Do nothing. */; + else if (TYPE_P (instantiation)) { if (!COMPLETE_TYPE_P (instantiation)) { diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index bda22d1..7c6a415 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,13 @@ +2025-04-23 Andre Vehreschild <vehre@gcc.gnu.org> + + PR fortran/119200 + * check.cc (gfc_check_lcobound): Use locus from intrinsic_where. + (gfc_check_image_index): Same. + (gfc_check_num_images): Same. + (gfc_check_team_number): Same. + (gfc_check_this_image): Same. + (gfc_check_ucobound): Same. + 2025-04-22 Andre Vehreschild <vehre@gcc.gnu.org> * match.cc (match_exit_cycle): Allow to exit team block. diff --git a/gcc/m2/ChangeLog b/gcc/m2/ChangeLog index eeb5f66..5290f7c 100644 --- a/gcc/m2/ChangeLog +++ b/gcc/m2/ChangeLog @@ -1,3 +1,39 @@ +2025-04-24 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/119915 + * gm2-libs/FormatStrings.mod (PerformFormatString): Handle + the %u and %x format specifiers in a similar way to the %d + specifier. Avoid using Slice and use Copy instead. + +2025-04-24 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/119914 + * gm2-compiler/M2Check.mod (checkConstMeta): Add check for + Ztype, Rtype and Ctype and unbounded arrays. + (IsZRCType): New procedure function. + (isZRC): Add comment. + * gm2-compiler/M2Quads.mod: + * gm2-compiler/M2Range.mod (gdbinit): New procedure. + (BreakWhenRangeCreated): Ditto. + (CheckBreak): Ditto. + (InitRange): Call CheckBreak. + (Init): Add gdbhook and initialize interactive watch point. + * gm2-compiler/SymbolTable.def (GetNthParamAnyClosest): New + procedure function. + * gm2-compiler/SymbolTable.mod (BreakSym): Remove constant. + (BreakSym): Add Variable. + (stop): Remove. + (gdbhook): New procedure. + (BreakWhenSymCreated): Ditto. + (CheckBreak): Ditto. + (NewSym): Call CheckBreak. + (Init): Add gdbhook and initialize interactive watch point. + (MakeProcedure): Replace guarded call to stop with CheckBreak. + (GetNthParamChoice): New procedure function. + (GetNthParamOrdered): Ditto. + (GetNthParamAnyClosest): Ditto. + (GetOuterModuleScope): Ditto. + 2025-04-11 Gaius Mulley <gaiusmod2@gmail.com> PR modula2/119735 diff --git a/gcc/modulo-sched.cc b/gcc/modulo-sched.cc index 08af5a9..0023467 100644 --- a/gcc/modulo-sched.cc +++ b/gcc/modulo-sched.cc @@ -356,7 +356,13 @@ doloop_register_get (rtx_insn *head, rtx_insn *tail) reg = XEXP (condition, 0); else if (GET_CODE (XEXP (condition, 0)) == PLUS && REG_P (XEXP (XEXP (condition, 0), 0))) - reg = XEXP (XEXP (condition, 0), 0); + { + if (CONST_INT_P (XEXP (condition, 1)) + && INTVAL (XEXP (condition, 1)) == -1) + reg = XEXP (XEXP (condition, 0), 0); + else + return NULL_RTX; + } else gcc_unreachable (); diff --git a/gcc/po/ChangeLog b/gcc/po/ChangeLog index b1537f7..96da438 100644 --- a/gcc/po/ChangeLog +++ b/gcc/po/ChangeLog @@ -1,3 +1,11 @@ +2025-04-23 Joseph Myers <josmyers@redhat.com> + + * gcc.pot: Regenerate. + +2025-04-23 Joseph Myers <josmyers@redhat.com> + + * sv.po: Update. + 2025-04-09 Joseph Myers <josmyers@redhat.com> * de.po: Update. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index af49263..47666a9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,97 @@ +2025-04-24 Jakub Jelinek <jakub@redhat.com> + Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org> + + PR target/119873 + * gcc.target/s390/pr119873-1.c: New test. + * gcc.target/s390/pr119873-2.c: New test. + * gcc.target/s390/pr119873-3.c: New test. + * gcc.target/s390/pr119873-4.c: New test. + +2025-04-24 Robert Dubner <rdubner@symas.com> + + * cobol.dg/group1/declarative_1.cob: Adjust for repaired exception logic. + +2025-04-24 Jan Hubicka <hubicka@ucw.cz> + + * gcc.target/i386/pr119919.c: New test. + +2025-04-24 Richard Sandiford <richard.sandiford@arm.com> + + PR target/119610 + * g++.dg/torture/pr119610.C: New test. + * g++.target/aarch64/sve/pr119610-sve.C: Likewise. + +2025-04-24 Jakub Jelinek <jakub@redhat.com> + + PR c++/110343 + * gcc.dg/raw-string-1.c: New test. + +2025-04-24 Kyrylo Tkachov <ktkachov@nvidia.com> + + * gcc.dg/completion-2.c: Remove check for default. + +2025-04-24 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/119915 + * gm2/pimlib/run/pass/format2.mod: New test. + +2025-04-24 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/avx512vl-pr103750-1.c: New test. + * gcc.target/i386/avx512f-pr96891-3.c: Adjust testcase. + * gcc.target/i386/avx512f-vpcmpgtuq-1.c: Ditto. + * gcc.target/i386/avx512vl-vpcmpeqq-1.c: Ditto. + * gcc.target/i386/avx512vl-vpcmpequq-1.c: Ditto. + * gcc.target/i386/avx512vl-vpcmpgeq-1.c: Ditto. + * gcc.target/i386/avx512vl-vpcmpgeuq-1.c: Ditto. + * gcc.target/i386/avx512vl-vpcmpgtq-1.c: Ditto. + * gcc.target/i386/avx512vl-vpcmpgtuq-1.c: Ditto. + * gcc.target/i386/avx512vl-vpcmpleq-1.c: Ditto. + * gcc.target/i386/avx512vl-vpcmpleuq-1.c: Ditto. + * gcc.target/i386/avx512vl-vpcmpltq-1.c: Ditto. + * gcc.target/i386/avx512vl-vpcmpltuq-1.c: Ditto. + * gcc.target/i386/avx512vl-vpcmpneqq-1.c: Ditto. + * gcc.target/i386/avx512vl-vpcmpnequq-1.c: Ditto. + +2025-04-24 Gaius Mulley <gaiusmod2@gmail.com> + + PR modula2/119914 + * gm2/pim/fail/constintarraybyte.mod: New test. + +2025-04-23 Dimitar Dimitrov <dimitar@dinux.eu> + + * g++.dg/no-stack-protector-attr-3.C: Require effective target + fstack_protector. + +2025-04-23 Jan Hubicka <hubicka@ucw.cz> + + * gcc.dg/ipa/ipa-clone-4.c: New file. + * gcc.dg/tree-prof/ipa-cp-1.c: New file. + +2025-04-23 Christophe Lyon <christophe.lyon@linaro.org> + + PR target/71233 + * gcc.target/aarch64/advsimd-intrinsics/vld1x2.c: Enable on arm. + * gcc.target/aarch64/advsimd-intrinsics/vld1x3.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vld1x4.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vst1x2.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vst1x3.c: Likewise. + * gcc.target/aarch64/advsimd-intrinsics/vst1x4.c: Likewise. + +2025-04-23 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> + + * g++.dg/eh/pr119507.C: Skip on sparc*-*-solaris2* && !gas. + +2025-04-23 Tamar Christina <tamar.christina@arm.com> + + PR target/119286 + * gcc.dg/vect/vect-early-break_38.c: Force -march=gfx908 for amdgcn. + +2025-04-23 liuhongt <hongtao.liu@intel.com> + + * gcc.target/i386/blendv-to-maxmin.c: New test. + * gcc.target/i386/blendv-to-pand.c: New test. + 2025-04-22 Jan Hubicka <hubicka@ucw.cz> * gcc.target/i386/pr89618-2.c: XFAIL. diff --git a/gcc/testsuite/g++.dg/template/recurse5.C b/gcc/testsuite/g++.dg/template/recurse5.C new file mode 100644 index 0000000..7bfe523 --- /dev/null +++ b/gcc/testsuite/g++.dg/template/recurse5.C @@ -0,0 +1,17 @@ +// Test that we don't bother to instantiate add since there were errors in +// checked_add. + +template <class T> T add (T t) { return t+1; } // { dg-bogus "no match" } + +template <class T> T checked_add (T t) +{ + add (t); + return t+1; // { dg-error "no match" } +} + +struct A { }; + +int main() +{ + checked_add (A()); +} diff --git a/gcc/testsuite/gcc.dg/pr116479.c b/gcc/testsuite/gcc.dg/pr116479.c new file mode 100644 index 0000000..dbbcb9a --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr116479.c @@ -0,0 +1,26 @@ +/* PR 116479 */ +/* { dg-do run { target { bitint } } } */ +/* { dg-additional-options "-O -funroll-loops -finline-stringops -fmodulo-sched --param=max-iterations-computation-cost=637924687 -std=c23" } */ + +#if __BITINT_MAXWIDTH__ >= 13577 +_BitInt (13577) b; + +void +foo (char *ret) +{ + __builtin_memset (&b, 4, 697); + *ret = 0; +} +#endif + +int +main () +{ +#if __BITINT_MAXWIDTH__ >= 13577 + char x; + foo (&x); + for (unsigned i = 0; i < sizeof (x); i++) + if (x != 0) + __builtin_abort (); +#endif +} diff --git a/gcc/testsuite/gcc.target/riscv/arch-25.c b/gcc/testsuite/gcc.target/riscv/arch-25.c index 3be4ade..9201883 100644 --- a/gcc/testsuite/gcc.target/riscv/arch-25.c +++ b/gcc/testsuite/gcc.target/riscv/arch-25.c @@ -2,4 +2,4 @@ /* { dg-options "-march=rv64i_zcf -mabi=lp64" } */ int foo() {} /* { dg-error "'-march=rv64i_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ -/* { dg-error "'-march=rv64i_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ +/* { dg-error "'-march=rv64ic_zca_zcf': zcf extension supports in rv32 only" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-1.c b/gcc/testsuite/gcc.target/riscv/attribute-c-1.c new file mode 100644 index 0000000..5627e16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-1.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32i_zca -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_c2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-2.c b/gcc/testsuite/gcc.target/riscv/attribute-c-2.c new file mode 100644 index 0000000..4c7d5f9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-2.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32if_zca -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_zicsr2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-3.c b/gcc/testsuite/gcc.target/riscv/attribute-c-3.c new file mode 100644 index 0000000..7ff68f7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32if_zca_zcf -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-4.c b/gcc/testsuite/gcc.target/riscv/attribute-c-4.c new file mode 100644 index 0000000..ef59b65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-4.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32ifd_zca_zcf -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-5.c b/gcc/testsuite/gcc.target/riscv/attribute-c-5.c new file mode 100644 index 0000000..14e9551 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-5.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32ifd_zca_zcf_zcd -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0_zcf1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-6.c b/gcc/testsuite/gcc.target/riscv/attribute-c-6.c new file mode 100644 index 0000000..30cda55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-6.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64i_zca -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_c2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-7.c b/gcc/testsuite/gcc.target/riscv/attribute-c-7.c new file mode 100644 index 0000000..b06388b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-7.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64ifd_zca -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_d2p2_zicsr2p0_zca1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-c-8.c b/gcc/testsuite/gcc.target/riscv/attribute-c-8.c new file mode 100644 index 0000000..fa76050 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-c-8.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64ifd_zca_zcd -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_d2p2_c2p0_zicsr2p0_zca1p0_zcd1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c index e477414..fc86dbe 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-1.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c index 7008eb5..4504158 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-2.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcf1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c index 89ebaaf..4ffc051 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-3.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c b/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c index cacbcaa..7ee8de2 100644 --- a/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c +++ b/gcc/testsuite/gcc.target/riscv/attribute-zce-4.c @@ -3,4 +3,4 @@ void foo(){} -/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_f2p2_c2p0_zicsr2p0_zca1p0_zcb1p0_zce1p0_zcmp1p0_zcmt1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/s390/pr119873-5.c b/gcc/testsuite/gcc.target/s390/pr119873-5.c new file mode 100644 index 0000000..b5a7950 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/pr119873-5.c @@ -0,0 +1,11 @@ +/* PR target/119873 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -m31 -mzarch" } */ + +extern void foo (int x, int y, int z, long long w, int v); + +void +bar (int x, int y, int z, long long w, int v) +{ + [[gnu::musttail]] return foo (x, y, z, w, v); +} |