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2019-01-16Actually remove definitions of DEFINE_NON_INLINE_P and DEFINE_INLINE_PSimon Marchi2-4/+1
2019-01-16Do not expand macros to 'defined'Pavel I. Kryukov2-5/+7
2019-01-15sim: Fix definition of SIM_ARANGE_INLINESimon Marchi2-1/+5
2019-01-03Add 'extern C' if simulator is written in C++Павел Крюков2-0/+12
2019-01-01Update copyright year range in all GDB files.Joel Brobecker618-618/+618
2018-12-18sim: Don't overwrite stored errno in sim_syscall_multiAndrew Burgess2-5/+5
2018-12-06sim/cris: Fix references to cgen cpu directoryAndrew Burgess2-10/+13
2018-12-06sim/opcodes: Allow use of out of tree cgen source directoryAndrew Burgess9-40/+100
2018-10-30[src/erc32] Use ncurses instead of termcap on Cygwin tooJoel Sherrill3-10/+15
2018-10-05or1k: Add the l.muld, l.muldu, l.macu, l.msbu insnsRichard Henderson12-233/+1058
2018-09-28Change "xor" name in cpu_core to allow building with iso646.h or C++ compilerКомпан, Вячеслав Олегович3-4/+14
2018-07-21Update my e-mail address, limit maintenance to MIPS I-IV ISAsMaciej W. Rozycki2-1/+6
2018-07-19Remove myself from target-specific MAINTAINERSDJ Delorie2-4/+8
2018-07-14sim: Add Stafford Horne as or1k maintainer.Stafford Horne2-0/+5
2018-06-19Bump to autoconf 2.69 and automake 1.15.1Simon Marchi132-17835/+19994
2018-06-18config: Sync with GCCSimon Marchi32-974/+1037
2018-05-09PR22069, Several instances of register accidentally spelled as regsiterAlan Modra3-2/+7
2018-01-22MAINTAINERS: Update my company e-mail addressMaciej W. Rozycki2-1/+5
2018-01-02Fix compile time warning (in the ARM simulator) about a print statement with ...Nick Clifton2-1/+7
2018-01-02Update copyright year range in all GDB filesJoel Brobecker618-618/+618
2017-12-12sim: testsuite: add testsuite for or1k simPeter Gavin28-0/+6510
2017-12-12sim: or1k: add autoconf generated filesStafford Horne5-0/+16427
2017-12-12sim: or1k: add cgen generated filesStafford Horne11-0/+27536
2017-12-12sim: or1k: add or1k target to simStafford Horne11-0/+1637
2017-12-12sim: cgen: add MUL2OFSI and MUL1OFSI functions (needed for OR1K l.mul[u])Peter Gavin2-0/+25
2017-12-12sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])Peter Gavin5-5/+149
2017-11-01FT32: support for FT32B processor - part 2/2James Bowman2-7/+19
2017-10-12FT32: support for FT32B processor - part 1James Bowman2-7/+15
2017-10-12Add myself as ft32 maintainer for sim.James Bowman2-0/+5
2017-10-03Update my email address.Jim Wilson2-1/+5
2017-09-21[SIM, ARM] Fix build failureYao Qi2-1/+8
2017-09-06Honor an existing CC_FOR_BUILD in the environment for sim.John Baldwin59-202/+434
2017-09-04Define an error function in the PPC simulator library.John Baldwin2-0/+15
2017-09-04Fix simulatorAnthony Green2-7/+16
2017-08-29Fix simulation of MSP430's open system call.Jozef Lawrynowicz2-10/+30
2017-06-02Correct check for endiannessMichael Eager2-1/+5
2017-05-24Refactor disassembler selectionYao Qi2-1/+9
2017-04-22Fix ldn/stn multiple instructions. Fix testcases with unaligned data.Jim Wilson14-202/+454
2017-04-08Add support for fcvtl and fcvtl2.Jim Wilson4-0/+112
2017-04-08Support the fcmXX zero instructions.Jim Wilson4-0/+232
2017-03-25Fix bug with cmn/adds where C flag was incorrectly set.Jim Wilson4-1/+27
2017-03-03Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.Jim Wilson5-9/+89
2017-02-25Add missing smov support, and clean up existing umov support.Jim Wilson4-75/+227
2017-02-25Add missing cnt (popcount) instruction support.Jim Wilson4-0/+94
2017-02-19Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.Jim Wilson8-36/+157
2017-02-14Add self to aarch64 maintainers. Fix mla instruction.Jim Wilson6-49/+128
2017-02-14Fix bit/bif instructions.Jim Wilson4-10/+107
2017-02-14Add ldn/stn single support, fix ldnr support.Jim Wilson6-269/+698
2017-02-13sim: use ARRAY_SIZE instead of ad-hoc sizeof calculationsMike Frysinger39-62/+141
2017-01-23Add support for cmtst.Jim Wilson4-0/+113
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