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2023-12-14RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.Jin Ma1-1/+1
2023-12-14Remove redundant Byte, Word, Dword and Qword from insn templates.Cui, Lili1-123/+123
2023-12-13Make const_1_mode print $1 in AT&T syntaxCui, Lili1-0/+2
2023-12-11LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">mengqinggang1-0/+7
2023-12-04s390: Support for jump visualization in disassemblyJens Remus3-42/+88
2023-12-01x86: allow 32-bit reg to be used with U{RD,WR}MSRJan Beulich2-4/+4
2023-12-01RISC-V: Make riscv_is_mapping_symbol stricterPatrick O'Neill1-3/+1
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu2-0/+57
2023-12-01RISC-V: Zv*: Add support for Zvkb ISA extensionChristoph Müllner1-10/+10
2023-11-30RISC-V: Avoid updating state until symbol is foundPatrick O'Neill1-12/+31
2023-11-27as: Add new estimated reciprocal instructions in LoongArch v1.1Jiajie Chen1-0/+12
2023-11-27as: Add new atomic instructions in LoongArch v1.1Jiajie Chen1-0/+42
2023-11-24RISC-V: drop leftover match_never() referencesJan Beulich1-4/+4
2023-11-24x86: shrink opcode sets tableJan Beulich2-2347/+302
2023-11-24x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possibleJan Beulich1-0/+6
2023-11-24RISC-V: reduce redundancy in sign/zero extension macro insn handlingJan Beulich1-2/+2
2023-11-24RISC-V: disallow x0 with certain macro-insnsJan Beulich2-45/+48
2023-11-24Fix building for the s390 target with clangNick Clifton1-2/+3
2023-11-23s390: Correct prno instruction nameJens Remus1-1/+1
2023-11-23s390: Add missing extended mnemonicsJens Remus2-5/+31
2023-11-23s390: Align optional operand definition to specsJens Remus1-9/+11
2023-11-23s390: Make operand table indices relative to each otherJens Remus1-82/+92
2023-11-23RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extensionJin Ma1-0/+15
2023-11-23RISC-V: Add vector mask instructions for T-Head VECTOR vendor extensionJin Ma1-0/+19
2023-11-23RISC-V: Add reductions instructions for T-Head VECTOR vendor extensionJin Ma1-0/+16
2023-11-23RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor e...Jin Ma1-0/+86
2023-11-23RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor exte...Jin Ma1-0/+36
2023-11-23RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extensionJin Ma1-0/+143
2023-11-23RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extensionJin Ma1-0/+18
2023-11-23RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extensionJin Ma1-0/+280
2023-11-23RISC-V: Add load/store instructions for T-Head VECTOR vendor extensionJin Ma1-0/+44
2023-11-23RISC-V: Add configuration-setting instructions for T-Head VECTOR vendor exten...Jin Ma1-0/+4
2023-11-23RISC-V: Add CSRs for T-Head VECTOR vendor extensionJin Ma1-2/+12
2023-11-21[opcodes] ARC + PPC: Fix -Walloc-size warningsJan-Benedict Glaw2-2/+2
2023-11-17x86: CPU-qualify {disp16} / {disp32}Jan Beulich2-3/+3
2023-11-16aarch64: Add support for VMSA feature enhancements.Srinath Parvathaneni1-0/+25
2023-11-16aarch64: Add new AT system instructions.Srinath Parvathaneni1-0/+9
2023-11-16aarch64: Add support to new features in RAS extension.Srinath Parvathaneni1-0/+14
2023-11-16aarch64: Add features to the Statistical Profiling Extension.Srinath Parvathaneni1-0/+1
2023-11-16aarch64: Add SLC target for PRFM instruction.Srinath Parvathaneni1-6/+6
2023-11-15Finalized intl-update patchesArsen Arsenovi?7-334/+2410
2023-11-10Add support for ilp32 register alias.Lulu Cai2-6/+6
2023-11-09aarch64: Fix error in THE system register checkingVictor Do Nascimento2-4/+1
2023-11-09x86: rework UWRMSR operand swappingJan Beulich2-3/+5
2023-11-09x86: do away with is_evex_encoding()Jan Beulich2-575/+585
2023-11-09x86: split insn templates' CPU fieldJan Beulich4-474/+4249
2023-11-09x86: Cpu64 handling improvementsJan Beulich3-52/+90
2023-11-09x86: Intel Core processors do not support CMPXCHG16BJan Beulich2-2/+2
2023-11-07aarch64: Add LSE128 instructionsVictor Do Nascimento4-2407/+2558
2023-11-07aarch64: Add arch support for LSE128 extensionVictor Do Nascimento1-0/+5