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| author | Jan Beulich <jbeulich@suse.com> | 2023-11-24 09:55:29 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2023-11-24 09:55:29 +0100 |
| commit | 39bb3ade816faf42ec34cc7ca962ad350cb4d16a (patch) | |
| tree | 20ebf46bd6a4f68bb3d7c6e8fcd3c4ae26f889c2 /opcodes | |
| parent | eb5e952f95423bc6ae18457ccc359c8b6c0fa387 (diff) | |
| download | binutils-39bb3ade816faf42ec34cc7ca962ad350cb4d16a.zip binutils-39bb3ade816faf42ec34cc7ca962ad350cb4d16a.tar.gz binutils-39bb3ade816faf42ec34cc7ca962ad350cb4d16a.tar.bz2 | |
x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possible
Deal with what 58bceb182740 ("x86: prefer VEX encodings over EVEX ones
when possible") left out, for being slightly less straightforward.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/i386-opc.tbl | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 167c0a0..b170d70 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1481,6 +1481,9 @@ gf2p8mulb<gfni>, 0x660f38cf, <gfni:cpu>GFNI, Modrm|<gfni:w0>|NoSuf, { RegXMM|Uns true_us:1f:C> // <Vxy> is used for VEX instructions with x/y suffixes. +// NOTE: The order of the "unnamed" ($-prefixed) entries here needs to remain +// in sync with <Exy>, for match_template()'s EVEX-to-VEX lowering to +// continue to work. <Vxy:vex:syntax:src, + $i:Vex:IntelSyntax:RegXMM|RegYMM|Unspecified|BaseIndex, + $a:Vex:ATTSyntax:RegXMM|RegYMM, + @@ -2097,6 +2100,9 @@ vpclmulhqhqdq, 0x6644/0x11, VPCLMULQDQ&(AVX|AVX512F), Modrm|Space0F3A|Vex|EVexDY // AVX512F instructions. // <Exy> is used for EVEX instructions with x/y suffixes. +// NOTE: The order of the "unnamed" ($-prefixed) entries here needs to remain +// in sync with <Vxy>, for match_template()'s EVEX-to-VEX lowering to +// continue to work. <Exy:vl:attr:sr:sae:src:dst, + $z::EVex512|Disp8MemShift=6:StaticRounding|SAE:SAE:RegZMM|Unspecified|BaseIndex:RegYMM, + $i:AVX512VL:Disp8ShiftVL|IntelSyntax:::RegXMM|RegYMM|Unspecified|BaseIndex:RegXMM, + |