aboutsummaryrefslogtreecommitdiff
path: root/gas/doc
diff options
context:
space:
mode:
Diffstat (limited to 'gas/doc')
-rw-r--r--gas/doc/as.texi61
-rw-r--r--gas/doc/c-aarch64.texi59
-rw-r--r--gas/doc/c-riscv.texi72
3 files changed, 158 insertions, 34 deletions
diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 40d45f7..1cb1fd8 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -240,7 +240,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{--gdwarf-<N>}] [@b{--gdwarf-sections}]
[@b{--gdwarf-cie-version}=@var{VERSION}]
[@b{--generate-missing-build-notes=[no|yes]}]
- [@b{--gsframe}]
+ [@b{--gsframe}] [@b{--gsframe=[no|yes]}]
[@b{--hash-size}=@var{N}]
[@b{--help}] [@b{--target-help}]
[@b{--info}] [@b{--no-info}]
@@ -260,7 +260,8 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
[@b{--sectname-subst}]
[@b{--size-check=[error|warning]}]
[@b{--statistics}]
- [@b{-v}] [@b{-version}] [@b{--version}]
+ [@b{-v}] [@b{--verbose}]
+ [@b{-version}] [@b{--version}]
[@b{-W}] [@b{--no-warn}] [@b{--warn}] [@b{--fatal-warnings}]
[@b{-w}] [@b{-x}]
[@b{-Z}] [@b{@@@var{FILE}}]
@@ -552,7 +553,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
@emph{Target RISC-V options:}
[@b{-fpic}|@b{-fPIC}|@b{-fno-pic}]
- [@b{-march}=@var{ISA}]
+ [@b{-march}=@var{ISA}|@var{Profiles}|@var{Profiles_ISA}]
[@b{-mabi}=@var{ABI}]
[@b{-mlittle-endian}|@b{-mbig-endian}]
@end ifset
@@ -778,6 +779,10 @@ symbols with the @code{STT_COMMON} type. The default can be controlled
by a configure option @option{--enable-elf-stt-common}.
@end ifset
+@item --emit-local-absolute
+Emit even pre-defined (local) absolute symbols to the outgoing symbol table.
+Note that this isn't the exact opposite of @samp{--strip-local-absolute}.
+
@item --emulation=@var{name}
If the assembler is configured to support multiple different target
configurations then this option can be used to select the desired form.
@@ -855,7 +860,11 @@ configure option.
@item --gsframe
@itemx --gsframe
-Create @var{.sframe} section from CFI directives.
+@itemx --gsframe=no
+@itemx --gsframe=yes
+Create @var{.sframe} section from CFI directives. The explicit
+@option{--gsframe=yes} option behaves the same as @option{--gsframe}.
+Generation can be suppressed with @option{--gsframe=no}.
@end ifset
@@ -975,10 +984,11 @@ assembly.
Remove local absolute symbols from the outgoing symbol table.
@item -v
-@itemx -version
+@itemx --verbose
Print the @command{as} version.
@item --version
+@itemx -version
Print the @command{as} version and exit.
@item -W
@@ -3907,6 +3917,7 @@ the same order they were declared. This may break some debuggers.
* Symbol Names:: Symbol Names
* Dot:: The Special Dot Symbol
* Symbol Attributes:: Symbol Attributes
+* Predefined Symbols:: Predefined Symbols
@end menu
@node Labels
@@ -4248,6 +4259,30 @@ Language Reference Manual} (HP 92432-90001) under the @code{IMPORT} and
@code{EXPORT} assembler directive documentation.
@end ifset
+@node Predefined Symbols
+@section Predefined Symbols
+
+Certain pre-defined symbols will be made available for use, and possibly also
+inserted in the symbol table. Because of the use of parentheses, access to
+these symbols will require quotation.
+
+Independent of the specific target, the following symbols will (perhaps
+conditionally; see each individual item) be made available:
+@itemize @bullet
+
+@item @code{GAS(version)}
+The version of the assembler, expressed as @samp{major} @code{*} 100000000
+@code{+} @samp{minor} @code{*} 1000000 @code{+} @samp{rev} @code{*} 10000.
+
+@item @code{GAS(date)}
+The date of the assembler sources (which may not be the date the assembler was
+built). This is added only for non-release versions of gas. The specific
+value probably better isn't checked for, just its defined-ness.
+
+@end itemize
+
+All symbols of the form @code{GAS(...)} are reserved for use by GNU @value{AS}.
+
@node Expressions
@chapter Expressions
@@ -4551,6 +4586,7 @@ Some machine configurations provide additional directives.
* Equiv:: @code{.equiv @var{symbol}, @var{expression}}
* Eqv:: @code{.eqv @var{symbol}, @var{expression}}
* Err:: @code{.err}
+* Errif:: @code{.errif @var{expression}}
* Error:: @code{.error @var{string}}
* Exitm:: @code{.exitm}
* Extern:: @code{.extern}
@@ -4683,6 +4719,7 @@ Some machine configurations provide additional directives.
* VTableInherit:: @code{.vtable_inherit @var{child}, @var{parent}}
@end ifset
+* Warnif:: @code{.warnif @var{expression}}
* Warning:: @code{.warning @var{string}}
* Weak:: @code{.weak @var{names}}
* Weakref:: @code{.weakref @var{alias}, @var{symbol}}
@@ -5526,6 +5563,13 @@ If @command{@value{AS}} assembles a @code{.err} directive, it will print an erro
message and, unless the @option{-Z} option was used, it will not generate an
object file. This can be used to signal an error in conditionally compiled code.
+@node Errif
+@section @code{.errif "@var{expression}"}
+@cindex errif directive
+
+Record @var{expression} for evaluation at the end of assembly. Raise an error
+if the expression evaluates to non-zero.
+
@node Error
@section @code{.error "@var{string}"}
@cindex error directive
@@ -7719,6 +7763,13 @@ parent whose addend is the value of the child symbol. As a special case the
parent name of @code{0} is treated as referring to the @code{*ABS*} section.
@end ifset
+@node Warnif
+@section @code{.warnif "@var{expression}"}
+@cindex errif directive
+
+Record @var{expression} for evaluation at the end of assembly. Raise a
+warning if the expression evaluates to non-zero.
+
@node Warning
@section @code{.warning "@var{string}"}
@cindex warning directive
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 10888d1..8f5702f 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -136,6 +136,12 @@ is enabled by default.
@item -mno-verbose-error
This option disables verbose error messages in AArch64 gas.
+@cindex @code{-menable-sysreg-checking} command-line option, AArch64
+@item -menable-sysreg-checking
+This option enables error messages that are issued if an attempt is made to
+assemble a system register access which will not execute on the target
+architecture.
+
@end table
@c man end
@@ -167,6 +173,8 @@ automatically cause those extensions to be disabled.
@tab Enable the Branch Record Buffer extension.
@item @code{chk} @tab
@tab Enable the Check Feature Status Extension.
+@item @code{cmpbr} @tab
+ @tab Enable Compare and Branch instructions.
@item @code{compnum} @tab @code{simd}
@tab Enable the complex number SIMD extensions. An alias of @code{fcma}.
@item @code{cpa} @tab
@@ -185,6 +193,12 @@ automatically cause those extensions to be disabled.
@tab Enable the F32 Matrix Multiply extension
@item @code{f64mm} @tab @code{sve}
@tab Enable the F64 Matrix Multiply extension.
+@item @code{f8f16mm} @tab @code{simd} @code{fp8}
+ @tab Enable 8-bit floating-point matrix multiply-accumulate to half-precision instructions.
+@item @code{f8f32mm} @tab @code{simd} @code{fp}
+ @tab Enable 8-bit floating-point matrix multiply-accumulate to single-precision instructions.
+@item @code{faminmax} @tab @code{simd}
+ @tab Enable the famin and famax instructions.
@item @code{fcma} @tab @code{fp16}, @code{simd}
@tab Enable the complex number SIMD extensions.
@item @code{flagm} @tab
@@ -205,6 +219,8 @@ automatically cause those extensions to be disabled.
@tab Enable Armv8.2 16-bit floating-point multiplication variant support.
@item @code{fp16} @tab @code{fp}
@tab Enable Armv8.2 16-bit floating-point support.
+@item @code{fprcvt} @tab @code{fp}
+ @tab Enable Armv9.6 fprcvt instructions.
@item @code{frintts} @tab @code{fp}
@tab Enable floating-point round to integral value instructions.
@item @code{gcs} @tab
@@ -225,20 +241,28 @@ automatically cause those extensions to be disabled.
@tab Enable Large System extensions.
@item @code{lse128} @tab @code{lse}
@tab Enable the 128-bit Atomic Instructions extension.
-@item @code{lut} @tab
+@item @code{lsfe} @tab @code{fp}
+ @tab Enable Large System Float Extension.
+@item @code{lsui} @tab
+ @tab Enable Unprivileged Load/Store instructions.
+@item @code{lut} @tab @code{simd}
@tab Enable the Lookup Table (LUT) extension.
@item @code{memtag} @tab
@tab Enable Armv8.5-A Memory Tagging Extensions.
@item @code{mops} @tab
@tab Enable Armv8.8-A memcpy and memset acceleration instructions
+@item @code{occmo} @tab
+ @tab Enable Outer Cacheable Cache Maintenance Operations.
@item @code{pan} @tab
@tab Enable Privileged Access Never support.
@item @code{pauth} @tab
@tab Enable Pointer Authentication.
+@item @code{pops} @tab
+ @tab Enable Point of Physical Storage.
@item @code{predres} @tab
- @tab Enable the Execution and Data and Prediction instructions.
+ @tab Enable execution and data prediction restriction instructions.
@item @code{predres2} @tab @code{predres}
- @tab Enable Prediction instructions.
+ @tab Enable additional prediction restriction instructions.
@item @code{profile} @tab
@tab Enable statistical profiling extensions.
@item @code{ras} @tab
@@ -275,6 +299,8 @@ automatically cause those extensions to be disabled.
@tab Enable the SME F8F16 Extension.
@item @code{sme-f8f32} @tab @code{sme2}, @code{fp8}
@tab Enable the SME F8F32 Extension.
+@item @code{sme-f16f16} @tab @code{sme2}
+ @tab Enable the SME2 F16F16 Extension.
@item @code{sme-f64f64} @tab @code{sme}
@tab Enable SME F64F64 Extension.
@item @code{sme-i16i64} @tab @code{sme}
@@ -285,8 +311,12 @@ automatically cause those extensions to be disabled.
@tab Enable SME2.
@item @code{sme2p1} @tab @code{sme2}
@tab Enable SME2.1.
+@item @code{sme2p2} @tab @code{sme2p1}
+ @tab Enable SME2.2.
@item @code{ssbs} @tab
@tab Enable Speculative Store Bypassing Safe state read and write.
+@item @code{ssve-aes} @tab @code{sme2}, @code{sve-aes}
+ @tab Enable SVE AES instructions in streaming mode.
@item @code{ssve-fp8dot2} @tab @code{sme2}, @code{fp8}
@tab Enable the Streaming SVE FP8 2-way dot product instructions.
@item @code{ssve-fp8dot4} @tab @code{sme2}, @code{fp8}
@@ -295,11 +325,19 @@ automatically cause those extensions to be disabled.
@tab Enable the Streaming SVE FP8 FMA instructions.
@item @code{sve} @tab @code{fcma}
@tab Enable the Scalable Vector Extension.
+@item @code{sve-aes} @tab @code{aes}
+ @tab Enable the SVE2 AES and PMULL Extensions.
+@item @code{sve-aes2} @tab
+@tab Enable the SVE-AES2 extension.
@item @code{sve-b16b16} @tab
@tab Enable the SVE B16B16 extension. These instructions also require either @code{+sve2} or @code{+sme2}.
+@item @code{sve-bfscale} @tab
+@tab Enable the SVE BFSCALE extension. These instructions also require either @code{+sve2} or @code{+sme2}.
+@item @code{sve-f16f32mm} @tab @code{sve}
+@tab Enable the SVE_F16F32MM extension.
@item @code{sve2} @tab @code{sve}
@tab Enable SVE2.
-@item @code{sve2-aes} @tab @code{sve2}, @code{aes}
+@item @code{sve2-aes} @tab @code{sve2}, @code{sve-aes}
@tab Enable the SVE2 AES and PMULL Extensions.
@item @code{sve2-bitperm} @tab @code{sve2}
@tab Enable the SVE2 BITPERM Extension.
@@ -309,6 +347,8 @@ automatically cause those extensions to be disabled.
@tab Enable the SVE2 SM4 Extension.
@item @code{sve2p1} @tab @code{sve2}
@tab Enable SVE2.1.
+@item @code{sve2p2} @tab @code{sve2p1}
+ @tab Enable SVE2.2.
@item @code{the} @tab
@tab Enable the Translation Hardening Extension.
@item @code{tme} @tab
@@ -317,8 +357,6 @@ automatically cause those extensions to be disabled.
@tab Enable @code{wfet} and @code{wfit} instructions.
@item @code{xs} @tab
@tab Enable the XS memory attribute extension.
-@item @code{sme-f16f16} @tab
- @tab Enable the SME2 F16F16 Extension.
@end multitable
@multitable @columnfractions .20 .80
@@ -339,6 +377,7 @@ automatically cause those extensions to be disabled.
@item @code{armv9.3-a} @tab @code{armv9.2-a}, @code{armv8.8-a}
@item @code{armv9.4-a} @tab @code{armv9.3-a}, @code{armv8.9-a}
@item @code{armv9.5-a} @tab @code{armv9.4-a}, @code{cpa}, @code{lut}, @code{faminmax}
+@item @code{armv9.6-a} @tab @code{armv9.5-a}, @code{cmpbr}, @code{fprcvt}, @code{lsui}, @code{occmo}, @code{sve2p2}
@item @code{armv8-r} @tab @code{armv8.4-a+nolor}
@end multitable
@@ -462,6 +501,14 @@ incrementally to the architecture being compiled for.
@c BBBBBBBBBBBBBBBBBBBBBBBBBB
@c CCCCCCCCCCCCCCCCCCCCCCCCCC
+@cindex @code{.cfi_mte_tagged_frame} directive, AArch64
+@item @code{.cfi_mte_tagged_frame}
+The @code{.cfi_mte_tagged_frame} directive inserts a 'G' character into the
+CIE corresponding to the current frame's FDE, meaning that the associated
+frames may modify MTE tags on the stack space they use. This information is
+intended to be used by the stack unwinder in order to properly untag stack
+frames.
+
@cindex @code{.cpu} directive, AArch64
@item .cpu @var{name}
Set the target processor. Valid values for @var{name} are the same as
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 0a92e78..ea4be32 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -41,9 +41,11 @@ Generate position-independent code
@item -fno-pic
Don't generate position-independent code (default)
-@cindex @samp{-march=ISA} option, RISC-V
-@item -march=ISA
-Select the base isa, as specified by ISA. For example -march=rv32ima.
+@cindex @samp{-march=ISA|Profiles|Profiles_ISA} option, RISC-V
+@item -march=ISA|Profiles|Profiles_ISA
+Select the base isa, as specified by ISA or Profiles or Profies_ISA.
+For example @samp{-march=rv32ima} @samp{-march=RVI20U64}
+@samp{-march=RVI20U64_d}.
If this option and the architecture attributes aren't set, then assembler
will check the default configure setting --with-arch=ISA.
@@ -179,12 +181,14 @@ instead of just
It's not expected that options are changed in this manner during regular use,
but there are a handful of esoteric cases like the one above where users need
to disable particular features of the assembler for particular code sequences.
-However, it's also useful to enable/disable the extensions for some specific
-code regions by @samp{.option arch, +-}. This is very common in the ifunc
-libraries. We can support functions which are implemented by different
-extensions in the same library, but these should not affect any file-level
-settings, like the elf architecture attribute. The complete list of option
-arguments is shown below:
+However, it's also useful to enable and reset the extensions for some specific
+code regions by @samp{.option arch, +ext} and @samp{.option arch, ISA}. Or
+use @samp{.option push} and @samp{.option pop} at the beginning and end of the
+code, so that we can indirectly turn on and off extensions in this range. This
+is very common in the ifunc libraries. We can support functions which are
+implemented by different extensions in the same library, but these should not
+affect any file-level settings, like the elf architecture attribute. The
+complete list of option arguments is shown below:
@table @code
@item push
@@ -195,9 +199,11 @@ command-line options are respected for the bulk of the file being assembled.
@item rvc
@itemx norvc
-Enables or disables the generation of compressed instructions. Instructions
-are opportunistically compressed by the RISC-V assembler when possible, but
-sometimes this behavior is not desirable, especially when handling alignments.
+Enable the generation of base compressed instructions (C extension), or
+disable the generation of all compressed instructions (C and all Zc*
+extensions). Instructions are opportunistically compressed by the RISC-V
+assembler when possible, but sometimes this behavior is not desirable,
+especially when handling alignments.
@item pic
@itemx nopic
@@ -215,17 +221,11 @@ desirable.
Enables or disables the CSR checking.
@item arch, @var{+extension[version]} [,...,@var{+extension_n[version_n]}]
-@itemx arch, @var{-extension} [,...,@var{-extension_n}]
@itemx arch, @var{ISA}
-Enables or disables the extensions for specific code region. For example,
-@samp{.option arch, +m2p0} means add m extension with version 2.0, and
-@samp{.option arch, -f, -d} means remove extensions, f and d, from the
-architecture string. Note that, @samp{.option arch, +c, -c} have the same
-behavior as @samp{.option rvc, norvc}. However, they are also undesirable
-sometimes. Besides, @samp{.option arch, -i} is illegal, since we cannot
-remove the base i extension anytime. If you want to reset the whole ISA
-string, you can also use @samp{.option arch, rv32imac} to overwrite the
-previous settings.
+Enable or reset the extensions for specific code region. For example,
+@samp{.option arch, +m2p0} means add m extension with version 2.0.
+@samp{.option arch, rv32imac} means reset and overwrite the previous settings
+by rv32imac.
@end table
@cindex INSN directives
@@ -737,7 +737,12 @@ to be recorded in the attribute as @code{RV32I2P0} in which @code{2P0} stands
for the default version of its base ISA. On the other hand, the architecture
@code{RV32G} has to be presented as @code{RV32I2P0_M2P0_A2P0_F2P0_D2P0} in
which the abbreviation @code{G} is expanded to the @code{IMAFD} combination
-with default versions of the standard extensions.
+with default versions of the standard extensions. All Profiles are expanded
+ to the mandatory extensions it includes then processing. For example,
+@code{RVI20U32} is expanded to @code{RV32I2P0} for processing, which contains
+the mandatory extensions @code{I} as it defined. And you can also combine
+Profiles with ISA use underline, like @code{RVI20U32_D} is expanded to the
+@code{RV32I2P0_F2P0_D2P0}.
@item Tag_RISCV_unaligned_access (6)
Tag_RISCV_unaligned_access is 0 for files that do not allow any unaligned
@@ -892,4 +897,25 @@ XSfCease provides an instruction to instigates power-down sequence.
It is documented in @url{https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf}.
+@item XMipsCbop
+The XMipsCbop extension provides instruction mips.pref.
+
+It is documented in @url{https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf}.
+
+@item XMipsCmov
+The XMipsCmov extension provides instruction mips.ccmov.
+
+It is documented in @url{https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf}.
+
+@item XMipsExectl
+The XMipsExectl extension provides instructions mips.ehb, mips.ihb and mips.pause.
+
+It is documented in @url{https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf}.
+
+@item XMipsSlsp
+
+The XMipsSlsp extension provides instructions mips.ldp, mips.lwp, mips.sdp and mips.swp.
+
+It is documented in @url{https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf}.
+
@end table
generated by cgit v1.1 at 2025-07-31 04:11:34 +0000