1 files changed, 53 insertions, 6 deletions
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 10888d1..8f5702f 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -136,6 +136,12 @@ is enabled by default.
 @item -mno-verbose-error
 This option disables verbose error messages in AArch64 gas.
 
+@cindex @code{-menable-sysreg-checking} command-line option, AArch64
+@item -menable-sysreg-checking
+This option enables error messages that are issued if an attempt is made to
+assemble a system register access which will not execute on the target
+architecture.
+
 @end table
 @c man end
 
@@ -167,6 +173,8 @@ automatically cause those extensions to be disabled.
  @tab Enable the Branch Record Buffer extension.
 @item @code{chk} @tab
  @tab Enable the Check Feature Status Extension.
+@item @code{cmpbr} @tab
+ @tab Enable Compare and Branch instructions.
 @item @code{compnum} @tab @code{simd}
  @tab Enable the complex number SIMD extensions.  An alias of @code{fcma}.
 @item @code{cpa} @tab
@@ -185,6 +193,12 @@ automatically cause those extensions to be disabled.
  @tab Enable the F32 Matrix Multiply extension
 @item @code{f64mm} @tab @code{sve}
  @tab Enable the F64 Matrix Multiply extension.
+@item @code{f8f16mm} @tab @code{simd} @code{fp8}
+ @tab Enable 8-bit floating-point matrix multiply-accumulate to half-precision instructions.
+@item @code{f8f32mm} @tab @code{simd} @code{fp}
+ @tab Enable 8-bit floating-point matrix multiply-accumulate to single-precision instructions.
+@item @code{faminmax} @tab @code{simd}
+ @tab Enable the famin and famax instructions.
 @item @code{fcma} @tab @code{fp16}, @code{simd}
  @tab Enable the complex number SIMD extensions.
 @item @code{flagm} @tab
@@ -205,6 +219,8 @@ automatically cause those extensions to be disabled.
  @tab Enable Armv8.2 16-bit floating-point multiplication variant support.
 @item @code{fp16} @tab @code{fp}
  @tab Enable Armv8.2 16-bit floating-point support.
+@item @code{fprcvt} @tab @code{fp}
+ @tab Enable Armv9.6 fprcvt instructions.
 @item @code{frintts} @tab @code{fp}
  @tab Enable floating-point round to integral value instructions.
 @item @code{gcs} @tab
@@ -225,20 +241,28 @@ automatically cause those extensions to be disabled.
  @tab Enable Large System extensions.
 @item @code{lse128} @tab @code{lse}
  @tab Enable the 128-bit Atomic Instructions extension.
-@item @code{lut} @tab
+@item @code{lsfe} @tab @code{fp}
+ @tab Enable Large System Float Extension.
+@item @code{lsui} @tab
+ @tab Enable Unprivileged Load/Store instructions.
+@item @code{lut} @tab @code{simd}
  @tab Enable the Lookup Table (LUT) extension.
 @item @code{memtag} @tab
  @tab Enable Armv8.5-A Memory Tagging Extensions.
 @item @code{mops} @tab
  @tab Enable Armv8.8-A memcpy and memset acceleration instructions
+@item @code{occmo} @tab
+ @tab Enable Outer Cacheable Cache Maintenance Operations.
 @item @code{pan} @tab
  @tab Enable Privileged Access Never support.
 @item @code{pauth} @tab
  @tab Enable Pointer Authentication.
+@item @code{pops} @tab
+ @tab Enable Point of Physical Storage.
 @item @code{predres} @tab
- @tab Enable the Execution and Data and Prediction instructions.
+ @tab Enable execution and data prediction restriction instructions.
 @item @code{predres2} @tab @code{predres}
- @tab Enable Prediction instructions.
+ @tab Enable additional prediction restriction instructions.
 @item @code{profile} @tab
  @tab Enable statistical profiling extensions.
 @item @code{ras} @tab
@@ -275,6 +299,8 @@ automatically cause those extensions to be disabled.
  @tab Enable the SME F8F16 Extension.
 @item @code{sme-f8f32} @tab @code{sme2}, @code{fp8}
  @tab Enable the SME F8F32 Extension.
+@item @code{sme-f16f16} @tab @code{sme2}
+ @tab Enable the SME2 F16F16 Extension.
 @item @code{sme-f64f64} @tab @code{sme}
  @tab Enable SME F64F64 Extension.
 @item @code{sme-i16i64} @tab @code{sme}
@@ -285,8 +311,12 @@ automatically cause those extensions to be disabled.
  @tab Enable SME2.
 @item @code{sme2p1} @tab @code{sme2}
  @tab Enable SME2.1.
+@item @code{sme2p2} @tab @code{sme2p1}
+ @tab Enable SME2.2.
 @item @code{ssbs} @tab
  @tab Enable Speculative Store Bypassing Safe state read and write.
+@item @code{ssve-aes} @tab @code{sme2}, @code{sve-aes}
+ @tab Enable SVE AES instructions in streaming mode.
 @item @code{ssve-fp8dot2} @tab @code{sme2}, @code{fp8}
  @tab Enable the Streaming SVE FP8 2-way dot product instructions.
 @item @code{ssve-fp8dot4} @tab @code{sme2}, @code{fp8}
@@ -295,11 +325,19 @@ automatically cause those extensions to be disabled.
  @tab Enable the Streaming SVE FP8 FMA instructions.
 @item @code{sve} @tab @code{fcma}
  @tab Enable the Scalable Vector Extension.
+@item @code{sve-aes} @tab @code{aes}
+ @tab Enable the SVE2 AES and PMULL Extensions.
+@item @code{sve-aes2} @tab
+@tab Enable the SVE-AES2 extension.
 @item @code{sve-b16b16} @tab
 @tab Enable the SVE B16B16 extension.  These instructions also require either @code{+sve2} or @code{+sme2}.
+@item @code{sve-bfscale} @tab
+@tab Enable the SVE BFSCALE extension. These instructions also require either @code{+sve2} or @code{+sme2}.
+@item @code{sve-f16f32mm} @tab @code{sve}
+@tab Enable the SVE_F16F32MM extension.
 @item @code{sve2} @tab @code{sve}
  @tab Enable SVE2.
-@item @code{sve2-aes} @tab @code{sve2}, @code{aes}
+@item @code{sve2-aes} @tab @code{sve2}, @code{sve-aes}
  @tab Enable the SVE2 AES and PMULL Extensions.
 @item @code{sve2-bitperm} @tab @code{sve2}
  @tab Enable the SVE2 BITPERM Extension.
@@ -309,6 +347,8 @@ automatically cause those extensions to be disabled.
  @tab Enable the SVE2 SM4 Extension.
 @item @code{sve2p1} @tab @code{sve2}
  @tab Enable SVE2.1.
+@item @code{sve2p2} @tab @code{sve2p1}
+ @tab Enable SVE2.2.
 @item @code{the} @tab
  @tab Enable the Translation Hardening Extension.
 @item @code{tme} @tab
@@ -317,8 +357,6 @@ automatically cause those extensions to be disabled.
  @tab Enable @code{wfet} and @code{wfit} instructions.
 @item @code{xs} @tab
  @tab Enable the XS memory attribute extension.
-@item @code{sme-f16f16} @tab
- @tab Enable the SME2 F16F16 Extension.
 @end multitable
 
 @multitable @columnfractions .20 .80
@@ -339,6 +377,7 @@ automatically cause those extensions to be disabled.
 @item @code{armv9.3-a} @tab @code{armv9.2-a}, @code{armv8.8-a}
 @item @code{armv9.4-a} @tab @code{armv9.3-a}, @code{armv8.9-a}
 @item @code{armv9.5-a} @tab @code{armv9.4-a}, @code{cpa}, @code{lut}, @code{faminmax}
+@item @code{armv9.6-a} @tab @code{armv9.5-a}, @code{cmpbr}, @code{fprcvt}, @code{lsui}, @code{occmo}, @code{sve2p2}
 @item @code{armv8-r} @tab @code{armv8.4-a+nolor}
 @end multitable
 
@@ -462,6 +501,14 @@ incrementally to the architecture being compiled for.
 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
 
+@cindex @code{.cfi_mte_tagged_frame} directive, AArch64
+@item	@code{.cfi_mte_tagged_frame}
+The @code{.cfi_mte_tagged_frame} directive inserts a 'G' character into the
+CIE corresponding to the current frame's FDE, meaning that the associated
+frames may modify MTE tags on the stack space they use.  This information is
+intended to be used by the stack unwinder in order to properly untag stack
+frames.
+
 @cindex @code{.cpu} directive, AArch64
 @item .cpu @var{name}
 Set the target processor.  Valid values for @var{name} are the same as