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| author | Victor Do Nascimento <vicdon01@e133397.arm.com> | 2024-02-27 01:32:52 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-05-16 13:22:30 +0100 |
| commit | eef66d27fcdc55c83a63a17f295409bb4a13688b (patch) | |
| tree | b9365975ccffe8a10e988a0bd7c409a6a5002926 /libctf | |
| parent | ab501c0deebc13c037f5385749b67d5186253e05 (diff) | |
| download | binutils-eef66d27fcdc55c83a63a17f295409bb4a13688b.zip binutils-eef66d27fcdc55c83a63a17f295409bb4a13688b.tar.gz binutils-eef66d27fcdc55c83a63a17f295409bb4a13688b.tar.bz2 | |
aarch64: fp8 convert and scale - add sve2 insn variants
Add the SVE2 variant of the FP8 convert and scale instructions,
enabled at assembly-time using the `+sve2+fp8' architectural
extension flag. More specifically, support is added for the
following instructions:
FP8 convert to BFloat16 (bottom/top):
-------------------------------------
- bf1cvt Z<d>.H, Z<n>.B
- bf2cvt Z<d>.H, Z<n>.B
- bf1cvtlt Z<d>.H, Z<n>.B
- bf2cvtlt Z<d>.H, Z<n>.B
FP8 convert to half-precision (bottom/top):
-------------------------------------------
- f1cvt Z<d>.H, Z<n>.B
- f2cvt Z<d>.H, Z<n>.B
- f1cvtlt Z<d>.H, Z<n>.B
- f2cvtlt Z<d>.H, Z<n>.B
BFloat16/half-precision convert, narrow and
interleave to FP8:
-------------------------------------------
- bfcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H }
- fcvtn Z<d>.B, { Z<n>1.H - Z<n>2.H }
Single-precision convert, narrow and interleave
to FP8 (bottom/top):
-----------------------------------------------
- fcvtnb Z<d>.B, { Z<n>1.S - Z<n>2.S }
- fcvtnt Z<d>.B, { Z<n>1.S - Z<n>2.S }
Diffstat (limited to 'libctf')
0 files changed, 0 insertions, 0 deletions