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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-02-06 14:59:02 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-05-16 13:22:30 +0100 |
| commit | ab501c0deebc13c037f5385749b67d5186253e05 (patch) | |
| tree | 345754fbfce0d735a03d8c20d0c0602d2c38dc4c /libctf | |
| parent | 7d0383ad39c1df982fc8a56a920d32a4c1f42625 (diff) | |
| download | binutils-ab501c0deebc13c037f5385749b67d5186253e05.zip binutils-ab501c0deebc13c037f5385749b67d5186253e05.tar.gz binutils-ab501c0deebc13c037f5385749b67d5186253e05.tar.bz2 | |
aarch64: fp8 convert and scale - Add advsimd insn variants
Add the advanced SIMD variant of the FP8 convert and scale
instructions, enabled at assembly-time using the `+fp8'
architectural extension flag. More specifically, support is
added for the following instructions:
FP8 convert to BFloat16 (vector):
---------------------------------
- bf1cvtl V<d>.8H, V<n>.8B
- bf2cvtl V<d>.8H, V<n>.8B
- bf1cvtl2 V<d>.8H, V<n>.16B
- bf2cvtl2 V<d>.8H, V<n>.16B
FP8 convert to half-precision (vector):
---------------------------------------
- f1cvtl V<d>.8H, V<n>.8B
- f2cvtl V<d>.8H, V<n>.8B
- f1cvtl2 V<d>.8H, V<n>.16B
- f2cvtl2 V<d>.8H, V<n>.16B
Single-precision to FP8 convert and narrow (vector):
----------------------------------------------------
- fcvtn V<d>.8B, V<n>.4S, V<m>.4S
- fcvtn2 V<d>.16B, V<n>.4S, V<m>.4S
Half-precision to FP8 convert and narrow (vector):
--------------------------------------------------
- fcvtn V<d>.8B, V<n>.4H, V<m>.4H
- fcvtn V<d>.16B, V<n>.8H, V<m>.8H
Floating-point adjust exponent by vector:
-----------------------------------------
- fscale V<d>.4H, V<n>.4H, V<m>.4H
- fscale V<d>.8H, V<n>.8H, V<m>.8H
- fscale V<d>.2S, V<n>.2S, V<m>.2S
- fscale V<d>.4S, V<n>.4S, V<m>.4S
- fscale V<d>.2d, V<n>.2d, V<m>.2d
Diffstat (limited to 'libctf')
0 files changed, 0 insertions, 0 deletions