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| author | Yixuan Chen <chenyixuan@iscas.ac.cn> | 2024-07-04 17:16:59 +0800 |
|---|---|---|
| committer | Vladimir Mezentsev <vladimir.mezentsev@oracle.com> | 2024-07-10 15:16:03 -0700 |
| commit | 762c38d552abbfed97c349c5e7c8ef34119b2f5e (patch) | |
| tree | f0b1d2e5cf0b78204d6ab4d0f8c7dd8c9512a5b7 /gprofng/src/collctrl.cc | |
| parent | 479edf0a6a61159486f14d5e62403f8769cc591d (diff) | |
| download | binutils-762c38d552abbfed97c349c5e7c8ef34119b2f5e.zip binutils-762c38d552abbfed97c349c5e7c8ef34119b2f5e.tar.gz binutils-762c38d552abbfed97c349c5e7c8ef34119b2f5e.tar.bz2 | |
RISC-V:[gprofng] Minimal support gprofng for riscv.
ChangeLog: Add target riscv to --enable-gprofng.
2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn>
* configure: Add riscv.
* configure.ac: Add riscv.
gprofng/ChangeLog: Minimal support gprofng for riscv.
2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn>
* gprofng/common/core_pcbe.c (core_pcbe_init): Add RISC-V vendor conditon.
(defined): Add riscv.
* gprofng/common/cpuid.c (defined): Add risc-v hwprobe.
* gprofng/common/gp-defs.h (TOK_A_RISCV): Add riscv.
(defined): Add riscv.
(ARCH_RISCV): Add riscv.
* gprofng/common/hwc_cpus.h: Add RISC-V vendor.
* gprofng/common/hwcfuncs.h (HW_INTERVAL_TYPE): Remove useless defination.
* gprofng/configure: Add riscv.
* gprofng/configure.ac: Add riscv.
* gprofng/libcollector/hwprofile.h (ARCH): Add RISC-V register.
(CONTEXT_PC): Add RISC-V register.
(CONTEXT_FP): Add RISC-V register.
(CONTEXT_SP): Add RISC-V register.
(SETFUNCTIONCONTEXT):
* gprofng/libcollector/libcol_util.c (__collector_util_init): Fix libc open condition.
* gprofng/libcollector/libcol_util.h (ARCH): Add RISC-V.
* gprofng/libcollector/unwind.c (ARCH): Add RISC-V register.
(GET_PC): Add RISC-V register.
(GET_SP): Add RISC-V register.
(GET_FP): Add RISC-V register.
(FILL_CONTEXT):
* gprofng/src/DbeSession.cc (ARCH): Add RISC-V.
* gprofng/src/Disasm.cc (Disasm::disasm_open): Add RISC-V.
* gprofng/src/Experiment.cc (Experiment::ExperimentHandler::startElement): Add RISC-V.
* gprofng/src/checks.cc (ARCH): Add RISC-V.
* gprofng/src/collctrl.cc (defined): Set risc-v cpu frequency to 1000MHz as default for now, will fix when I find a better method to get cpu frequency.
(read_cpuinfo): Add "mvendorid" condition according to risc-v /proc/cpuinfo file content.
* gprofng/src/dbe_types.h (enum Platform_t): Add RISC-V.
Diffstat (limited to 'gprofng/src/collctrl.cc')
| -rw-r--r-- | gprofng/src/collctrl.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/gprofng/src/collctrl.cc b/gprofng/src/collctrl.cc index d32590f..ece01d1 100644 --- a/gprofng/src/collctrl.cc +++ b/gprofng/src/collctrl.cc @@ -91,6 +91,9 @@ read_cpuinfo () #if defined(__aarch64__) asm volatile("mrs %0, cntfrq_el0" : "=r" (cpu_info.cpu_clk_freq)); +#elif defined(__riscv) + // Set 1000 MHz for minimal support RISC-V, will fix with a better method to get cpu clock frequency. + cpu_info.cpu_clk_freq = 1000; #endif // Read /proc/cpuinfo to get CPU info and clock rate @@ -106,7 +109,7 @@ read_cpuinfo () cpu_info.cpu_clk_freq = read_int (temp + 9); else if (strncmp (temp, "cpu family", 10) == 0) cpu_info.cpu_family = read_int (temp + 10); - else if (strncmp (temp, "vendor_id", 9) == 0) + else if ((strncmp (temp, "vendor_id", 9) || strncmp (temp, "mvendorid", 9)) == 0) { if (cpu_info.cpu_vendorstr == NULL) read_str (temp + 9, &cpu_info.cpu_vendorstr); |