RISC-V:[gprofng] Minimal support gprofng for riscv.

ChangeLog: Add target riscv to --enable-gprofng.

2024-07-04  Yixuan Chen  <chenyixuan@iscas.ac.cn>

        * configure: Add riscv.
        * configure.ac: Add riscv.

gprofng/ChangeLog: Minimal support gprofng for riscv.

2024-07-04  Yixuan Chen  <chenyixuan@iscas.ac.cn>

        * gprofng/common/core_pcbe.c (core_pcbe_init): Add RISC-V vendor conditon.
        (defined): Add riscv.
        * gprofng/common/cpuid.c (defined): Add risc-v hwprobe.
        * gprofng/common/gp-defs.h (TOK_A_RISCV): Add riscv.
        (defined): Add riscv.
        (ARCH_RISCV): Add riscv.
        * gprofng/common/hwc_cpus.h: Add RISC-V vendor.
        * gprofng/common/hwcfuncs.h (HW_INTERVAL_TYPE): Remove useless defination.
        * gprofng/configure: Add riscv.
        * gprofng/configure.ac: Add riscv.
        * gprofng/libcollector/hwprofile.h (ARCH): Add RISC-V register.
        (CONTEXT_PC): Add RISC-V register.
        (CONTEXT_FP): Add RISC-V register.
        (CONTEXT_SP): Add RISC-V register.
        (SETFUNCTIONCONTEXT):
        * gprofng/libcollector/libcol_util.c (__collector_util_init): Fix libc open condition.
        * gprofng/libcollector/libcol_util.h (ARCH): Add RISC-V.
        * gprofng/libcollector/unwind.c (ARCH): Add RISC-V register.
        (GET_PC): Add RISC-V register.
        (GET_SP): Add RISC-V register.
        (GET_FP): Add RISC-V register.
        (FILL_CONTEXT):
        * gprofng/src/DbeSession.cc (ARCH): Add RISC-V.
        * gprofng/src/Disasm.cc (Disasm::disasm_open): Add RISC-V.
        * gprofng/src/Experiment.cc (Experiment::ExperimentHandler::startElement): Add RISC-V.
        * gprofng/src/checks.cc (ARCH): Add RISC-V.
        * gprofng/src/collctrl.cc (defined): Set risc-v cpu frequency to 1000MHz as default for now, will fix when I find a better method to get cpu frequency.
        (read_cpuinfo): Add "mvendorid" condition according to risc-v /proc/cpuinfo file content.
        * gprofng/src/dbe_types.h (enum Platform_t): Add RISC-V.

6 files changed, 16 insertions, 2 deletions

diff --git a/gprofng/src/DbeSession.cc b/gprofng/src/DbeSession.cc
index 2032909..a6808d8 100644
--- a/gprofng/src/DbeSession.cc
+++ b/gprofng/src/DbeSession.cc
@@ -94,6 +94,8 @@ Platform_t DbeSession::platform =
 	Sparc;
 #elif ARCH(Aarch64)
 	Aarch64;
+#elif ARCH(RISCV)
+	RISCV;
 #else   // ARCH(Intel)
 	Intel;
 #endif
diff --git a/gprofng/src/Disasm.cc b/gprofng/src/Disasm.cc
index 1396e4f..e41bf67 100644
--- a/gprofng/src/Disasm.cc
+++ b/gprofng/src/Disasm.cc
@@ -208,6 +208,7 @@ Disasm::disasm_open ()
     case Amd64:
       need_swap_endian = (DbeSession::platform == Sparc);
       break;
+    case RISCV:
     case Sparcv8plus:
     case Sparcv9:
     case Sparc:
@@ -246,6 +247,7 @@ Disasm::disasm_open ()
       dis_info.arch = bfd_arch_i386;
       dis_info.mach = bfd_mach_x86_64;
       break;
+    case RISCV:
     case Sparcv8plus:
     case Sparcv9:
     case Sparc:
diff --git a/gprofng/src/Experiment.cc b/gprofng/src/Experiment.cc
index 02a24eb..a1f78fc 100644
--- a/gprofng/src/Experiment.cc
+++ b/gprofng/src/Experiment.cc
@@ -542,6 +542,8 @@ Experiment::ExperimentHandler::startElement (char*, char*, char *qName, Attribut
 	    exp->platform = Intel;
 	  else if (strcmp (str, "aarch64") == 0)
 	    exp->platform = Aarch64;
+	  else if (strcmp (str, "riscv64") == 0)
+	    exp->platform = RISCV;
 	  else
 	    exp->platform = Sparc;
 	  exp->need_swap_endian = (DbeSession::platform == Sparc) ?
diff --git a/gprofng/src/checks.cc b/gprofng/src/checks.cc
index 8392bbe..4fe850d 100644
--- a/gprofng/src/checks.cc
+++ b/gprofng/src/checks.cc
@@ -332,6 +332,10 @@ collect::check_executable_arch (Elf *elf)
     case EM_AARCH64:
       is_64 = true;
       break;
+#elif ARCH(RISCV)
+    case EM_RISCV:
+      is_64 = true;
+      break;
 #endif
     default:
       return EXEC_ELF_ARCH;
diff --git a/gprofng/src/collctrl.cc b/gprofng/src/collctrl.cc
index d32590f..ece01d1 100644
--- a/gprofng/src/collctrl.cc
+++ b/gprofng/src/collctrl.cc
@@ -91,6 +91,9 @@ read_cpuinfo ()
 
 #if defined(__aarch64__)
   asm volatile("mrs %0, cntfrq_el0" : "=r" (cpu_info.cpu_clk_freq));
+#elif defined(__riscv)
+  // Set 1000 MHz for minimal support RISC-V, will fix with a better method to get cpu clock frequency.
+  cpu_info.cpu_clk_freq = 1000;
 #endif
 
   // Read /proc/cpuinfo to get CPU info and clock rate
@@ -106,7 +109,7 @@ read_cpuinfo ()
 	    cpu_info.cpu_clk_freq = read_int (temp + 9);
 	  else if (strncmp (temp, "cpu family", 10) == 0)
 	    cpu_info.cpu_family = read_int (temp + 10);
-	  else if (strncmp (temp, "vendor_id", 9) == 0)
+	  else if ((strncmp (temp, "vendor_id", 9) || strncmp (temp, "mvendorid", 9)) == 0)
 	    {
 	      if (cpu_info.cpu_vendorstr == NULL)
 		read_str (temp + 9, &cpu_info.cpu_vendorstr);
diff --git a/gprofng/src/dbe_types.h b/gprofng/src/dbe_types.h
index dd97adc..430922a 100644
--- a/gprofng/src/dbe_types.h
+++ b/gprofng/src/dbe_types.h
@@ -42,7 +42,8 @@ enum Platform_t
   Sparcv8plus,
   Java,
   Amd64,
-  Aarch64
+  Aarch64,
+  RISCV
 };
 
 enum WSize_t