aarch64: Add the SME2 saturating conversion instructions

There are two instruction formats here:

- SQCVT, SQCVTU and UQCVT, which operate on lists of two or
  four registers.

- SQCVTN, SQCVTUN and UQCVTN, which operate on lists of
  four registers.

14 files changed, 328 insertions, 0 deletions

diff --git a/gas/testsuite/gas/aarch64/sme2-25-invalid.d b/gas/testsuite/gas/aarch64/sme2-25-invalid.d
new file mode 100644
index 0000000..62b23cd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-25-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sme2-25-invalid.s
+#error_output: sme2-25-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sme2-25-invalid.l b/gas/testsuite/gas/aarch64/sme2-25-invalid.l
new file mode 100644
index 0000000..5b18a2a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-25-invalid.l
@@ -0,0 +1,48 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqcvt 0,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqcvt z0\.h,0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqcvt z0\.b, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqcvt z0\.h, {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.b,{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqcvt z0\.b, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqcvt z0\.h, {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqcvt z0\.h, {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqcvt z0\.b, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqcvt z0\.b, {z0\.s-z3\.s}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqcvt z0\.h, {z0\.d-z3\.d}
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.b,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqcvt z0\.b, {z0\.s-z3\.s}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqcvt z0\.h, {z0\.d-z3\.d}
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqcvt z0\.s,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	sqcvt z0\.h, {z0\.d-z3\.d}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	sqcvt z0\.b, {z0\.s-z3\.s}
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `sqcvt z0\.h,{z0\.s-z2\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `sqcvt z0\.h,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 2 -- `sqcvt z0\.h,{z0\.s,z8\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z1\.s-z2\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z31\.s,z0\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvt z0\.b,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvt z0\.b,{z0\.s-z2\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.b,{z1\.s-z4\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.b,{z2\.s-z5\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.b,{z3\.s-z6\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvt z0\.h,{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvt z0\.h,{z0\.d-z2\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z1\.d-z4\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z2\.d-z5\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvt z0\.h,{z3\.d-z6\.d}'
diff --git a/gas/testsuite/gas/aarch64/sme2-25-invalid.s b/gas/testsuite/gas/aarch64/sme2-25-invalid.s
new file mode 100644
index 0000000..10395f7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-25-invalid.s
@@ -0,0 +1,28 @@
+	sqcvt	0, { z0.s - z1.s }
+	sqcvt	z0.h, 0
+
+	sqcvt	z0.s, { z0.s - z1.s }
+	sqcvt	z0.b, { z0.d - z1.d }
+	sqcvt	z0.s, { z0.d - z1.d }
+
+	sqcvt	z0.s, { z0.s - z3.s }
+	sqcvt	z0.b, { z0.d - z3.d }
+	sqcvt	z0.s, { z0.d - z3.d }
+
+	sqcvt	z0.h, { z0.s - z2.s }
+	sqcvt	z0.h, { z0.s - z3.s }
+	sqcvt	z0.h, { z0.s, z8.s }
+	sqcvt	z0.h, { z1.s - z2.s }
+	sqcvt	z0.h, { z31.s, z0.s }
+
+	sqcvt	z0.b, { z0.s - z1.s }
+	sqcvt	z0.b, { z0.s - z2.s }
+	sqcvt	z0.b, { z1.s - z4.s }
+	sqcvt	z0.b, { z2.s - z5.s }
+	sqcvt	z0.b, { z3.s - z6.s }
+
+	sqcvt	z0.h, { z0.d - z1.d }
+	sqcvt	z0.h, { z0.d - z2.d }
+	sqcvt	z0.h, { z1.d - z4.d }
+	sqcvt	z0.h, { z2.d - z5.d }
+	sqcvt	z0.h, { z3.d - z6.d }
diff --git a/gas/testsuite/gas/aarch64/sme2-25-noarch.d b/gas/testsuite/gas/aarch64/sme2-25-noarch.d
new file mode 100644
index 0000000..e1e9d39
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-25-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme2-25.s
+#error_output: sme2-25-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sme2-25-noarch.l b/gas/testsuite/gas/aarch64/sme2-25-noarch.l
new file mode 100644
index 0000000..66998ff
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-25-noarch.l
@@ -0,0 +1,37 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z31\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z19\.h,{z14\.s-z15\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.b,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z31\.b,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.b,{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z11\.b,{z20\.s-z23\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z31\.h,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z0\.h,{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvt z22\.h,{z4\.d-z7\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z31\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z19\.h,{z14\.s-z15\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.b,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z31\.b,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.b,{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z11\.b,{z20\.s-z23\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z31\.h,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z0\.h,{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtu z22\.h,{z4\.d-z7\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z31\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z19\.h,{z14\.s-z15\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.b,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z31\.b,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.b,{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z11\.b,{z20\.s-z23\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z31\.h,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z0\.h,{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvt z22\.h,{z4\.d-z7\.d}'
diff --git a/gas/testsuite/gas/aarch64/sme2-25.d b/gas/testsuite/gas/aarch64/sme2-25.d
new file mode 100644
index 0000000..b2fdce7
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-25.d
@@ -0,0 +1,45 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+:	c123e000 	sqcvt	z0\.h, {z0\.s-z1\.s}
+[^:]+:	c123e01f 	sqcvt	z31\.h, {z0\.s-z1\.s}
+[^:]+:	c123e3c0 	sqcvt	z0\.h, {z30\.s-z31\.s}
+[^:]+:	c123e1d3 	sqcvt	z19\.h, {z14\.s-z15\.s}
+[^:]+:	c133e000 	sqcvt	z0\.b, {z0\.s-z3\.s}
+[^:]+:	c133e01f 	sqcvt	z31\.b, {z0\.s-z3\.s}
+[^:]+:	c133e380 	sqcvt	z0\.b, {z28\.s-z31\.s}
+[^:]+:	c133e28b 	sqcvt	z11\.b, {z20\.s-z23\.s}
+[^:]+:	c1b3e000 	sqcvt	z0\.h, {z0\.d-z3\.d}
+[^:]+:	c1b3e01f 	sqcvt	z31\.h, {z0\.d-z3\.d}
+[^:]+:	c1b3e380 	sqcvt	z0\.h, {z28\.d-z31\.d}
+[^:]+:	c1b3e096 	sqcvt	z22\.h, {z4\.d-z7\.d}
+[^:]+:	c163e000 	sqcvtu	z0\.h, {z0\.s-z1\.s}
+[^:]+:	c163e01f 	sqcvtu	z31\.h, {z0\.s-z1\.s}
+[^:]+:	c163e3c0 	sqcvtu	z0\.h, {z30\.s-z31\.s}
+[^:]+:	c163e1d3 	sqcvtu	z19\.h, {z14\.s-z15\.s}
+[^:]+:	c173e000 	sqcvtu	z0\.b, {z0\.s-z3\.s}
+[^:]+:	c173e01f 	sqcvtu	z31\.b, {z0\.s-z3\.s}
+[^:]+:	c173e380 	sqcvtu	z0\.b, {z28\.s-z31\.s}
+[^:]+:	c173e28b 	sqcvtu	z11\.b, {z20\.s-z23\.s}
+[^:]+:	c1f3e000 	sqcvtu	z0\.h, {z0\.d-z3\.d}
+[^:]+:	c1f3e01f 	sqcvtu	z31\.h, {z0\.d-z3\.d}
+[^:]+:	c1f3e380 	sqcvtu	z0\.h, {z28\.d-z31\.d}
+[^:]+:	c1f3e096 	sqcvtu	z22\.h, {z4\.d-z7\.d}
+[^:]+:	c123e020 	uqcvt	z0\.h, {z0\.s-z1\.s}
+[^:]+:	c123e03f 	uqcvt	z31\.h, {z0\.s-z1\.s}
+[^:]+:	c123e3e0 	uqcvt	z0\.h, {z30\.s-z31\.s}
+[^:]+:	c123e1f3 	uqcvt	z19\.h, {z14\.s-z15\.s}
+[^:]+:	c133e020 	uqcvt	z0\.b, {z0\.s-z3\.s}
+[^:]+:	c133e03f 	uqcvt	z31\.b, {z0\.s-z3\.s}
+[^:]+:	c133e3a0 	uqcvt	z0\.b, {z28\.s-z31\.s}
+[^:]+:	c133e2ab 	uqcvt	z11\.b, {z20\.s-z23\.s}
+[^:]+:	c1b3e020 	uqcvt	z0\.h, {z0\.d-z3\.d}
+[^:]+:	c1b3e03f 	uqcvt	z31\.h, {z0\.d-z3\.d}
+[^:]+:	c1b3e3a0 	uqcvt	z0\.h, {z28\.d-z31\.d}
+[^:]+:	c1b3e0b6 	uqcvt	z22\.h, {z4\.d-z7\.d}
diff --git a/gas/testsuite/gas/aarch64/sme2-25.s b/gas/testsuite/gas/aarch64/sme2-25.s
new file mode 100644
index 0000000..45a2a70
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-25.s
@@ -0,0 +1,44 @@
+	sqcvt	z0.h, { z0.s - z1.s }
+	sqcvt	z31.h, { z0.s - z1.s }
+	sqcvt	z0.h, { z30.s - z31.s }
+	sqcvt	z19.h, { z14.s - z15.s }
+
+	sqcvt	z0.b, { z0.s - z3.s }
+	sqcvt	z31.b, { z0.s - z3.s }
+	sqcvt	z0.b, { z28.s - z31.s }
+	sqcvt	z11.b, { z20.s - z23.s }
+
+	sqcvt	z0.h, { z0.d - z3.d }
+	sqcvt	z31.h, { z0.d - z3.d }
+	sqcvt	z0.h, { z28.d - z31.d }
+	sqcvt	z22.h, { z4.d - z7.d }
+
+	sqcvtu	z0.h, { z0.s - z1.s }
+	sqcvtu	z31.h, { z0.s - z1.s }
+	sqcvtu	z0.h, { z30.s - z31.s }
+	sqcvtu	z19.h, { z14.s - z15.s }
+
+	sqcvtu	z0.b, { z0.s - z3.s }
+	sqcvtu	z31.b, { z0.s - z3.s }
+	sqcvtu	z0.b, { z28.s - z31.s }
+	sqcvtu	z11.b, { z20.s - z23.s }
+
+	sqcvtu	z0.h, { z0.d - z3.d }
+	sqcvtu	z31.h, { z0.d - z3.d }
+	sqcvtu	z0.h, { z28.d - z31.d }
+	sqcvtu	z22.h, { z4.d - z7.d }
+
+	uqcvt	z0.h, { z0.s - z1.s }
+	uqcvt	z31.h, { z0.s - z1.s }
+	uqcvt	z0.h, { z30.s - z31.s }
+	uqcvt	z19.h, { z14.s - z15.s }
+
+	uqcvt	z0.b, { z0.s - z3.s }
+	uqcvt	z31.b, { z0.s - z3.s }
+	uqcvt	z0.b, { z28.s - z31.s }
+	uqcvt	z11.b, { z20.s - z23.s }
+
+	uqcvt	z0.h, { z0.d - z3.d }
+	uqcvt	z31.h, { z0.d - z3.d }
+	uqcvt	z0.h, { z28.d - z31.d }
+	uqcvt	z22.h, { z4.d - z7.d }
diff --git a/gas/testsuite/gas/aarch64/sme2-26-invalid.d b/gas/testsuite/gas/aarch64/sme2-26-invalid.d
new file mode 100644
index 0000000..5e336bf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-26-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sme2-26-invalid.s
+#error_output: sme2-26-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sme2-26-invalid.l b/gas/testsuite/gas/aarch64/sme2-26-invalid.l
new file mode 100644
index 0000000..08c2f7f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-26-invalid.l
@@ -0,0 +1,13 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqcvtn 0,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `sqcvtn z0\.b,0'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvtn z0\.b,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvtn z0\.b,{z0\.s-z2\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.b,{z1\.s-z4\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.b,{z2\.s-z5\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.b,{z3\.s-z6\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvtn z0\.h,{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `sqcvtn z0\.h,{z0\.d-z2\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.h,{z1\.d-z4\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.h,{z2\.d-z5\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `sqcvtn z0\.h,{z3\.d-z6\.d}'
diff --git a/gas/testsuite/gas/aarch64/sme2-26-invalid.s b/gas/testsuite/gas/aarch64/sme2-26-invalid.s
new file mode 100644
index 0000000..2eddec9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-26-invalid.s
@@ -0,0 +1,14 @@
+	sqcvtn	0, { z0.s - z3.s }
+	sqcvtn	z0.b, 0
+
+	sqcvtn	z0.b, { z0.s - z1.s }
+	sqcvtn	z0.b, { z0.s - z2.s }
+	sqcvtn	z0.b, { z1.s - z4.s }
+	sqcvtn	z0.b, { z2.s - z5.s }
+	sqcvtn	z0.b, { z3.s - z6.s }
+
+	sqcvtn	z0.h, { z0.d - z1.d }
+	sqcvtn	z0.h, { z0.d - z2.d }
+	sqcvtn	z0.h, { z1.d - z4.d }
+	sqcvtn	z0.h, { z2.d - z5.d }
+	sqcvtn	z0.h, { z3.d - z6.d }
diff --git a/gas/testsuite/gas/aarch64/sme2-26-noarch.d b/gas/testsuite/gas/aarch64/sme2-26-noarch.d
new file mode 100644
index 0000000..e9af412
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-26-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme2-26.s
+#error_output: sme2-26-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sme2-26-noarch.l b/gas/testsuite/gas/aarch64/sme2-26-noarch.l
new file mode 100644
index 0000000..b1bd489
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-26-noarch.l
@@ -0,0 +1,25 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.b,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z31\.b,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.b,{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z11\.b,{z20\.s-z23\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.h,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z31\.h,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z0\.h,{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtn z22\.h,{z4\.d-z7\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.b,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z31\.b,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.b,{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z11\.b,{z20\.s-z23\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.h,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z31\.h,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z0\.h,{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sqcvtun z22\.h,{z4\.d-z7\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.b,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z31\.b,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.b,{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z11\.b,{z20\.s-z23\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.h,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z31\.h,{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z0\.h,{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `uqcvtn z22\.h,{z4\.d-z7\.d}'
diff --git a/gas/testsuite/gas/aarch64/sme2-26.d b/gas/testsuite/gas/aarch64/sme2-26.d
new file mode 100644
index 0000000..96e0ca9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-26.d
@@ -0,0 +1,33 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+:	c133e040 	sqcvtn	z0\.b, {z0\.s-z3\.s}
+[^:]+:	c133e05f 	sqcvtn	z31\.b, {z0\.s-z3\.s}
+[^:]+:	c133e3c0 	sqcvtn	z0\.b, {z28\.s-z31\.s}
+[^:]+:	c133e2cb 	sqcvtn	z11\.b, {z20\.s-z23\.s}
+[^:]+:	c1b3e040 	sqcvtn	z0\.h, {z0\.d-z3\.d}
+[^:]+:	c1b3e05f 	sqcvtn	z31\.h, {z0\.d-z3\.d}
+[^:]+:	c1b3e3c0 	sqcvtn	z0\.h, {z28\.d-z31\.d}
+[^:]+:	c1b3e0d6 	sqcvtn	z22\.h, {z4\.d-z7\.d}
+[^:]+:	c173e040 	sqcvtun	z0\.b, {z0\.s-z3\.s}
+[^:]+:	c173e05f 	sqcvtun	z31\.b, {z0\.s-z3\.s}
+[^:]+:	c173e3c0 	sqcvtun	z0\.b, {z28\.s-z31\.s}
+[^:]+:	c173e2cb 	sqcvtun	z11\.b, {z20\.s-z23\.s}
+[^:]+:	c1f3e040 	sqcvtun	z0\.h, {z0\.d-z3\.d}
+[^:]+:	c1f3e05f 	sqcvtun	z31\.h, {z0\.d-z3\.d}
+[^:]+:	c1f3e3c0 	sqcvtun	z0\.h, {z28\.d-z31\.d}
+[^:]+:	c1f3e0d6 	sqcvtun	z22\.h, {z4\.d-z7\.d}
+[^:]+:	c133e060 	uqcvtn	z0\.b, {z0\.s-z3\.s}
+[^:]+:	c133e07f 	uqcvtn	z31\.b, {z0\.s-z3\.s}
+[^:]+:	c133e3e0 	uqcvtn	z0\.b, {z28\.s-z31\.s}
+[^:]+:	c133e2eb 	uqcvtn	z11\.b, {z20\.s-z23\.s}
+[^:]+:	c1b3e060 	uqcvtn	z0\.h, {z0\.d-z3\.d}
+[^:]+:	c1b3e07f 	uqcvtn	z31\.h, {z0\.d-z3\.d}
+[^:]+:	c1b3e3e0 	uqcvtn	z0\.h, {z28\.d-z31\.d}
+[^:]+:	c1b3e0f6 	uqcvtn	z22\.h, {z4\.d-z7\.d}
diff --git a/gas/testsuite/gas/aarch64/sme2-26.s b/gas/testsuite/gas/aarch64/sme2-26.s
new file mode 100644
index 0000000..72bdbf6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-26.s
@@ -0,0 +1,29 @@
+	sqcvtn	z0.b, { z0.s - z3.s }
+	sqcvtn	z31.b, { z0.s - z3.s }
+	sqcvtn	z0.b, { z28.s - z31.s }
+	sqcvtn	z11.b, { z20.s - z23.s }
+
+	sqcvtn	z0.h, { z0.d - z3.d }
+	sqcvtn	z31.h, { z0.d - z3.d }
+	sqcvtn	z0.h, { z28.d - z31.d }
+	sqcvtn	z22.h, { z4.d - z7.d }
+
+	sqcvtun	z0.b, { z0.s - z3.s }
+	sqcvtun	z31.b, { z0.s - z3.s }
+	sqcvtun	z0.b, { z28.s - z31.s }
+	sqcvtun	z11.b, { z20.s - z23.s }
+
+	sqcvtun	z0.h, { z0.d - z3.d }
+	sqcvtun	z31.h, { z0.d - z3.d }
+	sqcvtun	z0.h, { z28.d - z31.d }
+	sqcvtun	z22.h, { z4.d - z7.d }
+
+	uqcvtn	z0.b, { z0.s - z3.s }
+	uqcvtn	z31.b, { z0.s - z3.s }
+	uqcvtn	z0.b, { z28.s - z31.s }
+	uqcvtn	z11.b, { z20.s - z23.s }
+
+	uqcvtn	z0.h, { z0.d - z3.d }
+	uqcvtn	z31.h, { z0.d - z3.d }
+	uqcvtn	z0.h, { z28.d - z31.d }
+	uqcvtn	z22.h, { z4.d - z7.d }