aarch64: Add the SME2 FP<->FP conversion instructions

This patch adds the BFCVT{,N} and FCVT{,N} instructions,
which narrow a pair of .S registers to a single .H register.

7 files changed, 102 insertions, 0 deletions

diff --git a/gas/testsuite/gas/aarch64/sme2-24-invalid.d b/gas/testsuite/gas/aarch64/sme2-24-invalid.d
new file mode 100644
index 0000000..9ce97b6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-24-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sme2-24-invalid.s
+#error_output: sme2-24-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sme2-24-invalid.l b/gas/testsuite/gas/aarch64/sme2-24-invalid.l
new file mode 100644
index 0000000..c44a582
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-24-invalid.l
@@ -0,0 +1,22 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `bfcvt 0,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 2 -- `bfcvt z0\.h,0'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `bfcvt z0\.h,{z1\.s-z2\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `bfcvtn z0\.h,{z0\.s-z2\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `bfcvt z0\.h,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvtn z0\.s,{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bfcvtn z0\.h, {z0\.s-z3\.s}
+[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt z0\.s,{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	bfcvt z0\.h, {z0\.s-z3\.s}
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvt z0\.s,{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvt z0\.h, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvt z0\.s,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvt z0\.h, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Error: operand mismatch -- `fcvt z0\.d,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fcvt z0\.h, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fcvt z0\.h,{z1\.s-z2\.s}'
diff --git a/gas/testsuite/gas/aarch64/sme2-24-invalid.s b/gas/testsuite/gas/aarch64/sme2-24-invalid.s
new file mode 100644
index 0000000..e22be36
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-24-invalid.s
@@ -0,0 +1,13 @@
+	bfcvt	0, { z0.s - z1.s }
+	bfcvt	z0.h, 0
+
+	bfcvt	z0.h, { z1.s - z2.s }
+	bfcvtn	z0.h, { z0.s - z2.s }
+	bfcvt	z0.h, { z0.s - z3.s }
+	bfcvtn	z0.s, { z0.s - z3.s }
+	bfcvt	z0.s, { z0.h - z3.h }
+
+	fcvt	z0.s, { z0.h - z1.h }
+	fcvt	z0.s, { z0.s - z1.s }
+	fcvt	z0.d, { z0.s - z1.s }
+	fcvt	z0.h, { z1.s - z2.s }
diff --git a/gas/testsuite/gas/aarch64/sme2-24-noarch.d b/gas/testsuite/gas/aarch64/sme2-24-noarch.d
new file mode 100644
index 0000000..c26670d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-24-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme2-24.s
+#error_output: sme2-24-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sme2-24-noarch.l b/gas/testsuite/gas/aarch64/sme2-24-noarch.l
new file mode 100644
index 0000000..ef23b8b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-24-noarch.l
@@ -0,0 +1,17 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `bfcvt z0\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfcvt z31\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfcvt z0\.h,{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfcvt z14\.h,{z20\.s-z21\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfcvtn z0\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfcvtn z31\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfcvtn z0\.h,{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `bfcvtn z26\.h,{z14\.s-z15\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvt z0\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvt z31\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvt z0\.h,{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvt z29\.h,{z6\.s-z7\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtn z0\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtn z31\.h,{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtn z0\.h,{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fcvtn z29\.h,{z6\.s-z7\.s}'
diff --git a/gas/testsuite/gas/aarch64/sme2-24.d b/gas/testsuite/gas/aarch64/sme2-24.d
new file mode 100644
index 0000000..3a621c2
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-24.d
@@ -0,0 +1,25 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+:	c160e000 	bfcvt	z0\.h, {z0\.s-z1\.s}
+[^:]+:	c160e01f 	bfcvt	z31\.h, {z0\.s-z1\.s}
+[^:]+:	c160e3c0 	bfcvt	z0\.h, {z30\.s-z31\.s}
+[^:]+:	c160e28e 	bfcvt	z14\.h, {z20\.s-z21\.s}
+[^:]+:	c160e020 	bfcvtn	z0\.h, {z0\.s-z1\.s}
+[^:]+:	c160e03f 	bfcvtn	z31\.h, {z0\.s-z1\.s}
+[^:]+:	c160e3e0 	bfcvtn	z0\.h, {z30\.s-z31\.s}
+[^:]+:	c160e1fa 	bfcvtn	z26\.h, {z14\.s-z15\.s}
+[^:]+:	c120e000 	fcvt	z0\.h, {z0\.s-z1\.s}
+[^:]+:	c120e01f 	fcvt	z31\.h, {z0\.s-z1\.s}
+[^:]+:	c120e3c0 	fcvt	z0\.h, {z30\.s-z31\.s}
+[^:]+:	c120e0dd 	fcvt	z29\.h, {z6\.s-z7\.s}
+[^:]+:	c120e020 	fcvtn	z0\.h, {z0\.s-z1\.s}
+[^:]+:	c120e03f 	fcvtn	z31\.h, {z0\.s-z1\.s}
+[^:]+:	c120e3e0 	fcvtn	z0\.h, {z30\.s-z31\.s}
+[^:]+:	c120e0fd 	fcvtn	z29\.h, {z6\.s-z7\.s}
diff --git a/gas/testsuite/gas/aarch64/sme2-24.s b/gas/testsuite/gas/aarch64/sme2-24.s
new file mode 100644
index 0000000..081d7f1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-24.s
@@ -0,0 +1,19 @@
+	bfcvt	z0.h, { z0.s - z1.s }
+	bfcvt	z31.h, { z0.s - z1.s }
+	bfcvt	z0.h, { z30.s - z31.s }
+	bfcvt	z14.h, { z20.s - z21.s }
+
+	bfcvtn	z0.h, { z0.s - z1.s }
+	bfcvtn	z31.h, { z0.s - z1.s }
+	bfcvtn	z0.h, { z30.s - z31.s }
+	bfcvtn	z26.h, { z14.s - z15.s }
+
+	fcvt	z0.h, { z0.s - z1.s }
+	fcvt	z31.h, { z0.s - z1.s }
+	fcvt	z0.h, { z30.s - z31.s }
+	fcvt	z29.h, { z6.s - z7.s }
+
+	fcvtn	z0.h, { z0.s - z1.s }
+	fcvtn	z31.h, { z0.s - z1.s }
+	fcvtn	z0.h, { z30.s - z31.s }
+	fcvtn	z29.h, { z6.s - z7.s }