aarch64: Add the SME2 FMLA and FMLS instructions

15 files changed, 1129 insertions, 0 deletions

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 5e02315..47ad704 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6727,6 +6727,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_SVE_Zm4_11_INDEX:
 	case AARCH64_OPND_SVE_Zm4_INDEX:
 	case AARCH64_OPND_SVE_Zn_INDEX:
+	case AARCH64_OPND_SME_Zm_INDEX1:
+	case AARCH64_OPND_SME_Zm_INDEX2:
 	case AARCH64_OPND_SME_Zn_INDEX1_16:
 	case AARCH64_OPND_SME_Zn_INDEX2_15:
 	case AARCH64_OPND_SME_Zn_INDEX2_16:
diff --git a/gas/testsuite/gas/aarch64/sme2-11-invalid.d b/gas/testsuite/gas/aarch64/sme2-11-invalid.d
new file mode 100644
index 0000000..1bc2509
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-11-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sme2-11-invalid.s
+#error_output: sme2-11-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sme2-11-invalid.l b/gas/testsuite/gas/aarch64/sme2-11-invalid.l
new file mode 100644
index 0000000..8044d26
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-11-invalid.l
@@ -0,0 +1,101 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fmla 0,{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `fmla za\.s\[w8,0\],0,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},0'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z2\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z2\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z4\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z4\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z2\.s-z5\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z3\.s-z6\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z16\.s\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[4\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w0,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `fmla za\.s\[w31,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,1<<63\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z31\.s'
+[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `fmla za\.s\[w8,0:0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `fmla za\.s\[w8,0:-1\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.s\[w8,0:1\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.s\[w8,0:100\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z16\.s'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z16\.s'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z2\.s},z0\.s'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z4\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s,z1\.s,z2\.s},z0\.s'
+[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s,z1\.s,z5\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
+[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fmla za\.s\[w8,0\],{z0-z1},z0\.s'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z1\.s},z0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z2\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z15\.s-z16\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z31\.s,z0\.s}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w7,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.s\[w12,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,-1\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.s\[w8,8\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z1\.s-z4\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z2\.s-z5\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.s\[w8,0\],{z3\.s-z6\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z15\.s-z18\.s}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z29\.s,z30\.s,z31\.s,z0\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.s\[w8,0\],{z0\.s-z2\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z2\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z4\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmla za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmla za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
diff --git a/gas/testsuite/gas/aarch64/sme2-11-invalid.s b/gas/testsuite/gas/aarch64/sme2-11-invalid.s
new file mode 100644
index 0000000..70ab0c4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-11-invalid.s
@@ -0,0 +1,91 @@
+	fmla	0, { z0.s - z1.s }, z0.s[0]
+	fmla	za.s[w8, 0], 0, z0.s[0]
+	fmla	za.s[w8, 0], { z0.s - z1.s }, 0
+
+	fmla	za.s[w7, 0], { z0.s - z1.s }, z0.s[0]
+	fmla	za.s[w12, 0], { z0.s - z1.s }, z0.s[0]
+	fmla	za.s[w8, -1], { z0.s - z1.s }, z0.s[0]
+	fmla	za.s[w8, 8], { z0.s - z1.s }, z0.s[0]
+	fmla	za.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s[0]
+	fmla	za.s[w8, 0], { z0.s - z2.s }, z0.s[0]
+	fmla	za.s[w8, 0], { z1.s - z2.s }, z0.s[0]
+	fmla	za.s[w8, 0], { z0.s - z1.s }, z16.s[0]
+	fmla	za.s[w8, 0], { z0.s - z1.s }, z0.s[-1]
+	fmla	za.s[w8, 0], { z0.s - z1.s }, z0.s[4]
+
+	fmla	za.s[w7, 0], { z0.s - z3.s }, z0.s[0]
+	fmla	za.s[w12, 0], { z0.s - z3.s }, z0.s[0]
+	fmla	za.s[w8, -1], { z0.s - z3.s }, z0.s[0]
+	fmla	za.s[w8, 8], { z0.s - z3.s }, z0.s[0]
+	fmla	za.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s[0]
+	fmla	za.s[w8, 0], { z0.s - z4.s }, z0.s[0]
+	fmla	za.s[w8, 0], { z1.s - z4.s }, z0.s[0]
+	fmla	za.s[w8, 0], { z2.s - z5.s }, z0.s[0]
+	fmla	za.s[w8, 0], { z3.s - z6.s }, z0.s[0]
+	fmla	za.s[w8, 0], { z0.s - z3.s }, z16.s[0]
+	fmla	za.s[w8, 0], { z0.s - z3.s }, z0.s[-1]
+	fmla	za.s[w8, 0], { z0.s - z3.s }, z0.s[4]
+
+	fmla	za.s[w0, 0], { z0.s - z1.s }, z0.s
+	fmla	za.s[w31, 0], { z0.s - z1.s }, z0.s
+	fmla	za.s[w8, 1<<63], { z0.s - z1.s }, z0.s
+	fmla	za.s[w8, 0], { z0.s - z1.s }, z31.s
+	fmla	za.s[w8, 0:0], { z0.s - z1.s }, z0.s
+	fmla	za.s[w8, 0:-1], { z0.s - z1.s }, z0.s
+	fmla	za.s[w8, 0:1], { z0.s - z1.s }, z0.s
+	fmla	za.s[w8, 0:100], { z0.s - z1.s }, z0.s
+
+	fmla	za.s[w7, 0], { z0.s - z1.s }, z0.s
+	fmla	za.s[w12, 0], { z0.s - z1.s }, z0.s
+	fmla	za.s[w8, -1], { z0.s - z1.s }, z0.s
+	fmla	za.s[w8, 8], { z0.s - z1.s }, z0.s
+	fmla	za.s[w8, 0], { z0.s - z1.s }, z16.s
+
+	fmla	za.s[w7, 0], { z0.s - z3.s }, z0.s
+	fmla	za.s[w12, 0], { z0.s - z3.s }, z0.s
+	fmla	za.s[w8, -1], { z0.s - z3.s }, z0.s
+	fmla	za.s[w8, 8], { z0.s - z3.s }, z0.s
+	fmla	za.s[w8, 0], { z0.s - z3.s }, z16.s
+
+	fmla	za.s[w8, 0], { z0.s - z2.s }, z0.s
+	fmla	za.s[w8, 0], { z0.s - z4.s }, z0.s
+	fmla	za.s[w8, 0], { z0.s, z1.s, z2.s }, z0.s
+	fmla	za.s[w8, 0], { z0.s, z1.s, z5.s }, z0.s
+
+	fmla	za.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s
+	fmla	za.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s
+	fmla	za[w8, 0], { z0.s - z1.s }, z0.s
+	fmla	za.s[w8, 0], { z0 - z1 }, z0.s
+	fmla	za.s[w8, 0], { z0.s - z1.s }, z0
+	fmla	za[w8, 0], { z0.s - z1.s }, z0
+
+	fmla	za.s[w7, 0], { z0.s - z1.s }, { z0.s - z1.s }
+	fmla	za.s[w12, 0], { z0.s - z1.s }, { z0.s - z1.s }
+	fmla	za.s[w8, -1], { z0.s - z1.s }, { z0.s - z1.s }
+	fmla	za.s[w8, 8], { z0.s - z1.s }, { z0.s - z1.s }
+	fmla	za.s[w8, 0], { z1.s - z2.s }, { z0.s - z1.s }
+	fmla	za.s[w8, 0], { z0.s - z1.s }, { z15.s - z16.s }
+	fmla	za.s[w8, 0], { z0.s - z1.s }, { z31.s, z0.s }
+
+	fmla	za.s[w7, 0], { z0.s - z3.s }, { z0.s - z3.s }
+	fmla	za.s[w12, 0], { z0.s - z3.s }, { z0.s - z3.s }
+	fmla	za.s[w8, -1], { z0.s - z3.s }, { z0.s - z3.s }
+	fmla	za.s[w8, 8], { z0.s - z3.s }, { z0.s - z3.s }
+	fmla	za.s[w8, 0], { z1.s - z4.s }, { z0.s - z3.s }
+	fmla	za.s[w8, 0], { z2.s - z5.s }, { z0.s - z3.s }
+	fmla	za.s[w8, 0], { z3.s - z6.s }, { z0.s - z3.s }
+	fmla	za.s[w8, 0], { z0.s - z3.s }, { z15.s - z18.s }
+	fmla	za.s[w8, 0], { z0.s - z3.s }, { z29.s, z30.s, z31.s, z0.s }
+
+	fmla	za.s[w8, 0], { z0.s - z2.s }, { z0.s - z1.s }
+	fmla	za.s[w8, 0], { z0.s - z3.s }, { z0.s - z1.s }
+	fmla	za.s[w8, 0], { z0.s - z1.s }, { z0.s - z2.s }
+	fmla	za.s[w8, 0], { z0.s - z1.s }, { z0.s - z3.s }
+	fmla	za.s[w8, 0], { z0.s - z1.s }, { z0.s - z4.s }
+
+	fmla	za.s[w8, 0, vgx4], { z0.s - z1.s }, { z0.s - z3.s }
+	fmla	za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z1.s }
+	fmla	za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z3.s }
+	fmla	za.s[w8, 0, vgx2], { z0.s - z3.s }, { z0.s - z1.s }
+	fmla	za[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }
+	fmla	za[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }
diff --git a/gas/testsuite/gas/aarch64/sme2-11-noarch.d b/gas/testsuite/gas/aarch64/sme2-11-noarch.d
new file mode 100644
index 0000000..7dcb6a0
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-11-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme
+#source: sme2-11.s
+#error_output: sme2-11-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sme2-11-noarch.l b/gas/testsuite/gas/aarch64/sme2-11-noarch.l
new file mode 100644
index 0000000..05c3139
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-11-noarch.l
@@ -0,0 +1,117 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGx2\],{Z0\.S-Z1\.S},Z0\.S\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w9,6\],{z12\.s-z13\.s},z1\.s\[2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w10,4\],{z4\.s-z7\.s},z9\.s\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGx2\],{Z0\.S-Z1\.S},Z0\.S\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w9,6\],{z12\.s-z13\.s},z1\.s\[2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w10,4\],{z4\.s-z7\.s},z9\.s\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}'
diff --git a/gas/testsuite/gas/aarch64/sme2-11.d b/gas/testsuite/gas/aarch64/sme2-11.d
new file mode 100644
index 0000000..7f077e3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-11.d
@@ -0,0 +1,125 @@
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+:	c1500000 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+:	c1500000 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+:	c1500000 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+:	c1506000 	fmla	za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+:	c1500007 	fmla	za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+:	c15003c0 	fmla	za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s\[0\]
+[^:]+:	c15f0000 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s\[0\]
+[^:]+:	c1500c00 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[3\]
+[^:]+:	c1512986 	fmla	za\.s\[w9, 6, vgx2\], {z12\.s-z13\.s}, z1\.s\[2\]
+[^:]+:	c1508000 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+:	c1508000 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+:	c1508000 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+:	c150e000 	fmla	za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+:	c1508007 	fmla	za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+:	c1508380 	fmla	za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s\[0\]
+[^:]+:	c15f8000 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s\[0\]
+[^:]+:	c1508c00 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[3\]
+[^:]+:	c159c484 	fmla	za\.s\[w10, 4, vgx4\], {z4\.s-z7\.s}, z9\.s\[1\]
+[^:]+:	c1201800 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+:	c1201800 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+:	c1201800 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+:	c1201800 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+:	c1207800 	fmla	za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+:	c1201807 	fmla	za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+:	c1201bc0 	fmla	za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s
+[^:]+:	c1201be0 	fmla	za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
+[^:]+:	c1201be0 	fmla	za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
+[^:]+:	c12f1800 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s
+[^:]+:	c1263925 	fmla	za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s
+[^:]+:	c1301800 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+:	c1301800 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+:	c1301800 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+:	c1301800 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+:	c1307800 	fmla	za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+:	c1301807 	fmla	za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+:	c1301b80 	fmla	za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s
+[^:]+:	c1301be0 	fmla	za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
+[^:]+:	c1301be0 	fmla	za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
+[^:]+:	c13f1800 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s
+[^:]+:	c13d7ae2 	fmla	za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s
+[^:]+:	c1a01800 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a01800 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a01800 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a01800 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a07800 	fmla	za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a01807 	fmla	za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a01bc0 	fmla	za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^:]+:	c1be1800 	fmla	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^:]+:	c1b25ac1 	fmla	za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s}
+[^:]+:	c1a11800 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1a11800 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1a11800 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1a11800 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1a17800 	fmla	za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1a11807 	fmla	za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1a11b80 	fmla	za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s}
+[^:]+:	c1bd1800 	fmla	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s}
+[^:]+:	c1b97a03 	fmla	za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s}
+[^:]+:	c1500010 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+:	c1500010 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+:	c1500010 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+:	c1506010 	fmls	za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+:	c1500017 	fmls	za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s\[0\]
+[^:]+:	c15003d0 	fmls	za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s\[0\]
+[^:]+:	c15f0010 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s\[0\]
+[^:]+:	c1500c10 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s\[3\]
+[^:]+:	c1512996 	fmls	za\.s\[w9, 6, vgx2\], {z12\.s-z13\.s}, z1\.s\[2\]
+[^:]+:	c1508010 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+:	c1508010 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+:	c1508010 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+:	c150e010 	fmls	za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+:	c1508017 	fmls	za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s\[0\]
+[^:]+:	c1508390 	fmls	za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s\[0\]
+[^:]+:	c15f8010 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s\[0\]
+[^:]+:	c1508c10 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s\[3\]
+[^:]+:	c159c494 	fmls	za\.s\[w10, 4, vgx4\], {z4\.s-z7\.s}, z9\.s\[1\]
+[^:]+:	c1201808 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+:	c1201808 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+:	c1201808 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+:	c1201808 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+:	c1207808 	fmls	za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+:	c120180f 	fmls	za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s
+[^:]+:	c1201bc8 	fmls	za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s
+[^:]+:	c1201be8 	fmls	za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
+[^:]+:	c1201be8 	fmls	za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
+[^:]+:	c12f1808 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s
+[^:]+:	c126392d 	fmls	za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s
+[^:]+:	c1301808 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+:	c1301808 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+:	c1301808 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+:	c1301808 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+:	c1307808 	fmls	za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+:	c130180f 	fmls	za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s
+[^:]+:	c1301b88 	fmls	za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s
+[^:]+:	c1301be8 	fmls	za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
+[^:]+:	c1301be8 	fmls	za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
+[^:]+:	c13f1808 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s
+[^:]+:	c13d7aea 	fmls	za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s
+[^:]+:	c1a01808 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a01808 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a01808 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a01808 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a07808 	fmls	za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a0180f 	fmls	za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+:	c1a01bc8 	fmls	za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^:]+:	c1be1808 	fmls	za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^:]+:	c1b25ac9 	fmls	za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s}
+[^:]+:	c1a11808 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1a11808 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1a11808 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1a11808 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1a17808 	fmls	za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1a1180f 	fmls	za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+:	c1a11b88 	fmls	za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s}
+[^:]+:	c1bd1808 	fmls	za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s}
+[^:]+:	c1b97a0b 	fmls	za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s}
diff --git a/gas/testsuite/gas/aarch64/sme2-11.s b/gas/testsuite/gas/aarch64/sme2-11.s
new file mode 100644
index 0000000..fbefe0d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-11.s
@@ -0,0 +1,127 @@
+	fmla	za.s[w8, 0], { z0.s - z1.s }, z0.s[0]
+	fmla	za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s[0]
+	FMLA	ZA.S[W8, 0, VGx2], { Z0.S - Z1.S }, Z0.S[0]
+	fmla	za.s[w11, 0], { z0.s - z1.s }, z0.s[0]
+	fmla	za.s[w8, 7], { z0.s - z1.s }, z0.s[0]
+	fmla	za.s[w8, 0], { z30.s - z31.s }, z0.s[0]
+	fmla	za.s[w8, 0], { z0.s - z1.s }, z15.s[0]
+	fmla	za.s[w8, 0], { z0.s - z1.s }, z0.s[3]
+	fmla	za.s[w9, 6], { z12.s - z13.s }, z1.s[2]
+
+	fmla	za.s[w8, 0], { z0.s - z3.s }, z0.s[0]
+	fmla	za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]
+	FMLA	ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S[0]
+	fmla	za.s[w11, 0], { z0.s - z3.s }, z0.s[0]
+	fmla	za.s[w8, 7], { z0.s - z3.s }, z0.s[0]
+	fmla	za.s[w8, 0], { z28.s - z31.s }, z0.s[0]
+	fmla	za.s[w8, 0], { z0.s - z3.s }, z15.s[0]
+	fmla	za.s[w8, 0], { z0.s - z3.s }, z0.s[3]
+	fmla	za.s[w10, 4], { z4.s - z7.s }, z9.s[1]
+
+	fmla	za.s[w8, 0], { z0.s - z1.s }, z0.s
+	fmla	za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s
+	FMLA	ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s
+	FMLA	ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S
+	fmla	za.s[w11, 0], { z0.s - z1.s }, z0.s
+	fmla	za.s[w8, 7], { z0.s - z1.s }, z0.s
+	fmla	za.s[w8, 0], { z30.s - z31.s }, z0.s
+	fmla	za.s[w8, 0], { z31.s, z0.s }, z0.s
+	fmla	za.s[w8, 0], { z31.s - z0.s }, z0.s
+	fmla	za.s[w8, 0], { z0.s - z1.s }, z15.s
+	fmla	za.s[w9, 5], { z9.s - z10.s }, z6.s
+
+	fmla	za.s[w8, 0], { z0.s - z3.s }, z0.s
+	fmla	za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
+	FMLA	ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s
+	FMLA	ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S
+	fmla	za.s[w11, 0], { z0.s - z3.s }, z0.s
+	fmla	za.s[w8, 7], { z0.s - z3.s }, z0.s
+	fmla	za.s[w8, 0], { z28.s - z31.s }, z0.s
+	fmla	za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s
+	fmla	za.s[w8, 0], { z31.s - z2.s }, z0.s
+	fmla	za.s[w8, 0], { z0.s - z3.s }, z15.s
+	fmla	za.s[w11, 2], { z23.s - z26.s }, z13.s
+
+	fmla	za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }
+	fmla	za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s }
+	FMLA	ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s }
+	FMLA	ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S }
+	fmla	za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s }
+	fmla	za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s }
+	fmla	za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s }
+	fmla	za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s }
+	fmla	za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s }
+
+	fmla	za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }
+	fmla	za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
+	FMLA	ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s }
+	FMLA	ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S }
+	fmla	za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s }
+	fmla	za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s }
+	fmla	za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s }
+	fmla	za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s }
+	fmla	za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s }
+
+	fmls	za.s[w8, 0], { z0.s - z1.s }, z0.s[0]
+	fmls	za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s[0]
+	FMLS	ZA.S[W8, 0, VGx2], { Z0.S - Z1.S }, Z0.S[0]
+	fmls	za.s[w11, 0], { z0.s - z1.s }, z0.s[0]
+	fmls	za.s[w8, 7], { z0.s - z1.s }, z0.s[0]
+	fmls	za.s[w8, 0], { z30.s - z31.s }, z0.s[0]
+	fmls	za.s[w8, 0], { z0.s - z1.s }, z15.s[0]
+	fmls	za.s[w8, 0], { z0.s - z1.s }, z0.s[3]
+	fmls	za.s[w9, 6], { z12.s - z13.s }, z1.s[2]
+
+	fmls	za.s[w8, 0], { z0.s - z3.s }, z0.s[0]
+	fmls	za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]
+	FMLS	ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S[0]
+	fmls	za.s[w11, 0], { z0.s - z3.s }, z0.s[0]
+	fmls	za.s[w8, 7], { z0.s - z3.s }, z0.s[0]
+	fmls	za.s[w8, 0], { z28.s - z31.s }, z0.s[0]
+	fmls	za.s[w8, 0], { z0.s - z3.s }, z15.s[0]
+	fmls	za.s[w8, 0], { z0.s - z3.s }, z0.s[3]
+	fmls	za.s[w10, 4], { z4.s - z7.s }, z9.s[1]
+
+	fmls	za.s[w8, 0], { z0.s - z1.s }, z0.s
+	fmls	za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s
+	FMLS	ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s
+	FMLS	ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S
+	fmls	za.s[w11, 0], { z0.s - z1.s }, z0.s
+	fmls	za.s[w8, 7], { z0.s - z1.s }, z0.s
+	fmls	za.s[w8, 0], { z30.s - z31.s }, z0.s
+	fmls	za.s[w8, 0], { z31.s, z0.s }, z0.s
+	fmls	za.s[w8, 0], { z31.s - z0.s }, z0.s
+	fmls	za.s[w8, 0], { z0.s - z1.s }, z15.s
+	fmls	za.s[w9, 5], { z9.s - z10.s }, z6.s
+
+	fmls	za.s[w8, 0], { z0.s - z3.s }, z0.s
+	fmls	za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
+	FMLS	ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s
+	FMLS	ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S
+	fmls	za.s[w11, 0], { z0.s - z3.s }, z0.s
+	fmls	za.s[w8, 7], { z0.s - z3.s }, z0.s
+	fmls	za.s[w8, 0], { z28.s - z31.s }, z0.s
+	fmls	za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s
+	fmls	za.s[w8, 0], { z31.s - z2.s }, z0.s
+	fmls	za.s[w8, 0], { z0.s - z3.s }, z15.s
+	fmls	za.s[w11, 2], { z23.s - z26.s }, z13.s
+
+	fmls	za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }
+	fmls	za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s }
+	FMLS	ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s }
+	FMLS	ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S }
+	fmls	za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s }
+	fmls	za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s }
+	fmls	za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s }
+	fmls	za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s }
+	fmls	za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s }
+
+	fmls	za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }
+	fmls	za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
+	FMLS	ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s }
+	FMLS	ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S }
+	fmls	za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s }
+	fmls	za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s }
+	fmls	za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s }
+	fmls	za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s }
+	fmls	za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s }
diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.d b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.d
new file mode 100644
index 0000000..e2e4a7a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: sme2-f64f64-2-invalid.s
+#error_output: sme2-f64f64-2-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l
new file mode 100644
index 0000000..97b0db1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.l
@@ -0,0 +1,98 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z2\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z2\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z16\.d\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[2\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z4\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z4\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z2\.d-z5\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z3\.d-z6\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z16\.d\[0\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[2\]'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w0,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `fmla za\.d\[w31,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,1<<63\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z31\.d'
+[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `fmla za\.d\[w8,0:0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `fmla za\.d\[w8,0:-1\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.d\[w8,0:1\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `fmla za\.d\[w8,0:100\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z16\.d'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z16\.d'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z2\.d},z0\.d'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z4\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d,z1\.d,z2\.d},z0\.d'
+[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d,z1\.d,z5\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fmla za\.d\[w8,0\],{z0-z1},z0\.d'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z1\.d},z0'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z2\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z15\.d-z16\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z31\.d,z0\.d}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w7,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fmla za\.d\[w12,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,-1\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fmla za\.d\[w8,8\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z1\.d-z4\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z2\.d-z5\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fmla za\.d\[w8,0\],{z3\.d-z6\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z15\.d-z18\.d}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z29\.d,z30\.d,z31\.d,z0\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fmla za\.d\[w8,0\],{z0\.d-z2\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z2\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z4\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fmla za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmla za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmla za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Error: operand mismatch -- `fmla za\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Info:    did you mean this\?
+[^ :]+:[0-9]+: Info:    	fmla za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^ :]+:[0-9]+: Info:    other valid variant\(s\):
+[^ :]+:[0-9]+: Info:    	fmla za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.s b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.s
new file mode 100644
index 0000000..9839bfe
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-invalid.s
@@ -0,0 +1,87 @@
+	fmla	za.d[w7, 0], { z0.d - z1.d }, z0.d[0]
+	fmla	za.d[w12, 0], { z0.d - z1.d }, z0.d[0]
+	fmla	za.d[w8, -1], { z0.d - z1.d }, z0.d[0]
+	fmla	za.d[w8, 8], { z0.d - z1.d }, z0.d[0]
+	fmla	za.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d[0]
+	fmla	za.d[w8, 0], { z0.d - z2.d }, z0.d[0]
+	fmla	za.d[w8, 0], { z1.d - z2.d }, z0.d[0]
+	fmla	za.d[w8, 0], { z0.d - z1.d }, z16.d[0]
+	fmla	za.d[w8, 0], { z0.d - z1.d }, z0.d[-1]
+	fmla	za.d[w8, 0], { z0.d - z1.d }, z0.d[2]
+
+	fmla	za.d[w7, 0], { z0.d - z3.d }, z0.d[0]
+	fmla	za.d[w12, 0], { z0.d - z3.d }, z0.d[0]
+	fmla	za.d[w8, -1], { z0.d - z3.d }, z0.d[0]
+	fmla	za.d[w8, 8], { z0.d - z3.d }, z0.d[0]
+	fmla	za.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d[0]
+	fmla	za.d[w8, 0], { z0.d - z4.d }, z0.d[0]
+	fmla	za.d[w8, 0], { z1.d - z4.d }, z0.d[0]
+	fmla	za.d[w8, 0], { z2.d - z5.d }, z0.d[0]
+	fmla	za.d[w8, 0], { z3.d - z6.d }, z0.d[0]
+	fmla	za.d[w8, 0], { z0.d - z3.d }, z16.d[0]
+	fmla	za.d[w8, 0], { z0.d - z3.d }, z0.d[-1]
+	fmla	za.d[w8, 0], { z0.d - z3.d }, z0.d[2]
+
+	fmla	za.d[w0, 0], { z0.d - z1.d }, z0.d
+	fmla	za.d[w31, 0], { z0.d - z1.d }, z0.d
+	fmla	za.d[w8, 1<<63], { z0.d - z1.d }, z0.d
+	fmla	za.d[w8, 0], { z0.d - z1.d }, z31.d
+	fmla	za.d[w8, 0:0], { z0.d - z1.d }, z0.d
+	fmla	za.d[w8, 0:-1], { z0.d - z1.d }, z0.d
+	fmla	za.d[w8, 0:1], { z0.d - z1.d }, z0.d
+	fmla	za.d[w8, 0:100], { z0.d - z1.d }, z0.d
+
+	fmla	za.d[w7, 0], { z0.d - z1.d }, z0.d
+	fmla	za.d[w12, 0], { z0.d - z1.d }, z0.d
+	fmla	za.d[w8, -1], { z0.d - z1.d }, z0.d
+	fmla	za.d[w8, 8], { z0.d - z1.d }, z0.d
+	fmla	za.d[w8, 0], { z0.d - z1.d }, z16.d
+
+	fmla	za.d[w7, 0], { z0.d - z3.d }, z0.d
+	fmla	za.d[w12, 0], { z0.d - z3.d }, z0.d
+	fmla	za.d[w8, -1], { z0.d - z3.d }, z0.d
+	fmla	za.d[w8, 8], { z0.d - z3.d }, z0.d
+	fmla	za.d[w8, 0], { z0.d - z3.d }, z16.d
+
+	fmla	za.d[w8, 0], { z0.d - z2.d }, z0.d
+	fmla	za.d[w8, 0], { z0.d - z4.d }, z0.d
+	fmla	za.d[w8, 0], { z0.d, z1.d, z2.d }, z0.d
+	fmla	za.d[w8, 0], { z0.d, z1.d, z5.d }, z0.d
+
+	fmla	za.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d
+	fmla	za.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d
+	fmla	za[w8, 0], { z0.d - z1.d }, z0.d
+	fmla	za.d[w8, 0], { z0 - z1 }, z0.d
+	fmla	za.d[w8, 0], { z0.d - z1.d }, z0
+	fmla	za[w8, 0], { z0.d - z1.d }, z0
+
+	fmla	za.d[w7, 0], { z0.d - z1.d }, { z0.d - z1.d }
+	fmla	za.d[w12, 0], { z0.d - z1.d }, { z0.d - z1.d }
+	fmla	za.d[w8, -1], { z0.d - z1.d }, { z0.d - z1.d }
+	fmla	za.d[w8, 8], { z0.d - z1.d }, { z0.d - z1.d }
+	fmla	za.d[w8, 0], { z1.d - z2.d }, { z0.d - z1.d }
+	fmla	za.d[w8, 0], { z0.d - z1.d }, { z15.d - z16.d }
+	fmla	za.d[w8, 0], { z0.d - z1.d }, { z31.d, z0.d }
+
+	fmla	za.d[w7, 0], { z0.d - z3.d }, { z0.d - z3.d }
+	fmla	za.d[w12, 0], { z0.d - z3.d }, { z0.d - z3.d }
+	fmla	za.d[w8, -1], { z0.d - z3.d }, { z0.d - z3.d }
+	fmla	za.d[w8, 8], { z0.d - z3.d }, { z0.d - z3.d }
+	fmla	za.d[w8, 0], { z1.d - z4.d }, { z0.d - z3.d }
+	fmla	za.d[w8, 0], { z2.d - z5.d }, { z0.d - z3.d }
+	fmla	za.d[w8, 0], { z3.d - z6.d }, { z0.d - z3.d }
+	fmla	za.d[w8, 0], { z0.d - z3.d }, { z15.d - z18.d }
+	fmla	za.d[w8, 0], { z0.d - z3.d }, { z29.d, z30.d, z31.d, z0.d }
+
+	fmla	za.d[w8, 0], { z0.d - z2.d }, { z0.d - z1.d }
+	fmla	za.d[w8, 0], { z0.d - z3.d }, { z0.d - z1.d }
+	fmla	za.d[w8, 0], { z0.d - z1.d }, { z0.d - z2.d }
+	fmla	za.d[w8, 0], { z0.d - z1.d }, { z0.d - z3.d }
+	fmla	za.d[w8, 0], { z0.d - z1.d }, { z0.d - z4.d }
+
+	fmla	za.d[w8, 0, vgx4], { z0.d - z1.d }, { z0.d - z3.d }
+	fmla	za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z1.d }
+	fmla	za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z3.d }
+	fmla	za.d[w8, 0, vgx2], { z0.d - z3.d }, { z0.d - z1.d }
+	fmla	za[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }
+	fmla	za[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }
diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.d b/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.d
new file mode 100644
index 0000000..23c66a9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a+sme2
+#source: sme2-f64f64-2.s
+#error_output: sme2-f64f64-2-noarch.l
diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l b/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l
new file mode 100644
index 0000000..5ab290d
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2-noarch.l
@@ -0,0 +1,117 @@
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w10,2\],{z6\.d-z7\.d},z5\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w9,3\],{z8\.d-z11\.d},z14\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},Z0\.D'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d,z0\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d-z0\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w9,5\],{z9\.d-z10\.d},z6\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},Z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d,z0\.d,z1\.d,z2\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z31\.d-z2\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,2\],{z23\.d-z26\.d},z13\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},{Z0\.d-Z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},{Z0\.D-Z1\.D}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z30\.d-z31\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z1\.d},{z30\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w10,1\],{z22\.d-z23\.d},{z18\.d-z19\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},{Z0\.d-Z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},{Z0\.D-Z3\.D}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,7\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z28\.d-z31\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w8,0\],{z0\.d-z3\.d},{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmla za\.d\[w11,3\],{z16\.d-z19\.d},{z24\.d-z27\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w10,2\],{z6\.d-z7\.d},z5\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w9,3\],{z8\.d-z11\.d},z14\.d\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},Z0\.D'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d,z0\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d-z0\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w9,5\],{z9\.d-z10\.d},z6\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},Z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d,z0\.d,z1\.d,z2\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z31\.d-z2\.d},z0\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,2\],{z23\.d-z26\.d},z13\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},{Z0\.d-Z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},{Z0\.D-Z1\.D}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z30\.d-z31\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z1\.d},{z30\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w10,1\],{z22\.d-z23\.d},{z18\.d-z19\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},{Z0\.d-Z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},{Z0\.D-Z3\.D}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,7\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z28\.d-z31\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w8,0\],{z0\.d-z3\.d},{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `fmls za\.d\[w11,3\],{z16\.d-z19\.d},{z24\.d-z27\.d}'
diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2.d b/gas/testsuite/gas/aarch64/sme2-f64f64-2.d
new file mode 100644
index 0000000..dbc8d65
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2.d
@@ -0,0 +1,125 @@
+#as: -march=armv8-a+sme2+sme-f64f64
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+:	c1d00000 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+:	c1d00000 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+:	c1d00000 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+:	c1d06000 	fmla	za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+:	c1d00007 	fmla	za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+:	c1d003c0 	fmla	za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d\[0\]
+[^:]+:	c1df0000 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d\[0\]
+[^:]+:	c1d00400 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[1\]
+[^:]+:	c1d544c2 	fmla	za\.d\[w10, 2, vgx2\], {z6\.d-z7\.d}, z5\.d\[1\]
+[^:]+:	c1d08000 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+:	c1d08000 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+:	c1d08000 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+:	c1d0e000 	fmla	za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+:	c1d08007 	fmla	za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+:	c1d08380 	fmla	za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d\[0\]
+[^:]+:	c1df8000 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d\[0\]
+[^:]+:	c1d08400 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[1\]
+[^:]+:	c1dea503 	fmla	za\.d\[w9, 3, vgx4\], {z8\.d-z11\.d}, z14\.d\[1\]
+[^:]+:	c1601800 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+:	c1601800 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+:	c1601800 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+:	c1601800 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+:	c1607800 	fmla	za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+:	c1601807 	fmla	za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+:	c1601bc0 	fmla	za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d
+[^:]+:	c1601be0 	fmla	za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
+[^:]+:	c1601be0 	fmla	za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
+[^:]+:	c16f1800 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d
+[^:]+:	c1663925 	fmla	za\.d\[w9, 5, vgx2\], {z9\.d-z10\.d}, z6\.d
+[^:]+:	c1701800 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+:	c1701800 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+:	c1701800 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+:	c1701800 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+:	c1707800 	fmla	za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+:	c1701807 	fmla	za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+:	c1701b80 	fmla	za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d
+[^:]+:	c1701be0 	fmla	za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
+[^:]+:	c1701be0 	fmla	za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
+[^:]+:	c17f1800 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d
+[^:]+:	c17d7ae2 	fmla	za\.d\[w11, 2, vgx4\], {z23\.d-z26\.d}, z13\.d
+[^:]+:	c1e01800 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+:	c1e01800 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+:	c1e01800 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+:	c1e01800 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+:	c1e07800 	fmla	za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+:	c1e01807 	fmla	za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+:	c1e01bc0 	fmla	za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, {z0\.d-z1\.d}
+[^:]+:	c1fe1800 	fmla	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z30\.d-z31\.d}
+[^:]+:	c1f25ac1 	fmla	za\.d\[w10, 1, vgx2\], {z22\.d-z23\.d}, {z18\.d-z19\.d}
+[^:]+:	c1e11800 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+:	c1e11800 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+:	c1e11800 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+:	c1e11800 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+:	c1e17800 	fmla	za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+:	c1e11807 	fmla	za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+:	c1e11b80 	fmla	za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, {z0\.d-z3\.d}
+[^:]+:	c1fd1800 	fmla	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z28\.d-z31\.d}
+[^:]+:	c1f97a03 	fmla	za\.d\[w11, 3, vgx4\], {z16\.d-z19\.d}, {z24\.d-z27\.d}
+[^:]+:	c1d00010 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+:	c1d00010 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+:	c1d00010 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+:	c1d06010 	fmls	za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+:	c1d00017 	fmls	za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d\[0\]
+[^:]+:	c1d003d0 	fmls	za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d\[0\]
+[^:]+:	c1df0010 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d\[0\]
+[^:]+:	c1d00410 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d\[1\]
+[^:]+:	c1d544d2 	fmls	za\.d\[w10, 2, vgx2\], {z6\.d-z7\.d}, z5\.d\[1\]
+[^:]+:	c1d08010 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+:	c1d08010 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+:	c1d08010 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+:	c1d0e010 	fmls	za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+:	c1d08017 	fmls	za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d\[0\]
+[^:]+:	c1d08390 	fmls	za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d\[0\]
+[^:]+:	c1df8010 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d\[0\]
+[^:]+:	c1d08410 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d\[1\]
+[^:]+:	c1dea513 	fmls	za\.d\[w9, 3, vgx4\], {z8\.d-z11\.d}, z14\.d\[1\]
+[^:]+:	c1601808 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+:	c1601808 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+:	c1601808 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+:	c1601808 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+:	c1607808 	fmls	za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+:	c160180f 	fmls	za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d
+[^:]+:	c1601bc8 	fmls	za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d
+[^:]+:	c1601be8 	fmls	za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
+[^:]+:	c1601be8 	fmls	za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
+[^:]+:	c16f1808 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d
+[^:]+:	c166392d 	fmls	za\.d\[w9, 5, vgx2\], {z9\.d-z10\.d}, z6\.d
+[^:]+:	c1701808 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+:	c1701808 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+:	c1701808 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+:	c1701808 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+:	c1707808 	fmls	za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+:	c170180f 	fmls	za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d
+[^:]+:	c1701b88 	fmls	za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d
+[^:]+:	c1701be8 	fmls	za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
+[^:]+:	c1701be8 	fmls	za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
+[^:]+:	c17f1808 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d
+[^:]+:	c17d7aea 	fmls	za\.d\[w11, 2, vgx4\], {z23\.d-z26\.d}, z13\.d
+[^:]+:	c1e01808 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+:	c1e01808 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+:	c1e01808 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+:	c1e01808 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+:	c1e07808 	fmls	za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+:	c1e0180f 	fmls	za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+:	c1e01bc8 	fmls	za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, {z0\.d-z1\.d}
+[^:]+:	c1fe1808 	fmls	za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z30\.d-z31\.d}
+[^:]+:	c1f25ac9 	fmls	za\.d\[w10, 1, vgx2\], {z22\.d-z23\.d}, {z18\.d-z19\.d}
+[^:]+:	c1e11808 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+:	c1e11808 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+:	c1e11808 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+:	c1e11808 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+:	c1e17808 	fmls	za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+:	c1e1180f 	fmls	za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+:	c1e11b88 	fmls	za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, {z0\.d-z3\.d}
+[^:]+:	c1fd1808 	fmls	za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z28\.d-z31\.d}
+[^:]+:	c1f97a0b 	fmls	za\.d\[w11, 3, vgx4\], {z16\.d-z19\.d}, {z24\.d-z27\.d}
diff --git a/gas/testsuite/gas/aarch64/sme2-f64f64-2.s b/gas/testsuite/gas/aarch64/sme2-f64f64-2.s
new file mode 100644
index 0000000..005db42
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2-f64f64-2.s
@@ -0,0 +1,127 @@
+	fmla	za.d[w8, 0], { z0.d - z1.d }, z0.d[0]
+	fmla	za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d[0]
+	FMLA	ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d[0]
+	fmla	za.d[w11, 0], { z0.d - z1.d }, z0.d[0]
+	fmla	za.d[w8, 7], { z0.d - z1.d }, z0.d[0]
+	fmla	za.d[w8, 0], { z30.d - z31.d }, z0.d[0]
+	fmla	za.d[w8, 0], { z0.d - z1.d }, z15.d[0]
+	fmla	za.d[w8, 0], { z0.d - z1.d }, z0.d[1]
+	fmla	za.d[w10, 2], { z6.d - z7.d }, z5.d[1]
+
+	fmla	za.d[w8, 0], { z0.d - z3.d }, z0.d[0]
+	fmla	za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]
+	FMLA	ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D[0]
+	fmla	za.d[w11, 0], { z0.d - z3.d }, z0.d[0]
+	fmla	za.d[w8, 7], { z0.d - z3.d }, z0.d[0]
+	fmla	za.d[w8, 0], { z28.d - z31.d }, z0.d[0]
+	fmla	za.d[w8, 0], { z0.d - z3.d }, z15.d[0]
+	fmla	za.d[w8, 0], { z0.d - z3.d }, z0.d[1]
+	fmla	za.d[w9, 3], { z8.d - z11.d }, z14.d[1]
+
+	fmla	za.d[w8, 0], { z0.d - z1.d }, z0.d
+	fmla	za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d
+	FMLA	ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d
+	FMLA	ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, Z0.D
+	fmla	za.d[w11, 0], { z0.d - z1.d }, z0.d
+	fmla	za.d[w8, 7], { z0.d - z1.d }, z0.d
+	fmla	za.d[w8, 0], { z30.d - z31.d }, z0.d
+	fmla	za.d[w8, 0], { z31.d, z0.d }, z0.d
+	fmla	za.d[w8, 0], { z31.d - z0.d }, z0.d
+	fmla	za.d[w8, 0], { z0.d - z1.d }, z15.d
+	fmla	za.d[w9, 5], { z9.d - z10.d }, z6.d
+
+	fmla	za.d[w8, 0], { z0.d - z3.d }, z0.d
+	fmla	za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
+	FMLA	ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, Z0.d
+	FMLA	ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D
+	fmla	za.d[w11, 0], { z0.d - z3.d }, z0.d
+	fmla	za.d[w8, 7], { z0.d - z3.d }, z0.d
+	fmla	za.d[w8, 0], { z28.d - z31.d }, z0.d
+	fmla	za.d[w8, 0], { z31.d, z0.d, z1.d, z2.d }, z0.d
+	fmla	za.d[w8, 0], { z31.d - z2.d }, z0.d
+	fmla	za.d[w8, 0], { z0.d - z3.d }, z15.d
+	fmla	za.d[w11, 2], { z23.d - z26.d }, z13.d
+
+	fmla	za.d[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }
+	fmla	za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z1.d }
+	FMLA	ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, { Z0.d - Z1.d }
+	FMLA	ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, { Z0.D - Z1.D }
+	fmla	za.d[w11, 0], { z0.d - z1.d }, { z0.d - z1.d }
+	fmla	za.d[w8, 7], { z0.d - z1.d }, { z0.d - z1.d }
+	fmla	za.d[w8, 0], { z30.d - z31.d }, { z0.d - z1.d }
+	fmla	za.d[w8, 0], { z0.d - z1.d }, { z30.d - z31.d }
+	fmla	za.d[w10, 1], { z22.d - z23.d }, { z18.d - z19.d }
+
+	fmla	za.d[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }
+	fmla	za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+	FMLA	ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, { Z0.d - Z3.d }
+	FMLA	ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, { Z0.D - Z3.D }
+	fmla	za.d[w11, 0], { z0.d - z3.d }, { z0.d - z3.d }
+	fmla	za.d[w8, 7], { z0.d - z3.d }, { z0.d - z3.d }
+	fmla	za.d[w8, 0], { z28.d - z31.d }, { z0.d - z3.d }
+	fmla	za.d[w8, 0], { z0.d - z3.d }, { z28.d - z31.d }
+	fmla	za.d[w11, 3], { z16.d - z19.d }, { z24.d - z27.d }
+
+	fmls	za.d[w8, 0], { z0.d - z1.d }, z0.d[0]
+	fmls	za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d[0]
+	FMLS	ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d[0]
+	fmls	za.d[w11, 0], { z0.d - z1.d }, z0.d[0]
+	fmls	za.d[w8, 7], { z0.d - z1.d }, z0.d[0]
+	fmls	za.d[w8, 0], { z30.d - z31.d }, z0.d[0]
+	fmls	za.d[w8, 0], { z0.d - z1.d }, z15.d[0]
+	fmls	za.d[w8, 0], { z0.d - z1.d }, z0.d[1]
+	fmls	za.d[w10, 2], { z6.d - z7.d }, z5.d[1]
+
+	fmls	za.d[w8, 0], { z0.d - z3.d }, z0.d[0]
+	fmls	za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]
+	FMLS	ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D[0]
+	fmls	za.d[w11, 0], { z0.d - z3.d }, z0.d[0]
+	fmls	za.d[w8, 7], { z0.d - z3.d }, z0.d[0]
+	fmls	za.d[w8, 0], { z28.d - z31.d }, z0.d[0]
+	fmls	za.d[w8, 0], { z0.d - z3.d }, z15.d[0]
+	fmls	za.d[w8, 0], { z0.d - z3.d }, z0.d[1]
+	fmls	za.d[w9, 3], { z8.d - z11.d }, z14.d[1]
+
+	fmls	za.d[w8, 0], { z0.d - z1.d }, z0.d
+	fmls	za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d
+	FMLS	ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d
+	FMLS	ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, Z0.D
+	fmls	za.d[w11, 0], { z0.d - z1.d }, z0.d
+	fmls	za.d[w8, 7], { z0.d - z1.d }, z0.d
+	fmls	za.d[w8, 0], { z30.d - z31.d }, z0.d
+	fmls	za.d[w8, 0], { z31.d, z0.d }, z0.d
+	fmls	za.d[w8, 0], { z31.d - z0.d }, z0.d
+	fmls	za.d[w8, 0], { z0.d - z1.d }, z15.d
+	fmls	za.d[w9, 5], { z9.d - z10.d }, z6.d
+
+	fmls	za.d[w8, 0], { z0.d - z3.d }, z0.d
+	fmls	za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
+	FMLS	ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, Z0.d
+	FMLS	ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D
+	fmls	za.d[w11, 0], { z0.d - z3.d }, z0.d
+	fmls	za.d[w8, 7], { z0.d - z3.d }, z0.d
+	fmls	za.d[w8, 0], { z28.d - z31.d }, z0.d
+	fmls	za.d[w8, 0], { z31.d, z0.d, z1.d, z2.d }, z0.d
+	fmls	za.d[w8, 0], { z31.d - z2.d }, z0.d
+	fmls	za.d[w8, 0], { z0.d - z3.d }, z15.d
+	fmls	za.d[w11, 2], { z23.d - z26.d }, z13.d
+
+	fmls	za.d[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }
+	fmls	za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z1.d }
+	FMLS	ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, { Z0.d - Z1.d }
+	FMLS	ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, { Z0.D - Z1.D }
+	fmls	za.d[w11, 0], { z0.d - z1.d }, { z0.d - z1.d }
+	fmls	za.d[w8, 7], { z0.d - z1.d }, { z0.d - z1.d }
+	fmls	za.d[w8, 0], { z30.d - z31.d }, { z0.d - z1.d }
+	fmls	za.d[w8, 0], { z0.d - z1.d }, { z30.d - z31.d }
+	fmls	za.d[w10, 1], { z22.d - z23.d }, { z18.d - z19.d }
+
+	fmls	za.d[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }
+	fmls	za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+	FMLS	ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, { Z0.d - Z3.d }
+	FMLS	ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, { Z0.D - Z3.D }
+	fmls	za.d[w11, 0], { z0.d - z3.d }, { z0.d - z3.d }
+	fmls	za.d[w8, 7], { z0.d - z3.d }, { z0.d - z3.d }
+	fmls	za.d[w8, 0], { z28.d - z31.d }, { z0.d - z3.d }
+	fmls	za.d[w8, 0], { z0.d - z3.d }, { z28.d - z31.d }
+	fmls	za.d[w11, 3], { z16.d - z19.d }, { z24.d - z27.d }