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Replace QEMU_EXT_OPTS dict with QEMU_SUPPORTED_EXTS set for simpler
extension handling. QEMU now uses unified naming, so we only need to
track which extensions are supported rather than mapping to different
option strings.
Changes to march-to-cpu-opt:
- Replace QEMU_EXT_OPTS dict with QEMU_SUPPORTED_EXTS set
- Update print_qemu_cpu() to use "{ext}=true" format directly
- Use rv64i/rv32i/rv64e/rv32e CPU models instead of rv64/rv32
The rv64/rv32 CPU models enable many extensions by default, which can
conflict with explicit extension settings. The rv64i/rv32i/rv64e/rv32e
models are bare bones CPUs that only enable the base I or E extension,
requiring all other extensions to be explicitly enabled. This gives us
full control over which extensions are active and eliminates the need
for manual f/d disable logic for *inx extensions.
Reference: QEMU commit deb0ff0c777d ("target/riscv: add rv32i, rv32e
and rv64e CPUs")
Add new script update-ext-cpu-opt to automatically sync the supported
extension list from QEMU source (target/riscv/cpu.c). The script:
- Parses ISA_EXT_DATA_ENTRY macros from QEMU
- Parses MISA_EXT_INFO for base extensions (a, b, c, d, f, m, v)
- Filters out has_priv_* extensions (no explicit switch)
- Filters out s* supervisor extensions
- Filters out i, e, g, s, u, h from MISA_EXT_INFO
- Supports --dry-run for preview
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Add zvfh and zvfhmin to the list of ISA extension supported by QEMU.
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Default behavior of qemu is treat tail/mask agnostic as tail/mask undisturbed,
and this may hidding some problem, one example is
[PR115725](https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115725) for
GCC.
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See this for detail:
https://www.qemu.org/docs/master/about/deprecated.html#risc-v-cpu-properties-which-start-with-capital-z-since-8-2
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Signed-off-by: Pan Li <pan2.li@intel.com>
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According to the ISA, the zve32/zve64 xdf decides the elen of the
RVV. Thus we should pick up extension instead of xlen for spike
varch generation.
Signed-off-by: Pan Li <pan2.li@intel.com>
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* Refactor CPU options for exacting common part between qemu and spike.
* Inject CPU options to spike run command line.
The below common CPU options are extracted to common part.
* xlen
* vlen
* extensions
The above CPU options will be leveraged to build the run arguments for
both the qemu and spike, for example.
QEMU: qemu-riscv64 -cpu rv64,v=true,vlen=1024,elen=64,vext_spec=v1.0
SPIKE: spike --isa=rv64imafdcv_zicsr_zifencei_zmmul --varch=vlen:1024,elen:64
Signed-off-by: Pan Li <pan2.li@intel.com>
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Some testcases in GCC's testsuite check stdout.
Qemu will print a warning if the vector spec is not specified which will cause those testcases to fail.
The warning:
vector version is not specified, use the default value v1.0
Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
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This could help multi-lib testing, but the price is slightly increase
the testing time since it will need to extract ELF attribute from binary
before running qemu.
But I think the cost is acceptable compare to make build system more
complicate, and actually we already use this approach in our internal stuffs
for years.
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Add unittest to march-to-cpu-opt
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Support testing zdinx/zfinx/zhinx.
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https://github.com/riscv-collab/riscv-gnu-toolchain/pull/1167 has found
some bug, and I realized the testing of march-to-cpu-opt is...not well,
so spend some time to improve that a little bit, it's not complete testing,
but at least it's a start :P
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If test --with-arch=rv32imc_zve128x
NameError: name 'arch' is not defined
Signed-off-by: Kwanghoon Son <kwangson@yahoo.com>
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- We don't set correct qemu option for zdinx/zfinx/zhinx, this patch is
fixing the march-to-cpu-opt, which is a script translate -march string
to qemu options.
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- Parse that from `--with-arch=` option
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