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path: root/opcodes/riscv-dis.c
AgeCommit message (Expand)AuthorFilesLines
2024-01-05RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvliJin Ma1-0/+22
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2023-12-01RISC-V: Make riscv_is_mapping_symbol stricterPatrick O'Neill1-3/+1
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu1-0/+27
2023-11-30RISC-V: Avoid updating state until symbol is foundPatrick O'Neill1-12/+31
2023-11-24RISC-V: disallow x0 with certain macro-insnsJan Beulich1-0/+3
2023-11-23RISC-V: Add CSRs for T-Head VECTOR vendor extensionJin Ma1-2/+12
2023-11-07RISC-V: Add support for XCValu extension in CV32E40PMary Bennett1-0/+4
2023-11-07RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett1-0/+11
2023-10-13RISC-V: Add support for numbered ISA mapping stringsJoseph Faulls1-1/+15
2023-09-07RISC-V: Clarify the naming rules of vendor operands.Nelson Chu1-81/+86
2023-08-15RISC-V: remove indirection from register tablesJan Beulich1-6/+6
2023-08-02Revert "2.41 Release sources"Sam James1-1/+15
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-15/+1
2023-07-28Fix typo in riscv-dis.c commentTsukasa OI1-1/+1
2023-07-18RISC-V: Supports Zcb extension.Jiawei1-0/+14
2023-07-01RISC-V: Add support for the Zvbb ISA extensionChristoph Müllner1-0/+4
2023-06-30RISC-V: Add support for the Zfa extensionChristoph Müllner1-0/+16
2023-05-19RISC-V: Minor improvements for dis-assembler.Nelson Chu1-21/+37
2023-04-18RISC-V: Cache the latest mapping symbol and its boundary.Kito Cheng1-0/+43
2023-03-31RISC-V: Allocate "various" operand typeTsukasa OI1-5/+21
2023-03-21RISC-V: Fix disassemble fetch fail return value.Jiawei1-2/+2
2023-02-03RISC-V: don't disassemble unrecognized insns as .byteJan Beulich1-30/+20
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-11-28RISC-V: Better support for long instructions (disassembler)Tsukasa OI1-5/+9
2022-10-28RISC-V: Output mapping symbols with ISA string.Nelson Chu1-0/+9
2022-10-14opcodes/riscv-dis.c: Remove last_map_stateTsukasa OI1-3/+0
2022-10-14opcodes/riscv-dis.c: Make XLEN variable staticTsukasa OI1-1/+1
2022-10-14opcodes/riscv-dis.c: Use bool type whenever possibleTsukasa OI1-5/+5
2022-10-14opcodes/riscv-dis.c: Tidying with spacingTsukasa OI1-1/+1
2022-10-14opcodes/riscv-dis.c: Tidying with comments/clarityTsukasa OI1-4/+21
2022-10-06RISC-V: Print XTheadMemPair literal as "immediate"Tsukasa OI1-1/+1
2022-10-06RISC-V: Fix T-Head immediate types on printingTsukasa OI1-4/+4
2022-10-06RISC-V: Print comma and tabs as the "text" styleTsukasa OI1-11/+20
2022-10-06RISC-V: Optimize riscv_disassemble_data printfTsukasa OI1-6/+4
2022-10-06RISC-V: Fix printf argument types corresponding %xTsukasa OI1-7/+7
2022-10-06RISC-V: Fix immediates to have "immediate" styleTsukasa OI1-5/+5
2022-10-04RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI1-1/+1
2022-10-04opcodes/riscv: style csr names as registersAndrew Burgess1-1/+2
2022-09-30RISC-V: fix build after "Add support for arbitrary immediate encoding formats"Jan Beulich1-2/+2
2022-09-22RISC-V: Add support for literal instruction argumentsChristoph Müllner1-0/+9
2022-09-22RISC-V: Add support for arbitrary immediate encoding formatsChristoph Müllner1-0/+34
2022-09-22RISC-V: Remove "b" operand type from disassemblerTsukasa OI1-1/+0
2022-09-06opcodes: Add non-enum disassembler optionsTsukasa OI1-0/+2
2022-09-02RISC-V: Print highest address (-1) on the disassemblerTsukasa OI1-6/+14
2022-09-02RISC-V: PR29342, Fix RV32 disassembler address computationTsukasa OI1-1/+7
2022-07-07RISC-V: Fix disassembling Zfinx with -M numericTsukasa OI1-1/+1
2022-04-30opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblersThomas Hebb1-16/+12
2022-04-04opcodes/riscv: implement style support in the disassemblerAndrew Burgess1-72/+121
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI1-0/+4
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