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path: root/opcodes/i386-dis.c
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2021-03-22Add startswith function and use it instead of CONST_STRNEQ.Martin Liska1-12/+12
2021-03-12Re: x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Alan Modra1-1/+1
2021-03-11x86: re-order logic in OP_XMM()Jan Beulich1-35/+31
2021-03-11x86: drop a few redundant EVEX-related checksJan Beulich1-4/+3
2021-03-11x86: remove stray uses of xmmq_modeJan Beulich1-4/+1
2021-03-10x86/Intel: correct AVX512 S/G disassemblyJan Beulich1-70/+12
2021-03-10x86: re-arrange enumerator and table entry orderJan Beulich1-77/+79
2021-03-10x86: reuse further VEX entries for EVEXJan Beulich1-17/+11
2021-03-10x86: reuse VEX entries for EVEX vperm{q,pd}Jan Beulich1-4/+2
2021-03-10x86: re-arrange order of decode for various EVEX opcodesJan Beulich1-79/+42
2021-03-10x86: re-arrange order of decode for various mask reg opcodesJan Beulich1-600/+328
2021-03-10x86: re-arrange order of decode for various VEX opcodesJan Beulich1-154/+70
2021-03-10x86: re-arrange order of decode for various legacy opcodesJan Beulich1-70/+28
2021-03-10x86: correct decoding of nop/reserved space (0f18 ... 0x1f)Jan Beulich1-48/+45
2021-03-09x86-64: make SYSEXIT handling similar to SYSRET'sJan Beulich1-1/+1
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-11-29x86: Do not dump DS/CS segment overrides for branch hintsBorislav Petkov1-2/+11
2020-11-14x86: Ignore CS/DS/ES/SS segment-override prefixes in 64-bit modeBorislav Petkov1-5/+20
2020-10-26Change avxvnni disassembler output from {vex3} to {vex}Cui,Lili1-1/+0
2020-10-20Add AMD znver3 processor supportGanesh Gopalasubramanian1-0/+41
2020-10-14x86: Support Intel AVX VNNIH.J. Lu1-6/+37
2020-10-14x86: Add support for Intel HRESET instructionLili Cui1-1/+24
2020-10-14x86: Support Intel UINTRLili Cui1-6/+69
2020-10-05x86-64: Always display suffix for %LQ in 64bitH.J. Lu1-1/+1
2020-10-05x86: Clear modrm if not neededH.J. Lu1-4/+8
2020-09-25Put together MOD_VEX_0F38* in i386-dis.c,Cui,Lili1-62/+62
2020-09-24Add support for Intel TDX instructions.Cui,Lili1-4/+61
2020-09-23Enable support to Intel Keylocker instructionsTerry Guo1-7/+100
2020-09-02ubsan: i386-dis.cAlan Modra1-13/+13
2020-07-21Revert "x86: Don't display eiz with no scale"Jan Beulich1-1/+1
2020-07-15x86: Don't display eiz with no scaleH.J. Lu1-1/+1
2020-07-15x86: move putop() case labels to restore alphabetic sortingJan Beulich1-49/+48
2020-07-15x86: make PUSH/POP disassembly uniformJan Beulich1-30/+20
2020-07-15x86: avoid attaching suffixes to unambiguous insnsJan Beulich1-99/+44
2020-07-14x86-64: Zero-extend lower 32 bits displacement to 64 bitsH.J. Lu1-2/+7
2020-07-14x86/Intel: debug registers are named DRnJan Beulich1-1/+1
2020-07-14x86: drop Rm and the 'L' macroJan Beulich1-74/+54
2020-07-14x86: drop Rdq, Rd, and MaskRJan Beulich1-56/+60
2020-07-14x86: simplify decode of opcodes valid only without any (embedded) prefixJan Beulich1-135/+42
2020-07-14x86: also use %BW / %DQ for kshift*Jan Beulich1-65/+17
2020-07-14x86: simplify decode of opcodes valid with (embedded) 66 prefix onlyJan Beulich1-3474/+788
2020-07-14x86: drop further EVEX table entries that can be served by VEX onesJan Beulich1-12/+8
2020-07-14x86: drop need_vex_regJan Beulich1-48/+15
2020-07-14x86: drop Vex128 and Vex256Jan Beulich1-53/+45
2020-07-14x86: replace %LW by %DQJan Beulich1-9/+9
2020-07-14x86: merge/move logic determining the EVEX disp8 shiftJan Beulich1-29/+16
2020-07-14x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W}Jan Beulich1-12/+7
2020-07-14x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel modeJan Beulich1-37/+15
2020-07-14x86: fold VCMP_Fixup() into CMP_Fixup()Jan Beulich1-70/+45
2020-07-14x86: don't disassemble MOVBE with two suffixesJan Beulich1-43/+5
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