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| author | Lili Cui <lili.cui@intel.com> | 2020-10-14 04:52:11 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-10-14 04:53:59 -0700 |
| commit | c1fa250ae1604d3337cf63279503a737c9377574 (patch) | |
| tree | f47d5dab92a4856a64e80b87f35a20d153e82fac /opcodes/i386-dis.c | |
| parent | f64c42a9fb19409bb45d86d4b78f0465980dfcba (diff) | |
| download | fsf-binutils-gdb-c1fa250ae1604d3337cf63279503a737c9377574.zip fsf-binutils-gdb-c1fa250ae1604d3337cf63279503a737c9377574.tar.gz fsf-binutils-gdb-c1fa250ae1604d3337cf63279503a737c9377574.tar.bz2 | |
x86: Add support for Intel HRESET instruction
gas/
* NEWS: Add Intel HRESET.
* config/tc-i386.c (cpu_arch): Add .hreset.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document .hreset, nohreset.
* testsuite/gas/i386/i386.exp: Run HRESET tests.
* testsuite/gas/i386/hreset.d: New file.
* testsuite/gas/i386/x86-64-hreset.d: Likewise.
* testsuite/gas/i386/hreset.s: Likewise.
opcodes/
* i386-dis.c (PREFIX_0F3A0F): New.
(MOD_0F3A0F_PREFIX_1): Likewise.
(REG_0F3A0F_PREFIX_1_MOD_3): Likewise.
(RM_0F3A0F_P_1_MOD_3_REG_0): Likewise.
(prefix_table): Add PREFIX_0F3A0F.
(mod_table): Add MOD_0F3A0F_PREFIX_1.
(reg_table): Add REG_0F3A0F_PREFIX_1_MOD_3.
(rm_table): Add RM_0F3A0F_P_1_MOD_3_REG_0.
* i386-gen.c (cpu_flag_init): Add HRESET_FLAGS,
CPU_ANY_HRESET_FLAGS.
(cpu_flags): Add CpuHRESET.
(output_i386_opcode): Allow 4 byte base_opcode.
* i386-opc.h (enum): Add CpuHRESET.
(i386_cpu_flags): Add cpuhreset.
* i386-opc.tbl: Add Intel HRESET instruction.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
Diffstat (limited to 'opcodes/i386-dis.c')
| -rw-r--r-- | opcodes/i386-dis.c | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index a55a629..f1d1edf 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -692,6 +692,7 @@ enum REG_0F1C_P_0_MOD_0, REG_0F1E_P_1_MOD_3, REG_0F38D8_PREFIX_1, + REG_0F3A0F_PREFIX_1_MOD_3, REG_0F71, REG_0F72, REG_0F73, @@ -799,6 +800,7 @@ enum MOD_0F38F9, MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1, + MOD_0F3A0F_PREFIX_1, MOD_62_32BIT, MOD_C4_32BIT, MOD_C5_32BIT, @@ -944,6 +946,7 @@ enum RM_0F01_REG_5_MOD_3, RM_0F01_REG_7_MOD_3, RM_0F1E_P_1_MOD_3_REG_7, + RM_0F3A0F_P_1_MOD_3_REG_0, RM_0FAE_REG_6_MOD_3_P_0, RM_0FAE_REG_7_MOD_3, RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 @@ -1037,6 +1040,7 @@ enum PREFIX_0F38F8, PREFIX_0F38FA, PREFIX_0F38FB, + PREFIX_0F3A0F, PREFIX_VEX_0F10, PREFIX_VEX_0F11, PREFIX_VEX_0F12, @@ -2927,6 +2931,10 @@ static const struct dis386 reg_table[][8] = { { "aesencwide256kl", { M }, 0 }, { "aesdecwide256kl", { M }, 0 }, }, + /* REG_0F3A0F_PREFIX_1_MOD_3 */ + { + { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) }, + }, /* REG_0F71 */ { { Bad_Opcode }, @@ -3713,6 +3721,12 @@ static const struct dis386 prefix_table[][4] = { { MOD_TABLE (MOD_0F38FB_PREFIX_1) }, }, + /* PREFIX_0F3A0F */ + { + { Bad_Opcode }, + { MOD_TABLE (MOD_0F3A0F_PREFIX_1)}, + }, + /* PREFIX_VEX_0F10 */ { { "vmovups", { XM, EXx }, 0 }, @@ -4938,7 +4952,7 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* f0 */ - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F3A0F) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8399,6 +8413,11 @@ static const struct dis386 mod_table[][2] = { { "encodekey256", { Gd, Ed }, 0 }, }, { + /* MOD_0F3A0F_PREFIX_1 */ + { Bad_Opcode }, + { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) }, + }, + { /* MOD_62_32BIT */ { "bound{S|}", { Gv, Ma }, 0 }, { EVEX_TABLE (EVEX_0F) }, @@ -8963,6 +8982,10 @@ static const struct dis386 rm_table[][8] = { { "nopQ", { Ev }, 0 }, }, { + /* RM_0F3A0F_P_1_MOD_3_REG_0 */ + { "hreset", { Skip_MODRM, Ib }, 0 }, + }, + { /* RM_0FAE_REG_6_MOD_3 */ { "mfence", { Skip_MODRM }, 0 }, }, |