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2023-07-01Bump riscv-isa-sim from `740e635` to `f45f726`dependabot[bot]1-0/+0
2023-06-01Bump riscv-isa-sim from `929ff56` to `740e635`dependabot[bot]1-0/+0
2023-04-01Bump riscv-isa-sim from `d1ae27b` to `929ff56`dependabot[bot]1-0/+0
2023-03-01Bump riscv-isa-sim from `e2a364a` to `d1ae27b`dependabot[bot]1-0/+0
2023-02-01Bump riscv-isa-sim from `3349dc5` to `e2a364a`dependabot[bot]1-0/+0
2022-12-22Bump riscv-isa-sim from `adfaef0` to `3349dc5`dependabot[bot]1-0/+0
2022-12-09Bump everythingJerry Zhao1-0/+0
2020-03-29bump spike, tests, openocdAndrew Waterman1-0/+0
2020-03-05bump spike, testsAndrew Waterman1-0/+0
2020-02-11fesvr: bump for merged to master versionMegan Wachs1-0/+0
2020-02-11fesvr: bump to pick up more DMACTIVE fixesMegan Wachs1-0/+0
2020-02-11riscv-isa-sim: bump to master commit with dmactive FESVR fixMegan Wachs1-0/+0
2020-02-10Bump riscv-isa-sim to the latest to pick up DMACTIVE fixMegan Wachs1-0/+0
2019-04-03Merge fesvr into spike repo; bump spike to v1.0.0Andrew Waterman1-0/+0
2019-02-28bump spike for fix (#276)Srivatsa Yogendra1-0/+0
2019-01-28bumping spike for pmp fix (#272)Srivatsa Yogendra1-0/+0
2018-12-21bumping isa-sim for pmp fix (#267)Srivatsa Yogendra1-0/+0
2018-10-18bump spike for pmp registers (#260)Srivatsa Yogendra1-0/+0
2018-09-22Bump riscv-fesvr and riscv-isa-sim (#246)Shreesha Srinath1-0/+0
2018-09-05debug: bump Spike to support custom registersMegan Wachs1-0/+0
2018-08-22Bump tests, spike, openocd (#236)Andrew Waterman1-0/+0
2018-05-17Bump OpenOCD, spike, GNU tools (incl. gdb), and testsTim Newsome1-0/+0
2018-04-30Bump SpikeGleb Gagarin1-0/+0
2018-04-13Bump OpenOCD, GNU tools (incl. gdb), and testsTim Newsome1-0/+0
2018-02-20Bump OpenOCD, spike, testsTim Newsome1-0/+0
2017-12-21Bump tools to get small_progbuf and xml_registersTim Newsome1-0/+0
2017-12-12Bump fesvr/spike/opcodes/pk/tests for tval/satp CSR renaming (#158)Andrew Waterman1-0/+0
2017-11-15bumped spike versionGleb Gagarin1-0/+0
2017-11-09bump tests for rv64mi-p-ecall fixAndrew Waterman1-0/+0
2017-10-31Bump riscv-tests, riscv-openocd, and riscv-isa-sim.Richard Xia1-0/+0
2017-06-21bump spike (#97)Andrew Waterman1-0/+0
2017-06-08Bump gnu-toolchain, openocd, and isa-sim to do a releasePalmer Dabbelt1-0/+0
2017-05-23Bump spike, to disable werrorPalmer Dabbelt1-0/+0
2017-05-17Bump all the submodules from the debug-0.13 -> priv-1.10 mergePalmer Dabbelt1-0/+0
2017-05-15bump spike to allow testing debug-checkMegan Wachs1-0/+0
2017-05-01Use ELF entry point to set spike's default start addressAndrew Waterman1-0/+0
2017-05-01bump spike (#67)Yunsup Lee1-0/+0
2017-04-10Implement new FP encodingAndrew Waterman1-0/+0
2017-03-31bump spikeYunsup Lee1-0/+0
2017-03-30New PMP encodingAndrew Waterman1-0/+0
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman1-0/+0
2017-03-26Bump spike, tests, pkAndrew Waterman1-0/+0
2017-03-23WIP on priv-1.10Andrew Waterman1-0/+0
2017-03-09WIP on priv-1.10Andrew Waterman1-0/+0
2017-01-04Delete obsolete references to JOBS variableAndrew Waterman1-0/+0
2016-11-16Bump riscv-tests and riscv-isa-sim to pull in changes related to OpenOCD GDB ...Richard Xia1-0/+0
2016-10-25Bump riscv-tests to include debug tool improvements. (#46)Richard Xia1-0/+0
2016-10-10bump spikeAndrew Waterman1-0/+0
2016-09-21bump gcc, spike, pk, testsAndrew Waterman1-0/+0
2016-08-26WIP on priv-1.9.1Andrew Waterman1-0/+0
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