Replace Vecf(init) with VecInit()
Replace Wire(init) with WireDefault()
Replace Module(clock, reset) with withClockAndReset
Replace chiselCloneType with chiselTypeOf
Add asUInt to expressions that now return Bits

Don't merge this commit until we verify that the chisel3 changes are desirable.

remove header from resources

SERDES Fix

update for debug apb & regiontype in rocket-chip

comments on bootrom

Enable overriding of source ID bits in SerialAdapter

Update Switcher for rocket-chip Feb 14 2019

Add sinkId parameter for integration

Single mBus multi-port switcher support

Helps both top and testharness

Don't do anything special with simserial args

Fesvr handles this now so just pass on the plusargs and
they will be correctly ignored
Fixes #34

Fix periodchecker to not use timescale

Add README

Add prefix to vsrc, csrc and add bootrom to resources