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testchipip
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fix_missing_import

d8383843 · import <stdexcept> in testchip_tsi · Mar 22, 2022

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chisel-3.5-bump

aaf0cd18 · Convert fire() to fire · Jan 17, 2022

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ibex-integration

5917176c · Add changes to bootrom · Oct 02, 2021

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chisel-3.5

e78b1384 · update for latest chisel, remove toBool and chisel3.core. · Sep 16, 2021

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rtml

81341be7 · Merge remote-tracking branch 'origin/mockdram' into rtml · Apr 23, 2021

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mockdram

35c5b626 · Fix MockDRAM region replicaiton · Apr 23, 2021

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offchip-axi-setup

fd7760e2 · Update comment [ci skip] · Mar 22, 2021

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clock-mutex-mux

7812138d · Make ClockMutexMux respect depth parameter · Feb 10, 2021

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banked-buffer

b1993815 · Add TLBankedBuffer · Feb 05, 2021

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abe-temp-bgl

91c08ca1 · Properly setup Axi mem domain · Jan 28, 2021

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tsi-host-widget

39ed56be · Rename serialIfWidth | Use MasterPortParams | Small comment changes · Jan 04, 2021

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add-ci

3a949dfb · Reduce heap size · Dec 29, 2020

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no_supervisor_bootrom

00103634 · Bootrom support for systems with no S-mode (no MIDELEG) · Dec 22, 2020

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chisel34-bump

6fbb1b77 · Cleanup build.sbt | Bump versions · Nov 30, 2020

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block-dev-multiclock

b178da62 · [blkdev] Break assumption that client domain == manager domain · Nov 07, 2020

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unify-fesvr

56bfaa3f · Rename testchip_fesvr to testchip_tsi · Oct 09, 2020

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tile-reset-ctrl

b3aa1bea · Remove bootrom dumps · Oct 01, 2020

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diplomatic-clocks-dram

8f489545 · Add a form of ClockedIO with reset · Sep 29, 2020

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pbus-tl-mem

bd0ff2d0 · Add config to hang the serial TL mem off the PBus for the no-L2 case. · Sep 25, 2020

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bootrom-dump

28b44293 · Makefile should generate bootrom objdump by default · Sep 24, 2020

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