This reverts commit 0db73aaf.

This reverts commit aa459e01.

This reverts commit 80710752.

* A replacement for the previous object model structure. the new structure is distributed and does not rely on a traversal of the design except in the core for now (this may be replaced as well). Relationships between parents and children are stored and later traversed. The same getOMComponents functions are called but not in device rather they have been moved to a LogicalTreeNode associated with the design component.

Ephemeral nodes

In principle, clients should not reference chisel3.core directly. In the case of DontCare, we want to force references to the definition in the chisel3 package to avoid having DontCare defined as a user node.

Avoid explicitly creating entire DM flags array

This also constant-propagates through the async crossing.

This is now legal, since it is a WARL register.

This commit reduces the amount of Verilog that gets generated by about
200 KB.  It should have no semantic impact.  (The regmapper uses explicit
base addresses for each field, so changing the size of the array doesn't
affect the generated memory map.)

Support non-power-of-2 data scratchpads

Memory system features

This reverts commit a62230d8e886a766d1fb4d93dbc2b92275aa98c5.

What I believe is a bug in the Linux kernel (missing sfence.vma here
https://github.com/torvalds/linux/blob/master/arch/riscv/kernel/head.S#L123)
causes the kernel to fail to boot.

It's not necessary to match on the entire physical address of the PTE.
Instead, can match on the VPN subfields in TCAM fashion.  This reduces
the tag size from 35 bits to 19 for Sv39 with 38-bit physical addresses.

This allows MMIO loads to proceed at full throughput, rather than half.

Set misa.X bit, since CEASE instruction is nonstandard

* added customExtension to OMISA